TWI272512B - Apparatus, method and recording medium recorded with program for designing the layout of semiconductor IC - Google Patents

Apparatus, method and recording medium recorded with program for designing the layout of semiconductor IC Download PDF

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Publication number
TWI272512B
TWI272512B TW92127399A TW92127399A TWI272512B TW I272512 B TWI272512 B TW I272512B TW 92127399 A TW92127399 A TW 92127399A TW 92127399 A TW92127399 A TW 92127399A TW I272512 B TWI272512 B TW I272512B
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TW
Taiwan
Prior art keywords
layout
unit
parameter
value
capacitance
Prior art date
Application number
TW92127399A
Other languages
English (en)
Chinese (zh)
Other versions
TW200408983A (en
Inventor
Tetsuo Shimamura
Yasuhiro Shikakura
Original Assignee
Sanyo Electric Co
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Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200408983A publication Critical patent/TW200408983A/zh
Application granted granted Critical
Publication of TWI272512B publication Critical patent/TWI272512B/zh

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  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
TW92127399A 2002-11-18 2003-10-03 Apparatus, method and recording medium recorded with program for designing the layout of semiconductor IC TWI272512B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002333044A JP2004171076A (ja) 2002-11-18 2002-11-18 半導体集積回路のレイアウト設計装置、レイアウト設計方法及びレイアウト設計プログラム

Publications (2)

Publication Number Publication Date
TW200408983A TW200408983A (en) 2004-06-01
TWI272512B true TWI272512B (en) 2007-02-01

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ID=32697859

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92127399A TWI272512B (en) 2002-11-18 2003-10-03 Apparatus, method and recording medium recorded with program for designing the layout of semiconductor IC

Country Status (3)

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JP (1) JP2004171076A (ja)
CN (1) CN1316595C (ja)
TW (1) TWI272512B (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI398789B (zh) * 2009-06-05 2013-06-11 Askey Computer Corp 電路輔助設計方法及系統
CN102402633B (zh) * 2010-09-17 2013-11-06 中国科学院微电子研究所 一种建立参数化器件物理版图单元生成程序的方法
CN105335583B (zh) * 2015-11-30 2019-04-19 英业达科技有限公司 布局检查系统及其方法
JP7339548B2 (ja) * 2020-09-29 2023-09-06 東芝情報システム株式会社 レイアウト装置、レイアウト方法及びレイアウト用プログラム

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3156311B2 (ja) * 1991-10-31 2001-04-16 富士通株式会社 半導体論理セルライブラリ生成装置
JPH05218202A (ja) * 1992-02-07 1993-08-27 Matsushita Electric Ind Co Ltd 半導体素子のマスクデータ生成装置
JPH09325978A (ja) * 1996-06-05 1997-12-16 Oki Electric Ind Co Ltd Ｃａｄシステムにおけるレイアウト方法
US5896300A (en) * 1996-08-30 1999-04-20 Avant| Corporation Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets
US6295627B1 (en) * 1998-12-04 2001-09-25 Cypress Semiconductor Corporation Method and apparatus for the automated design of memory devices
US6480992B1 (en) * 1999-11-08 2002-11-12 International Business Machines Corporation Method, apparatus, and program product for laying out capacitors in an integrated circuit

Also Published As

Publication number Publication date
TW200408983A (en) 2004-06-01
CN1521833A (zh) 2004-08-18
CN1316595C (zh) 2007-05-16
JP2004171076A (ja) 2004-06-17

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