TWI268564B - Semiconductor device and fabrication method thereof - Google Patents

Semiconductor device and fabrication method thereof

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Publication number
TWI268564B
TWI268564B TW094111288A TW94111288A TWI268564B TW I268564 B TWI268564 B TW I268564B TW 094111288 A TW094111288 A TW 094111288A TW 94111288 A TW94111288 A TW 94111288A TW I268564 B TWI268564 B TW I268564B
Authority
TW
Taiwan
Prior art keywords
metallic
dielectric layer
layer
redistribution
opening
Prior art date
Application number
TW094111288A
Other languages
English (en)
Other versions
TW200636885A (en
Inventor
Yi-Hsin Chen
Feng-Lung Chien
Chao-Dung Suo
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW094111288A priority Critical patent/TWI268564B/zh
Priority to US11/373,693 priority patent/US7489037B2/en
Publication of TW200636885A publication Critical patent/TW200636885A/zh
Application granted granted Critical
Publication of TWI268564B publication Critical patent/TWI268564B/zh

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    • HELECTRICITY
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW094111288A 2005-04-11 2005-04-11 Semiconductor device and fabrication method thereof TWI268564B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW094111288A TWI268564B (en) 2005-04-11 2005-04-11 Semiconductor device and fabrication method thereof
US11/373,693 US7489037B2 (en) 2005-04-11 2006-03-10 Semiconductor device and fabrication method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094111288A TWI268564B (en) 2005-04-11 2005-04-11 Semiconductor device and fabrication method thereof

Publications (2)

Publication Number Publication Date
TW200636885A TW200636885A (en) 2006-10-16
TWI268564B true TWI268564B (en) 2006-12-11

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TW (1) TWI268564B (zh)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
KR100642643B1 (ko) * 2005-03-18 2006-11-10 삼성전자주식회사 내부회로의 전원/접지선들과 직접 접속되는 재배치된전원/접지선들을 갖는 반도체 칩들 및 그 제조방법들
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