TWI257103B - Enabling memory redundancy during testing - Google Patents

Enabling memory redundancy during testing

Info

Publication number
TWI257103B
TWI257103B TW092133681A TW92133681A TWI257103B TW I257103 B TWI257103 B TW I257103B TW 092133681 A TW092133681 A TW 092133681A TW 92133681 A TW92133681 A TW 92133681A TW I257103 B TWI257103 B TW I257103B
Authority
TW
Taiwan
Prior art keywords
during testing
memory redundancy
enabling memory
redundancy during
enabling
Prior art date
Application number
TW092133681A
Other languages
English (en)
Other versions
TW200519954A (en
Inventor
Michael R Ouellette
Jeremy Rowland
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200519954A publication Critical patent/TW200519954A/zh
Application granted granted Critical
Publication of TWI257103B publication Critical patent/TWI257103B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)
TW092133681A 2002-12-16 2003-12-01 Enabling memory redundancy during testing TWI257103B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/040473 WO2004061852A1 (en) 2002-12-16 2002-12-16 Enabling memory redundancy during testing

Publications (2)

Publication Number Publication Date
TW200519954A TW200519954A (en) 2005-06-16
TWI257103B true TWI257103B (en) 2006-06-21

Family

ID=32710251

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092133681A TWI257103B (en) 2002-12-16 2003-12-01 Enabling memory redundancy during testing

Country Status (8)

Country Link
EP (1) EP1620857B1 (zh)
JP (1) JP4215723B2 (zh)
CN (1) CN100552805C (zh)
AT (1) ATE448547T1 (zh)
AU (1) AU2002361765A1 (zh)
DE (1) DE60234394D1 (zh)
TW (1) TWI257103B (zh)
WO (1) WO2004061852A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409820B (zh) * 2009-02-18 2013-09-21 King Yuan Electronics Co Ltd Semiconductor Test System with Self - Test for Memory Repair Analysis

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7219275B2 (en) * 2005-02-08 2007-05-15 International Business Machines Corporation Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy
CN102411994B (zh) * 2011-11-24 2015-01-07 深圳市芯海科技有限公司 集成电路内置存储器的数据校验方法及装置
KR102038036B1 (ko) * 2013-05-28 2019-10-30 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치를 포함하는 반도체 시스템
JP6706371B2 (ja) * 2018-08-08 2020-06-03 シャープ株式会社 表示装置およびその制御方法
CN109857606A (zh) * 2019-02-12 2019-06-07 深圳忆联信息系统有限公司 避免损失良率的memory冗余位测试方法及装置
CN114267402B (zh) * 2021-11-22 2022-11-18 上海芯存天下电子科技有限公司 闪存的坏存储单元测试方法、装置、设备及存储介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819205A (en) * 1985-03-25 1989-04-04 Motorola, Inc. Memory system having memory elements independently defined as being on-line or off-line
EP0802541B1 (en) * 1996-04-18 2003-03-12 STMicroelectronics S.r.l. Method for detecting redundant defective addresses in a memory device with redundancy
KR100234377B1 (ko) * 1997-04-10 1999-12-15 윤종용 메모리 집적 회로의 리던던시 메모리 셀 제어회로 및 그 제어방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI409820B (zh) * 2009-02-18 2013-09-21 King Yuan Electronics Co Ltd Semiconductor Test System with Self - Test for Memory Repair Analysis

Also Published As

Publication number Publication date
CN1708808A (zh) 2005-12-14
AU2002361765A1 (en) 2004-07-29
EP1620857B1 (en) 2009-11-11
ATE448547T1 (de) 2009-11-15
WO2004061852A1 (en) 2004-07-22
EP1620857A1 (en) 2006-02-01
CN100552805C (zh) 2009-10-21
JP4215723B2 (ja) 2009-01-28
TW200519954A (en) 2005-06-16
EP1620857A4 (en) 2006-08-02
JP2006510156A (ja) 2006-03-23
DE60234394D1 (de) 2009-12-24

Similar Documents

Publication Publication Date Title
WO2004061602A3 (en) Method and apparatus for testing embedded cores
NO20040396L (no) Apparat for redundant multipleksing og ommultipreksing av programstrommer og beste ytelsesdata.
IS6393A (is) Aðferðir til að framleiða kísilörsmið, kísilskammtavírafylki og tæki, sem byggja á þessu
AU2003263748A8 (en) Nrom memory cell, memory array, related devices and methods
AU2003227596A1 (en) Method for the generation of memory effects on hair
NO20033454D0 (no) Prosess og anordning for damp/metan-reformering
GB2391358B (en) System on chip (soc) and method of testing and/or debugging the system on chip
AU3832297A (en) Semiconductor memory device having faulty cells
GB2406196B (en) Efficient read, write method for pipeline memory
IS7519A (is) 11-beta-hýdroxýstera vetnissviftir 1 hindrar nytsamlegir í meðferð við sykursýki, offitu og blóðfituröskun
NO20020434L (no) Fremgangsmåte og utstyr for å regulere trykk i brönn
DE69618833D1 (de) Rückschlagventil für einen aufblasbaren Körper
NO20030184D0 (no) System og fremgangsmåte for lokalisering og posisjonering av en ultralydgenerator for testing
AU2003266006A1 (en) Steam reforming process and apparatus
TWI265490B (en) Method and system for storing memory compressed data onto memory compressed disks
NO20005464L (no) Fremgangsmåte og anordning for tetning mellom brönnfôring og ventiltrekonnektor-konstruksjon
GB0019518D0 (en) Apparatus for testing computer memory
AU2001253822A1 (en) Apparatus and method for self testing programmable logic arrays
NO20000078D0 (no) Fremgangsmåte for å detektere seismiske hendelser, og for å detektere og korrigere geometri- og statikk-feil i seismiske data
NO20005173D0 (no) Gen som koder for heliomicin og anvendelse derav
TWI257103B (en) Enabling memory redundancy during testing
GB2404261B (en) Method and apparatus for memory redundancy and recovery from uncorrectable errors
EP1254532A4 (en) METHOD AND DEVICE FOR SELECTING THE BETTER CELL OF REDUNDANT CURRENTS WITHIN A CELL-ORIENTED ENVIRONMENT
DE60336614D1 (de) Redundanz -Schaltung und -Verfahren für Halbleiterspeicher
NO20033472D0 (no) Fremgangsmåte for å frembringe akustiske metrologidata og tilhörende anordning

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees