TWI256646B - Semiconductor readout circuit - Google Patents

Semiconductor readout circuit

Info

Publication number
TWI256646B
TWI256646B TW093138174A TW93138174A TWI256646B TW I256646 B TWI256646 B TW I256646B TW 093138174 A TW093138174 A TW 093138174A TW 93138174 A TW93138174 A TW 93138174A TW I256646 B TWI256646 B TW I256646B
Authority
TW
Taiwan
Prior art keywords
potential
readout circuit
data lines
semiconductor readout
data line
Prior art date
Application number
TW093138174A
Other languages
English (en)
Other versions
TW200525551A (en
Inventor
Nobuhiko Ito
Kaoru Yamamoto
Yoshimitsu Yamauchi
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200525551A publication Critical patent/TW200525551A/zh
Application granted granted Critical
Publication of TWI256646B publication Critical patent/TWI256646B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Landscapes

  • Read Only Memory (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW093138174A 2003-12-17 2004-12-09 Semiconductor readout circuit TWI256646B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003419757A JP4028840B2 (ja) 2003-12-17 2003-12-17 半導体読み出し回路

Publications (2)

Publication Number Publication Date
TW200525551A TW200525551A (en) 2005-08-01
TWI256646B true TWI256646B (en) 2006-06-11

Family

ID=34510645

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093138174A TWI256646B (en) 2003-12-17 2004-12-09 Semiconductor readout circuit

Country Status (5)

Country Link
US (1) US7057944B2 (zh)
EP (1) EP1544863B1 (zh)
JP (1) JP4028840B2 (zh)
KR (1) KR100645287B1 (zh)
TW (1) TWI256646B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7639543B2 (en) * 2006-12-18 2009-12-29 Spansion Llc High speed cascode circuit with low power consumption
JP4795994B2 (ja) * 2007-03-01 2011-10-19 シャープ株式会社 半導体記憶装置およびこれを備えた電子機器
JP2009016016A (ja) * 2007-07-09 2009-01-22 Samsung Electronics Co Ltd 半導体集積回路
US7755962B2 (en) * 2007-07-09 2010-07-13 Samsung Electronics Co., Ltd. Semiconductor memory devices, memory systems and computing systems including the same
JP5607870B2 (ja) * 2008-04-25 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル 電流センス回路及びこれを備えた半導体記憶装置
KR102643712B1 (ko) * 2016-10-26 2024-03-06 에스케이하이닉스 주식회사 센스 앰프, 이를 포함하는 비휘발성 메모리 장치 및 시스템

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0646513B2 (ja) 1989-07-12 1994-06-15 株式会社東芝 半導体記憶装置のデータ読出回路
US5113373A (en) 1990-08-06 1992-05-12 Advanced Micro Devices, Inc. Power control circuit
JPH05166365A (ja) 1991-12-12 1993-07-02 Toshiba Corp ダイナミック型半導体記憶装置
FR2694119B1 (fr) * 1992-07-24 1994-08-26 Sgs Thomson Microelectronics Circuit de lecture pour mémoire, avec recharge et équilibrage avant lecture.
JPH1011974A (ja) 1996-06-28 1998-01-16 Nkk Corp データライン電位安定化回路を有する半導体記憶装置
FR2801419B1 (fr) * 1999-11-18 2003-07-25 St Microelectronics Sa Procede et dispositif de lecture pour memoire en circuit integre
JP2002184188A (ja) * 2000-12-18 2002-06-28 Mitsubishi Electric Corp 半導体記憶装置
KR100402243B1 (ko) * 2001-09-24 2003-10-17 주식회사 하이닉스반도체 개선된 주변회로를 갖는 반도체 기억장치
JP2003242793A (ja) * 2002-02-15 2003-08-29 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置及びそのデータ読み出し方法

Also Published As

Publication number Publication date
JP2005182876A (ja) 2005-07-07
JP4028840B2 (ja) 2007-12-26
TW200525551A (en) 2005-08-01
US7057944B2 (en) 2006-06-06
KR20050061389A (ko) 2005-06-22
EP1544863A1 (en) 2005-06-22
US20050135161A1 (en) 2005-06-23
EP1544863B1 (en) 2007-01-24
KR100645287B1 (ko) 2006-11-15

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees