TWI249794B - Method of forming device isolation film in semiconductor device - Google Patents

Method of forming device isolation film in semiconductor device Download PDF

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TWI249794B
TWI249794B TW092133177A TW92133177A TWI249794B TW I249794 B TWI249794 B TW I249794B TW 092133177 A TW092133177 A TW 092133177A TW 92133177 A TW92133177 A TW 92133177A TW I249794 B TWI249794 B TW I249794B
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film
trench
threshold voltage
forming
ion implantation
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TW092133177A
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TW200501268A (en
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Cha-Deok Dong
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1249794 玫、發明說明： 【發明所屬之技術領域】 本發明是有關於在半導體裝置中形成裝置隔離膜之方 法。 【先前技術】 在半導體裝置中形成裝置隔離膜之一般過程包括形成光 阻圖案之步驟用於半導體基板上預先設定區域中形成裝置 隔離膜’並且藉由使用圖案作為遮罩經由實施蝕刻過程形 成溝渠。在此時，為了補償在蝕刻過程期間所發生的蝕刻 抽害，並且為了增加埋在溝渠内側氧化膜之附著力，而實 施氧化過程用於在所形成溝渠之内壁形成侧壁氧化膜，而 同時實施溝渠上部或底部角落之圓化（rounding)處理。 在此時在半導體基板上實施離子植入，經由此形成裝 置隔離膜之過程前之離子植入過程而控制臨界電壓 ，但是
【發明内容】 本發明被設計以解決 以上問題。本發明是有 關於在半導 89518 1249794 體裝置中形成裝置隔離膜之方法，其中此裝置之性能表現 可以藉由使得此用於控制臨界電壓而植入離子之區域能有 恆定離子濃度分佈而改善。 本發明之一觀點是提示一種方法在半導體裝置中形成裝 置隔離膜，包括以下步驟：實施離子植入用於控制在半導 骨豆基板表面上i臨界電壓；藉由在半導體基板上實施微影 過私而形成溝渠，以界定活性區與裝置隔離區；實施氧化 過程用於絕對防止此被植入以控制臨界電壓之離子擴散至 裝置隔離區，且在溝渠之侧壁形成側壁氧化膜；在活性區 上貫施離子植入以補償用於控制臨界電壓之離子，其藉由 氧化過程從活性區擴散至側壁氧化膜；以及藉由將氧化膜 埋在溝渠内而形成裝置隔離膜。 在上述根據本發明另一實施例在半導體裝置中形成裝置 隔離膜之方法中，當形成溝渠時，形成側壁氧化膜，而在 溝渠之上部或底部角落實施圓化處理，以增加此將被埋入 溝渠内 < 氧化膜之附著力，並且在同時形成膜至大約5〇a 至ιοοΑ範圍之厚度。 在上述根據本發明另一實施例在半導體裝置中形成裝置 隔離膜之方法中，在大約800。〇至95〇。〇範圍之溫度藉由乾 式氧化方法實施氧化過程。 在上述根據本發明另一實施例在半導體裝置中形成裝置 1¾離膜之方法中，在10 KevS 25 Κπ之能帶中藉由 ιοη/cm至iEl2ion/cm2之劑量實施氧化過程之後，在活性區 上貫施離子植入過程。 89518 1249794 在上述根據本發明另一實施例在半導體裝置中形成裝置 隔離膜之方法中’使用作為離子以植人料控制臨界電 壓。 本發明上述觀點與其他特性，將在以下之描述中並參考 所附圖式而說明。 【實施方式】 本發明將藉由較佳實施例並參考所附圖式詳細說明。炊 j，本發明之較佳實施例可以各種形式修正，並且本發明 I:園之分析不應受到以下所說明實施例之限制。本發明所 提供之較佳實施例是用於對熟習本發明技術之人士更清姑 地說明本發m，將圖中膜之厚度等放大以作更^ 《說明’並且在圖中使用相同的參考符號以辨識相同或ί 似-件。而且在本說明書中，，，某膜在另—膜上或在半導體 =板上”之片語意味著，某膜可以直接接觸另_膜或半導體 基板，或否則可將第三膜設置介於兩者之間。 至圖5為橫截面圖，用於說明根據本發明較佳實施例 在半導體裝置中形成裝置隔離膜之方法。 現在參考圖1，其說明在半導體 干孚把基板10芡整個上表面上形 成螢幕氧化膜11。 將半導體基板Η)分割成：區域（以下稱為"pM〇s區"），其 ，开:成P-型式電晶體；以及另—區域（以下稱為"NM〇s區"） 夫其上形成N -型式電晶體。此聲葚g ^ ,y 爱幕虱化膜（未圖示）作用 為、犮衝層以減少在稍後實施之離 一 雖于植入過程中之損害。在 ，精由濕式氧化法或乾式氧化法在大約7啊至90(rc 89518 1249794 範圍之溫度形成一直至厘泠广阁丄μ m x 2 且土 y予度靶圍大約5〇a至7〇a之螢幕氧 化膜（未圖示）。 其次’實施離子植人過程以形成井區域，並藉由使用微 影術過程而控制在各PM0S_刪區中之臨界電墨。圖^ 說明活性區⑷，即’此區在其上可植入離子以控制在NM0S 區中之臨界電壓。使用砰㈤或磷（P)作為離子植入摻雜 劑，用於控制在PMOS區域中之臨界電壓；並且使用硼（B) 作為離子植入摻雜劑，用於控制在NM〇Sg域中之臨界電 壓。其次，藉由蝕刻過程去除螢幕氧化膜丨i。 現在請參考圖2,在半導體基板1〇之整個上表面上（在其 中冗成上述過程）’依序形成：閘極氧化膜12、多晶矽膜Μ 以及墊氮化物膜16。 在溫度大約750°C至850°C之溫度實施乾式或濕式氧化過 程後，藉由在大約9〇〇它至910°C之溫度使用N2氣體實施回 火過程20至30分鐘而可形成閘極氧化膜12，其厚度範圍可 以為大約500A至700A。 可以在PH3氣體與例如SiH4或之矽源氣體之氛圍中 在大約0.1至3 torr之壓力下、在大約5〇〇°c至550°C之溫度， 藉由/儿和經摻雜多晶石夕膜一直至大約25〇A至5〇〇A範圍之 厚度，而形成多晶矽膜14。 此外，藉由低壓化學氣相沉積（以下稱為"Lp_CVDn)法， 可以形成厚度大約900A至2000A之墊氮化物膜16。 請參考圖3，在以上所產生物件之上部之上形成光阻圖案 (未圖示），並且然後藉由使用光阻圖案作為遮罩（未圖示） 89518 _〇 1249794 實施I虫刻過程，而形；^、、1泪^ I λ 义成/冓木（T)以界定裝置隔離區。 在形成溝渠（T)之時會綠4占云丨 宁焉犯蝕刻，以致於半導體基板10具有 大約75°或85。之特定斜率。 現在請參考圖4，經由氧化過程在溝渠（T)之側壁中形成 側壁氧化膜18。形成側壁氧化膜18以補償用於形成溝渠⑺ 之触刻過程期間對於此側壁所產生之敍刻損害，並且改善 埋在溝渠（τ)内部氧化η堇> _ t 4 、’ 、丨虱化艇之附耆力，而同時在溝渠（τ)之上部 或底部角WT)實施圓化處理。在此時，在大約卿。C至95〇 °c之溫度藉由乾式氧化法形成一直至大約5〇Α至贈厚度 :i、,i 土氧化腱18。在習知技術中，用於形成習知技術側壁 氧化膜是在大約1_1至⑽。c的溫度實施，因此，此所 植入用於控制在職⑽區中臨界電壓之硼離子藉由擴散至 側壁氧化膜18 ’而降低用於控制臨界電壓離予之密度。然 而’在本發明中，藉由將製程溫度降低至大約_。。至 °C，而可避免此用於控制臨界電壓所植入之硼離 側壁氧化膜18。 見在μ乡考圖5，為了補償此等删離子經由氧化過程從活 性區（Α)擴散至側壁氧化膜18，而在以上形成之物件中形成 之活性區（Α)上實施氧化植人過程。由㈣降低之氧化過程 《溫度’而減少所擴散卿子之數量，但難以完全避免爛 離子擴散。因此’為了補償由於氧化過程所擴散之蝴離子， 而在活性區上f施離子植人過程。此時之離子植人過程可 :用具有10至25 Kev能帶之1E1 i至1E12 iGn/em2劑量實施。 藉由濕式姓刻過程而去除塾氮化物膜16，並且藉由實施例 89518 -10- 1249794 如化學機賴光（CMP)過程等平坦化過程而形成裝置隔離 膜20。沉積具有極佳間隙填充性質之高密度電漿（匿)氧化 膜’而填人以上所產生結構之溝渠⑺中。並且然後將塾氮 化物膜16去除一直至多晶矽膜14曝露為止。 根據本發明之較佳實施例，、經由氧化過程降低過程溫 度，以形成至溝渠之側壁氧化膜，並且實施離子植入過程 以補償在氧化過程中擴散至侧壁氧化膜之離子，以致於在 其上植入用於控制臨界電壓之離子之活性區域之離子濃度 分佈可以為恆定，因此，可以改善裝置之性能表現。/又 如同以上說明，根據本發明’藉由降低過程溫度铖由氧 化過程以形成對溝渠之側壁氧化膜，並且實施離予植入過 程用於補償在氧化過程擴散至側壁氧化膜之離予。此在= 中植入用於控制臨界電壓之離子之活性區域之離子濃度= 佈可以妹定，因此可以獲得此效果以改善此裝置之= 表現。 择二以上根據較佳實施例說明，但應瞭解可以由熟習此 技術人士對本發明作各種改變與修正，而不會偏離本發明 與所附申請專利範圍之精神與範圍。 " 【圖式簡單說明】 圖1至圖5為橫截面圖，用於說明根據本發明較佳實施例 在半導體裝置中形成裝置隔離膜之方法。 【圖式代表符號說明】 10 半導體基板 11 螢幕氧化膜 89518 1249794 12 閘極氧化膜 14 多晶矽膜 16 氮化物膜 18 側壁氧化膜 20 裝置隔離膜 A 活性區 T 溝渠 89518 - 12 -

Claims (1)

1249794 拾、申請專利範園： 1- 種在半導體裝置中形成裝置隔離膜之方法，包括以下 步驟： 實施離子植入，用於控制在半導體基板表面上之臨界 電壓； 藉由在半導體基板上實施微影術過程以形成溝渠，以 界定活性區與裝置隔離區； …只施氧化過私用於絕對防止此等被植入以控制臨界電 之離子擴政至裝置隔離區，並且在溝渠側壁形成側壁 氧化膜； 在活性區上貫施離子植入，以補償用於控制臨界電壓 之離子其藉由氧化過程從活性區擴散至側壁氧化膜； 以及 藉由將氧化膜埋入溝渠中而形成裝置隔離膜。 2. 如申請專利範圍第1項之方法，其中 、當形成溝渠日寺，形幻則壁氧化月奠，而纟溝渠之上部或 底π角洛λ施圓化處理，以增加埋於溝渠中氧化膜之附 著力’在同時，並且在同時形成此膜至大約50人至1〇〇人 範圍之厚度。 3. 如申請專利範圍第1項之方法，其中 藉由在大、、、勺800 C至95〇。〇範圍的溫度，藉由乾式氧化 法實施氧化過程。 4·如申請專利範圍第1項之方法，其中 在貝她氧化過程後，在10 Kev至25 Kev之能帶中藉由 89518 1249794 1E11 ion/cm2至1E12 ion/cm2之劑量，在活性區上實施離子 植入過程。 5.如申請專利範圍第1項之方法，其中 使用硼作為離子而植入用於控制臨界電壓。 89518
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