TWI243456B - Image sensor chip package with level control and method for packaging the same - Google Patents

Image sensor chip package with level control and method for packaging the same

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Publication number
TWI243456B
TWI243456B TW092115559A TW92115559A TWI243456B TW I243456 B TWI243456 B TW I243456B TW 092115559 A TW092115559 A TW 092115559A TW 92115559 A TW92115559 A TW 92115559A TW I243456 B TWI243456 B TW I243456B
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TW
Taiwan
Prior art keywords
substrate
patent application
scope
item
image sensing
Prior art date
Application number
TW092115559A
Other languages
Chinese (zh)
Other versions
TW200428613A (en
Inventor
Cheng-Hsiang Hsu
Original Assignee
Cheng-Hsiang Hsu
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Publication date
Application filed by Cheng-Hsiang Hsu filed Critical Cheng-Hsiang Hsu
Priority to TW092115559A priority Critical patent/TWI243456B/en
Publication of TW200428613A publication Critical patent/TW200428613A/en
Application granted granted Critical
Publication of TWI243456B publication Critical patent/TWI243456B/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

An image sensor chip package with level control and a method for packaging the same are disclosed. The image sensor chip package mainly comprises a substrate, an image sensor chip and an adhesive compound, wherein an upper surface of the substrate defines a chip-attached area. The adhesive compound sticks a backside of the image sensor chip with the chip-attached area of the substrate. The substrate includes a plurality of metal pads on the chip-attached area and a plurality of inner fingers around the chip-attached area. The metal pads are same of a supporting height and are not covered by a solder mask to levelly control the image sensor chip during chip-attached process.

Description

12434561243456

【發明所屬之技術領域】 本發 關於一種 法0 明係有關於影像感測晶片之封裝技術,特別係有 水平控制之影像感測晶片封裝構造及其封裝方 【先前技術】 在半導體晶片之封裝領域中,影像感測晶片〔土㈣“ s^r^or chip〕係不同於一般積體電路晶片,無法以不透 先封膠體進行封裝,且影像感測晶片在一封裝構造内其水 :度比一般積體電路晶片的要求更高,習知積體電路晶片 f在封装構造内稍有傾斜,只要電性連接良好仍可視為良 ,但以相同之晶片傾斜度,影像感測晶片將會被判斷為· ί裝失敗’故影像感測晶片在封裝構造内的水平控制極為 重要’同時要兼顧其散熱性。 於我國專利公告第523 1 69號揭示有一種習知影像感測 晶片封裝構造,一影像感測晶片黏設於一具有凸緣層之基 板’其主要在於增進一透光層〔即透明玻璃〕於該凸緣層 之疋位’該凸緣層係具有沉坑,以供該透光層之定位設 置’對於該影像感測晶片與基板之黏固方式則未加以揭 示。習知黏晶材料可分為液態塗施之黏膠艘與固態黏附之 膠帶’而在影像感測晶片封裝構造中,常見係以膠帶黏固籲 該影像感測晶片,但散熱性較差且水平度維持有限,易受 防銲層〔solder mask〕與膠帶固化收縮影響,若以液態 塗施之黏膠體黏固該影像感測晶片則會引發嚴重的水平度[Technical field to which the invention belongs] The present invention relates to a method for packaging an image sensing chip, and particularly relates to a level-controlled image sensing chip packaging structure and its packaging method. [Previous technology] Packaging of semiconductor wafers In the field, the image sensing chip [土 ㈣ “s ^ r ^ or chip] is different from the general integrated circuit chip, and cannot be packaged with an impervious sealant, and the image sensing chip has water in a packaging structure: The degree of integration is higher than that of a general integrated circuit chip. It is known that the integrated circuit chip f is slightly inclined in the package structure. As long as the electrical connection is good, it can be regarded as a good one. It will be judged that the mounting failure 'so the level control of the image sensing chip in the package structure is extremely important' and it is necessary to take into account its heat dissipation. In China Patent Publication No. 523 1 69, a conventional image sensing chip package is disclosed. Structure, an image-sensing chip is adhered to a substrate with a flange layer, which is mainly to enhance a light-transmitting layer (that is, transparent glass) at the position of the flange layer, and the flange layer It has a sinker for the positioning of the light-transmitting layer. The method of fixing the image sensor chip and the substrate has not been revealed. The conventional sticky crystal material can be divided into a liquid-applied adhesive boat and a solid-state adhesive. In the packaging structure of image sensing chips, it is common to use adhesive tape to adhere to the image sensing chip, but the heat dissipation is poor and the level is limited. It is easily affected by the solder mask and the curing shrinkage of the tape. If the image sensor chip is fixed with a liquid-applied viscose, serious levelness will be caused.

第5頁 1243456 五、發明說明(2) 如第1圖所示,一種習知影像感測晶片封裝構造包含 有一基板10、一影像感測晶片20、一黏膠體30、銲線40、 一框壩50及一透明蓋60,該黏膠體30係黏固該影像感測晶 片20之背面22至該基板1〇之上表面11,並以銲線40電性連 接該影像感測晶片2 0至該基板1 〇之内接點1 4,利用該框壩 5 0與該透明蓋6 0密閉該影像感測晶片2 0,且該影像感測晶 片20之感測表面21應對準於該透明蓋60,以接收影像光 源,由於該黏膠體30係為液態或黏稠膠態塗施,該基板1〇 透過該黏膠體30對於該影像感測晶片20之水平控制度甚 差’在黏晶過程中黏附與壓合該影像感測晶片2 〇時該黏膠 體30尚未熱固化’該影像感測晶片2〇之感測表面21易產生 不受控制的傾斜,此外,該基板丨〇之上表面丨丨與下表面j 2 %知地係披覆有一防銲層1 3〔 s〇 1 der mask,俗稱之綠 漆〕,該防銲層1 3係顯露該些内接點丨4與外接點丨5,習知 該防銲層1 3之塗施方式係為液態印刷,導致該基板丨〇上表 面1 1具有較差的水平度,對於被封裝的該影像感測晶片2〇 亦會產生不被控制的水平影響。 【發明内容】 ,發明之主要目的係在於提供一種水平控制之影像感 t f 2 ί ’利用一基板之黏晶區形成有複數個金屬 Ϊ蓋片係具有一致之支撐高度且不被防銲層 f ^ I ^ ti撐一影像感測晶片之背面,以增進該被 封裝I像感測晶片之感測表面之水平控制度。 本發月之—人目的係在於提供一種水平控制之影像感Page 5 1243456 V. Description of the invention (2) As shown in Fig. 1, a conventional image sensing chip package structure includes a substrate 10, an image sensing chip 20, an adhesive 30, a bonding wire 40, and a frame. The dam 50 and a transparent cover 60 are used for fixing the back surface 22 of the image sensing chip 20 to the upper surface 11 of the substrate 10 and electrically connecting the image sensing chip 20 to the bonding wire 40 through The contact point 14 within the substrate 10 is used to seal the image sensing chip 20 with the frame dam 50 and the transparent cover 60, and the sensing surface 21 of the image sensing chip 20 should be aligned with the transparent cover. 60, to receive the image light source, since the viscose 30 is a liquid or viscous colloidal coating, the substrate 10 passes through the viscose 30 to control the level of the image sensing chip 20 very poorly. When the image sensing chip 20 is adhered and pressed, the adhesive 30 is not yet thermally cured. The sensing surface 21 of the image sensing chip 20 is prone to uncontrolled tilt. In addition, the substrate 丨 〇 upper surface 丨丨 It is covered with a solder mask 1 3 (s〇1 der mask, commonly known as green) ], The solder mask layer 1 3 reveals the internal contacts 丨 4 and the external contacts 丨 5, it is known that the application method of the solder mask layer 13 is liquid printing, which causes the upper surface of the substrate 11 to have The poor level will also have an uncontrolled level effect on the packaged image sensing chip 20. [Summary of the Invention] The main purpose of the invention is to provide a horizontally controlled image sense tf 2 ′ 'Using a sticky crystal region of a substrate, a plurality of metal cymbals cover sheets have a uniform support height and are not protected by the solder resist f ^ I ^ ti supports the back surface of an image sensing chip to improve the level control of the sensing surface of the packaged I image sensing chip. This Month of the Month-The purpose of man is to provide a level-controlled image sense

1243456 — -一 --— _____ 五'發明說明(3) 一 --— ^ L曰^封裝構造,利用一基板之黏晶區形成有複數個金屬 、導熱墊片,該些導熱墊片以貫孔連接至在該基板下 =之散熱金屬層,該些金屬墊片係接觸一影像感測晶片 之考面,以增進該影像感測晶片之散熱。 本發明之再一目的係在於提供一種影像感測晶片之封 =方法,在黏晶步驟中,一黏膠體黏固一影像感測晶片之 面與基板之上表面,利用一基板之黏晶區形成有複數 個^屬墊片,孩些金屬墊片係支撐與接觸該影像感測晶片 之责面,以水平控制該影像感測晶片之感測表面。 依本發明之水平控制之影像感測晶片封裝構造,其主 要包含有一基板、一影像感測晶片及一黏膠體,其中該基罐I 板係具有一上表面及一下表面,該基板之上表面係定義有 一黏晶區,该基板係包含有複數個内接點、複數個金屬墊 片及複數個外接點,該些内接點係設於該基板之上表面且. 沿該黏晶區之外周邊環繞排列,該些金屬墊片係設於該基 板之黏晶區」該些金屬墊片係具有一致之支撐高度且不被 防銲層所覆蓋,用以水平支撐該影像感測晶片,該些金屬 墊片係可與忒些内接點由同一金屬層形成,而該些外接點 係設於該基板之下表面並與對應之内接點電性導通,該影 像感測晶片係具有一感測表面及一對應背面,該影像感測船 晶片之背面係以该黏膠體固定於該基板之黏晶區並被該些 金屬墊片支撐與接觸,以水平控制該影像感測晶片之感測 表面’該影像感測晶片之感測表面設有複數個銲墊,該些 銲塾係電性導接至該基板之内接點,較佳地,該基板之上1243456 — -One-— _____ Five 'invention description (3) One --- ^ L ^ ^ package structure, a plurality of metal and thermal pads are formed by using the die-bonding region of a substrate. The hole is connected to a heat-dissipating metal layer under the substrate, and the metal pads contact the test surface of an image sensing chip to improve the heat dissipation of the image sensing chip. Another object of the present invention is to provide a method for sealing an image sensing wafer. In the die bonding step, a viscose is used to fix the surface of the image sensing wafer and the upper surface of the substrate, and uses the substrate's die bonding area. A plurality of metal gaskets are formed, and some metal gaskets support and contact the surface of the image sensing chip to control the sensing surface of the image sensing chip horizontally. The horizontally controlled image sensing chip package structure according to the present invention mainly includes a substrate, an image sensing chip, and a viscose. The base can I board has an upper surface and a lower surface, and the upper surface of the substrate. The system defines a sticky crystal region. The substrate includes a plurality of internal contacts, a plurality of metal pads, and a plurality of external contacts. The internal contacts are provided on the upper surface of the substrate and along the sticky crystal region. The outer perimeter is arranged in a circle, and the metal pads are arranged in the sticky crystal region of the substrate. The metal pads have a uniform support height and are not covered by the solder resist layer to horizontally support the image sensing chip. The metal pads can be formed from the same metal layer as the internal contacts, and the external contacts are disposed on the lower surface of the substrate and electrically connected to the corresponding internal contacts. The image sensing chip has A sensing surface and a corresponding back surface. The back surface of the image sensing boat wafer is fixed to the die attach region of the substrate with the adhesive and supported and contacted by the metal pads to horizontally control the image sensing wafer. Sensing surface ' Sensing the sensing surface of the image sensor wafer with a plurality of pads, the plurality of electrically conductive bonding based Sook connected to the contacts of the substrate, preferably, on the substrate

1243456 五、發明說明(4) 表面係形成有一框壩,以供接合一透明蓋或以填充透明膠 取代之,或者直接和微型攝影模組〔c〇mpact Camera1243456 V. Description of the invention (4) A frame dam is formed on the surface for attaching a transparent cover or replacing it with transparent plastic, or directly with a miniature camera module [c〇mpact Camera

Module,CCM〕之鏡頭〔Lens/Holder〕結合。 【實施方式】 參閱所附圖式’本發明將列舉以下之實施例說明。 依本發明之一具體實施例,請參閱第2圖,一種水平 控制之影像感測晶片封裝構造100係主要包含一基板110、 一影像感測晶片120及一黏膠體130,其中該基板110係具 有一上表面111及一下表面112,該基板n〇係可為一種具 有在上、下表面111、112形成有電路圖案之雙層或多層印 刷電路板或陶瓷電路板,該上表面111係定義有一黏晶區 11 3〔如第3圖所示〕,該基板11 0係包含有複數個内接點 11 4〔 inner f inger〕、複數個水平控制之金屬墊片11 5 〔metal pad〕及複數個外接點118〔outer finger〕。 請參閱第2及3圖,該些内接點114係設於該基板11〇之 上表面1 1 〇且沿該黏晶區11 3之外周邊環繞排列,該些水平 控制之金屬墊片11 5 a係設於該基板11 〇之黏晶區11 3,該些 金屬墊片115係具有一致之支撐高度且不被一防銲層Π9所 覆蓋,用以水平支撐該影像感測晶片1 2 〇,較佳地,該些 金屬墊片115係可包含有複數個支撐塾片115 a與散熱墊片 11 5b,該些支撐墊片11 5a係為放射狀對稱排列或其它對稱 或非對稱之任意可排膠形狀,以利該黏膠體1 3 〇之排膠, 該些散熱墊片11 5b係設於該黏晶區11 3之周邊,該些金屬 塾片115係可與該些内接點114由同一金屬層蝕刻形成,而Module, CCM] lens [Lens / Holder] combination. [Embodiment] The present invention will be described with reference to the attached drawings. According to a specific embodiment of the present invention, please refer to FIG. 2. A horizontally controlled image sensing chip package structure 100 mainly includes a substrate 110, an image sensing chip 120, and an adhesive 130, wherein the substrate 110 is It has an upper surface 111 and a lower surface 112. The substrate n0 may be a double-layer or multilayer printed circuit board or a ceramic circuit board with a circuit pattern formed on the upper and lower surfaces 111, 112. The upper surface 111 is defined There is a sticky crystal region 11 3 (as shown in FIG. 3). The substrate 110 includes a plurality of inner contacts 11 4 [inner f inger], a plurality of horizontally controlled metal pads 11 5 [metal pad], and A plurality of outer fingers 118 [outer finger]. Please refer to FIGS. 2 and 3. The internal contacts 114 are arranged on the upper surface 1 1 0 of the substrate 11 and are arranged in a circle along the periphery of the sticky region 11 3. The horizontally controlled metal pads 11 5 a is provided on the sticky crystal region 11 3 of the substrate 11 〇, the metal pads 115 have a uniform support height and are not covered by a solder mask Π 9 for horizontally supporting the image sensing chip 1 2 〇, preferably, the metal pads 115 may include a plurality of support pads 115 a and a heat sink 11 5b, and the support pads 11 5a are radially symmetrically arranged or other symmetrical or asymmetrical Any shape can be drained to facilitate the degumming of the viscose body 130. The heat sinks 11 5b are provided around the viscous crystal area 113, and the metal cymbals 115 can be connected to the inner portions. The dot 114 is formed by etching the same metal layer, and

1243456 五、發明說明(5) 該些外接點11 8係設於該基板11 0之下表面11 2並與對應之 内接點11 4電性導通,較佳地,該些外接點11 8係設於該基 板110之下表面112周邊,以擴大該基板11〇下表面112中央 可利用面積,在本實施例中,該基板1 1 〇另包含有一散熱 金屬層117於該基板下表面112之中央,而且該基板11〇具 有至少一以金屬電錢形成之貫孔116〔via〕,以連接至該 散熱金屬層117與該些散熱墊片115b,在本實施例中,該 些内接點114、金屬墊片115與散熱金屬層117均顯露於該 基板11 0表面鋪設之防銲層1 1 9,以達到該影像感測晶片 120之水平控制與散熱之功效,而該防銲層119係覆蓋該些龜 内接點114之間的基板110表面為較佳,在該基板上表面 111之該防銲層1 1 9係具有對應於該黏晶區11 3之開口,以 防止該黏膠體130之擴大溢膠並確保該些金屬墊片i15a之 水平支撐頂面為顯露,要特別留意的是,在一具體實施例 中,該防銲層11 9在該基板上表面1 11係具有一中央開口及 一周邊缺口 〔如第2圓所示〕,該防銲層11 9之中央開口係 對應於該基板11 0之黏晶區11 3,用以顯露該些金屬墊片 11 5 ’而該防銲層11 9之周邊缺口係環繞該上表面111之周 邊,以利一框壩150接合至該基板1 1〇且可阻擋該框壩15〇 在形成過程其廢膠〔f lash〕擴散流動至該些内接點114,_ 此外,該基板11 0在該防銲層丨丨9之周邊缺口處設有複數個 半穿孔161a,該些半穿孔丨6 la應不貫通至該基板11〇之下 表面11 2 ’以利該框壩1 5 〇之潜接結合。 請參閱第2圖,該影像感測晶片丨20係具有一感測表面 第9頁 1243456 五、發明說明(6) 1 2 1及一對應背面1 2 2,該影像感測晶片1 2 0之背面1 2 2係以 該黏膠體1 3 0固定於該基板1丨〇之黏晶區丨丨3並被該些支撐 塾片115a與該些導熱墊片1 i5b所支撐與接觸,以水平控制 該影像感測晶片1 2 0之感測表面1 2 1,該黏膠體1 3 0係可為 液態或黏稠膠態塗施之熱固性環氧膠,如銀膠或B階樹脂 膠’亦可為紫外線固化膠體,在該黏膠體丨3 〇黏固後,該 些金屬墊片115係接觸該影像感測晶片12〇之背面122並被 該黏膠體1 30密封,以達到良好水平控制該影像感測晶片 1 2 0以及增進該影像感測晶片丨2 〇之散熱性,該影像感測晶 片1 2 0之感測表面1 2 1周邊設有複數個銲墊1 2 3,該些銲墊 123係以銲線140電性導接至該基板11〇之内接點114 ,較佳鄱 地’該基板11 0之上表面111係形成有一框壩15〇〔 f rame dam〕,以供支撐一透明蓋16〇或微型攝影模組之鏡頭,此 外’在該影像感測晶片120之感測表面丨21可結合玻璃基板 或液晶〔圊未繪出〕,以組合成各式光學元件,如微型攝· 影模組〔Compact Camera Module, CCM〕。 因此’本發明之影像感測晶片封裝構造丨〇 〇係利用複 數個設於該基板黏晶區11 3之金屬墊片丨丨5,該些金屬墊片 115係具有一致之支撐高度且不被防銲層119覆蓋,以支撐 與接觸該影像感測晶片1 20之背面1 22,達到「在黏晶步驟鲁 水平控制該影像感測晶片120之感測表面121」之功效〔詳 述如后〕,再者,本發明之影像感測晶片封裝構造1〇〇係 利用複數個設於該基板黏晶區11 3之散熱墊片11 5 b,該些 散熱墊片115b並以貫孔116連接至該基板下表面112之該散1243456 V. Description of the invention (5) The external points 11 8 are arranged on the lower surface 11 2 of the substrate 11 0 and are electrically connected to corresponding internal contacts 11 4. Preferably, the external points 11 8 are It is arranged around the lower surface 112 of the substrate 110 to enlarge the usable area in the center of the lower surface 112 of the substrate 110. In this embodiment, the substrate 1 1 10 further includes a heat dissipation metal layer 117 on the lower surface 112 of the substrate. Center, and the substrate 11 has at least one through hole 116 [via] formed by metal electric money to be connected to the heat dissipation metal layer 117 and the heat sink pads 115b. In this embodiment, the internal contacts 114. The metal pad 115 and the heat-dissipating metal layer 117 are all exposed on the surface of the substrate 110 and the solder resist layer 1 1 9 is applied to achieve the level control and heat dissipation effect of the image sensing chip 120, and the solder resist layer 119 It is preferable to cover the surface of the substrate 110 between the inner contact points 114 of the turtles. The solder mask layer 1 1 9 on the upper surface 111 of the substrate has an opening corresponding to the sticky crystal region 11 3 to prevent the sticking. The expansion of the gel body 130 and ensure that the top surface of the horizontal support of the metal pads i15a is It is important to note that, in a specific embodiment, the solder mask layer 11 9 has a central opening and a peripheral notch on the upper surface 1 11 of the substrate (as shown by the second circle). The solder mask layer The central opening of 11 9 corresponds to the die-bonding region 11 3 of the substrate 11 0 to expose the metal pads 11 5 ′, and the peripheral notch of the solder resist 11 9 surrounds the periphery of the upper surface 111 to The frame dam 150 is bonded to the substrate 1 10 and can block the diffusion and flow of the waste rubber (f lash) to the internal contacts 114 during the formation process of the frame dam 150. In addition, the substrate 110 is A number of semi-perforations 161a are provided at the peripheral gap of the solder layer 丨 丨 9, and the semi-perforations 丨 6 la should not penetrate to the lower surface 11 2 ′ of the substrate 11 to facilitate the submerged bonding of the frame dam 1 5 . Please refer to FIG. 2. The image sensing chip 20 has a sensing surface. Page 9 1243456 V. Description of the invention (6) 1 2 1 and a corresponding back surface 1 2 2 The image sensing chip 1 2 0 The back surface 1 2 2 is fixed to the viscous region 丨 3 of the substrate 1 with the viscose 1 3 0 and is supported and contacted by the support tabs 115a and the thermal pads 1 i5b for horizontal control. The image sensing chip 1 2 0 has a sensing surface 1 21, and the viscose 1 30 is a liquid or viscous colloidal thermosetting epoxy glue, such as silver glue or B-stage resin glue. Ultraviolet-cured colloid. After the viscose is cured, the metal pads 115 contact the back surface 122 of the image sensing chip 120 and are sealed by the viscose 1 30 to achieve a good level to control the image sense. The test chip 1 2 0 and the heat dissipation of the image sensor chip 丨 2 〇 are improved. The sensing surface 1 2 1 of the image sensor chip 1 2 0 is provided with a plurality of pads 1 2 3 around the pads 123. It is electrically connected to the inner contact 114 of the substrate 110 with a bonding wire 140, and preferably, a frame dam is formed on the upper surface 111 of the substrate 110. 15〇 [frame dam] for supporting a lens with a transparent cover 160 or a miniature camera module, and in addition, 'the sensing surface of the image sensing chip 120 can be combined with a glass substrate or a liquid crystal [液晶 not shown ] To form various optical components, such as a Compact Camera Module (CCM). Therefore, the image sensing chip package structure of the present invention uses a plurality of metal pads provided on the substrate's die-bond region 11 13. The metal pads 115 have a uniform support height and are not The solder resist layer 119 is covered to support and contact the back surface 1 22 of the image sensing chip 120 to achieve the effect of "controlling the sensing surface 121 of the image sensing chip 120 horizontally in the step of sticking the crystals" (detailed later) ], Furthermore, the image sensing chip package structure 100 of the present invention uses a plurality of heat dissipation pads 11 5 b provided in the die attach region 11 3 of the substrate, and the heat dissipation pads 115 b are connected with the through holes 116. To the lower surface 112 of the substrate.

1243456 五、發明說明(7) 熱金屬層11 7,該些散熱墊片11 5b係傳導該影像感測晶片 120之產生熱量至該基板110之下表面112,達到「該影像 感測晶片1 2 0之散熱增益性」。 關於本發明之影像感測晶片封裝構造1 〇 〇之製造方法 詳述如后,請參閱第3及4A圖,提供一上述之基板11〇 ,該 基板110之黏晶區113設有複數個金屬墊片115 ,該些金屬 墊片115係具有一致之支撐高度且不被該防輝層119覆蓋, 該基板11 0係多個地一體形成於一大面積矩陣基板 〔matrix〕,以利量產製造;接著,請參閱第4B圖,利用 預模〔pr 〇-mol ding〕、射出成形或黏著結合方式將一框❿ 壩150形成在該基板110之上表面111周邊而不復蓋該些内 接點11 4、金屬墊片11 5,該框壩1 5 0之頂面係形成有複數 個凸點1 5 1,用以水平支撐一透明蓋1 6 0,由於該框壩1 5 p 係不影響該影像感測晶片1 2 0之光感特性,該框壩1 5 0係可 為任意顏色,如紅、綠、藍等豐富視覺的顏色,以達到供 顏色管理之彩色光學封裝;之後,請參閱第4C圖,提供一 * 上述影像感測晶片120,以一液態或黏稠膠態之黏膠體130 塗施於該基板11 0之黏晶區11 3,並在黏附該影像感測晶片 120之背面122之後,固化該黏膠體130,以熱固化或紫外 線固化黏固該影像感測晶片120之背面122與該基板110之鲁 黏晶區113,藉由該些金屬墊片115〔其支撐墊片11 5a〕支 撐該影像感測晶片1 20之背面1 22,以水平控制該影像感測 晶片1 2 0之感測表面1 2 1,避免該影像感測晶片1 2 0在黏晶 步驟產生傾斜,或者被該基板110之防銲層119影響其水平1243456 V. Description of the invention (7) The hot metal layer 11 7 and the heat sinks 11 5b conduct the heat generated by the image sensing chip 120 to the lower surface 112 of the substrate 110 to achieve "the image sensing chip 1 2 0 heat dissipation gain ". The manufacturing method of the image sensing chip package structure 1000 according to the present invention is described in detail below. Please refer to FIGS. 3 and 4A to provide a substrate 110 as described above, and a plurality of metals are provided in the die-bonding region 113 of the substrate 110. Gasket 115. These metal gaskets 115 have a uniform supporting height and are not covered by the anti-glow layer 119. The substrate 110 is integrally formed on a large area matrix substrate [matrix] for mass production. Manufacture; then, referring to FIG. 4B, a frame dam 150 is formed around the upper surface 111 of the substrate 110 without using a pre-mold [pr 〇-mol ding], injection molding, or adhesive bonding. The contact 11 4 and the metal gasket 11 5 have a plurality of bumps 1 5 1 formed on the top surface of the frame dam 1 50 to support a transparent cover 1 60 horizontally. Does not affect the light-sensing characteristics of the image sensing chip 120, the frame dam 150 can be any color, such as red, green, blue and other visually rich colors, to achieve color optical packaging for color management; Please refer to Figure 4C, provide a * The above image sensing chip 120, a liquid or adhesive The thick colloidal viscose 130 is applied to the viscous crystal region 11 3 of the substrate 110, and after the back surface 122 of the image sensing chip 120 is adhered, the viscose 130 is cured and cured by heat curing or ultraviolet curing. The back surface 122 of the image sensing wafer 120 and the glutinous crystal region 113 of the substrate 110 support the back surface 1 22 of the image sensing wafer 120 by the metal pads 115 (the supporting pads 11 5a), and are horizontal. Control the sensing surface 1 2 1 of the image sensing wafer 1 2 0 to avoid the image sensing wafer 1 2 0 from being tilted during the die-bonding step or being affected by the level of the solder mask 119 of the substrate 110

第11頁 1243456 五、發明說明(8) 度;之後,請參閱第4D圖,以複數個銲線14()或TAB〔Tape Automated Bonding〕引線等電性連接裝置電性連接該影 像感測晶片1 2 0之銲墊1 2 3與該基板1丨〇之内接點丨丨4,該些 鮮線14 0與該影像感測晶片1 2 0均不超過該框壩1 5 〇之頂 面;最後,請參閱第4E圖,在保持該框壩丨5〇内為鈍態氣 氛或真空態條件,一大面積透明蓋〗6 〇以熱固性膠體接合 於該框壩1 5 0頂面’以密封該影像感測晶片丨2 〇,由該框壩 1 5 0之凸點1 5 1水平控制該透明蓋1 6 〇,本實施例中,在切 割過程中以切割刀具70同時切割該基板丨1()、該框壩15〇及 該透明蓋160,以避免影響該影像感測晶片12〇之氣密狀 態,即為上述之影像感測晶片封裝構造丨〇 〇。Page 11 1243456 V. Description of the invention (8) degrees; then, referring to Figure 4D, electrically connect the image sensing chip with electrical connection devices such as a plurality of bonding wires 14 () or TAB (Tape Automated Bonding) leads. The solder pads 1 2 3 of 1 2 0 and the inner contacts 1 4 of the substrate 1 4, the fresh lines 14 0 and the image sensing chip 1 2 0 do not exceed the top surface of the frame dam 1 5 0 ; Finally, please refer to FIG. 4E. While maintaining the frame dam in a passive state or vacuum condition within 50 °, a large area of transparent cover is attached to the top surface of the frame dam with a thermosetting colloid. The image sensing wafer is sealed, and the transparent cover 16 is controlled by the bumps 151 of the frame dam 150. In this embodiment, the substrate is simultaneously cut by the cutting tool 70 during the cutting process. 1 (), the frame dam 150 and the transparent cover 160 to avoid affecting the airtight state of the image sensing chip 120, which is the above-mentioned image sensing chip package structure.

因此,本發明之影像感測晶片封裝構造及其製造方 法主要係運用在微型攝影模組〔Compact Camera Module,CCM〕,在切割單離成個別影像感測晶片封裝構 造1 0 0時〔如第2圖所示〕,該影像感測晶片1 2 〇係由該基 板110之金屬墊片115水平控制,且該透明蓋160係由該基 板11 0上框壩1 5 〇之凸點1 51水平控制,故該影像感測晶片 120之感測表面丨21與該透明蓋16〇在以熱固性膠體黏固過 程均能水平控制在該基板丨丨〇上,而兩者呈高度平行,有 效確保微型攝影模組〔CCM〕之製造品質。 ’ 為準’任何熟知此項技藝者,在不脫離本發明之精神和範 圍内所作之任何變化與修改,均屬於本發明之保護範圍。 本發明之保護範圍當視後附之申請專利範圍所界定者Therefore, the image sensing chip package structure and manufacturing method of the present invention are mainly applied to a miniature camera module (Compact Camera Module, CCM). When the cutting sheet is separated into individual image sensing chip package structures 100 (as in the first 2]], the image sensing chip 12 is controlled horizontally by the metal pad 115 of the substrate 110, and the transparent cover 160 is controlled by the bump 1 51 of the frame dam 1550 on the substrate 110. Control, so the sensing surface of the image sensing chip 120 and the transparent cover 16 can be horizontally controlled on the substrate during the thermosetting gel bonding process, and the two are highly parallel, effectively ensuring micro Manufacturing quality of photographic module [CCM]. Any changes and modifications made by anyone skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. The scope of protection of the present invention shall be defined by the scope of the attached patent application

第12頁 第 1 圖: S知景々像感測晶片封裝構造之截面示意 第 2 圖: 依據本發明,一種水平控制之影像感測 封裝構造之截面圖; 第 3 圓·· 依據本發明,該影像感測晶 片封裝構造 板上視圖 •,及 第4A至4E圖: 依據本發明之影像感測晶片 之封裝方法 製程中一 基板之截面示意圖 〇 元件符號簡單說明: ·· 10 基板 11 上表面 12 下表面 13 防銲層 14 内接點 丨5 外接墊 20 影像感測晶片2 1 感測表面 a 背面 30 黏膠體 40 銲線 50 框壩 60 透明蓋 7〇 切割刀具 100 影像感測晶片封裝構造 110 基板 111 上表面 112 下表面 113 黏晶區 114 内接點 115 金屬墊片 115a 支撐墊片 115b導熱墊片 116 貫孔 116a 半穿孔 117 散熱金屬層 118 外接墊 119 防銲層 120 影像感測晶片1 21 感測表面 122 背面 123 銲墊 130 黏膠體 140 鲜線 150 框壩 151 凸點 1 G 0 透明蕈Figure 1 on page 12: Schematic cross-sectional view of the package structure of the S-view image sensor chip. Figure 2: Cross-sectional view of a horizontally-controlled image sensing package structure according to the present invention. 3rd circle · According to the present invention, View of the image sensing chip package structure plate •, and FIGS. 4A to 4E: A schematic cross-sectional view of a substrate in the process of packaging the image sensing chip according to the present invention. 〇 Simple explanation of component symbols: ·· 10 Upper surface of substrate 11 12 Lower surface 13 Solder resist 14 Internal contact 5 External pad 20 Image sensing chip 2 1 Sensing surface a Back 30 Adhesive body 40 Welding wire 50 Frame dam 60 Transparent cover 70 Cutting tool 100 Image sensing chip package structure 110 Substrate 111 Upper surface 112 Lower surface 113 Sticky crystal region 114 Inner contact 115 Metal pad 115a Support pad 115b Thermal pad 116 Through hole 116a Half-perforated 117 Thermal metal layer 118 External pad 119 Solder resist layer 120 Image sensor chip 1 21 Sensing surface 122 Back surface 123 Pad 130 Adhesive body 140 Fresh line 150 Frame dam 151 Bump 1 G 0 Transparent mushroom

第13頁Page 13

Claims (1)

1243456 ---一t號92115559___年月曰 修正__ 六、申請專利範圍 厂一~… 1 【申請專利範圍】 A : T j . g ______.一一〜 、一種水平控制之影像感測晶片封裝構造,其包含: 一基板,其係具有一上表面及一下表面,該基板之上 表面係定義有一黏晶區,該基板係包含: 複數個内接點,其係設於該基板之上表面且沿該黏晶 區之外周邊排列; 複數個水平控制之金屬墊片,其係設於該基板之黏晶 區’該些金屬墊片係具有一致之支撐高度;及 複數個外接點,其係設於該基板之下表面,並與對應 _之内接點電性導通; 一影像感測晶片,其係具有一感測表面及一對應背 面’該影像感測晶片之背面係固定於該基板之黏晶區並 被該些金屬墊片支撐,以維持該影像感測晶片之感測表 面為水平,該影像感測晶片之感測表面設有複數個銲 墊,該些銲墊係電性導接至該基板之内接點;及 一黏膠體,黏固該影像感測晶片之背面於該基板之黏 晶區。 2、 如申請專利範圍第1項所述之水平控制之影像感測晶 片封裝構造,其中該基板係包含有一防銲層,該防銲層 _係不覆蓋該些金屬墊片。 3、 如申請專利範圍第2項所述之水平控制之影像感測晶 片封裝構造,其中該防銲層於該基板之上表面係形成有 一中央開口,用以顯露該黏晶區。 4、 如申請專利範圍第2項所述之水平控制之影像感測晶1243456 --- T No. 92115559___ said in the month of January __ VI. Patent application scope factory one ~ ... 1 [Patent application scope] A: T j. G ______. One by one ~, a level control image sensor chip The package structure includes: a substrate having an upper surface and a lower surface; the upper surface of the substrate is defined with a sticky crystal region; the substrate system includes: a plurality of internal contacts disposed on the substrate The surface and along the periphery of the sticky crystal region; a plurality of horizontally controlled metal pads, which are arranged in the sticky crystal region of the substrate; the metal pads have a uniform supporting height; and a plurality of external points, It is located on the lower surface of the substrate and is electrically connected to the corresponding internal contact points. An image sensing chip has a sensing surface and a corresponding back surface. The back surface of the image sensing chip is fixed to The sticky crystal region of the substrate is supported by the metal pads to maintain the sensing surface of the image sensing chip as a level. The sensing surface of the image sensing chip is provided with a plurality of pads. The pads are Electrically connected to the substrate An internal contact point; and an adhesive body for adhering the back surface of the image sensing chip to the adhesive region of the substrate. 2. The horizontally controlled image-sensing wafer package structure described in item 1 of the scope of the patent application, wherein the substrate includes a solder mask layer, and the solder mask layer does not cover the metal pads. 3. The horizontally controlled image-sensing wafer package structure described in item 2 of the patent application scope, wherein the solder mask layer has a central opening formed on the upper surface of the substrate to expose the die-bonding area. 4. The level-controlled image sensing crystal as described in item 2 of the scope of patent application 六、申請專利範圍 片封裝構造,其中該防銲層於該基板之上表面係形成有 一周邊缺口,其係環繞該上表面之周邊,以利一框壩接 合至該基板。 5、如申請專利範圍第1項所述之水平控制之影像感測晶 片封裝構造’其中該些金屬墊片係呈放射狀對稱排列或 其它可排膠形狀。 δ、如申請專利範圍第1項所述之水平控制之影像感測晶 片封裝構造,其中該些金屬墊片與該些内接點係由同一 金屬層形成。 7、 如申請專利範圍第1項所述之水平控制之影像感測晶龜 片封裝構造,其中該些金屬墊片係接觸該影像感測晶片 之背面並被該黏膠體密封。 8、 如申請專利範圍第1項所述之水平控制之影像感測晶 片封裝構造,其中該基板之下表面係形成有一散熱金屬 層。 9、 如申請專利範圍第丨或8項所述之水平控制之影像感測 晶片封装構造,其中該些金屬墊片係包含複數個導熱墊 片。 、’、 1 〇、如申請專利範圍第9項所述之水平控制之影像感測晶 片封裝構造,其中該些導熱墊片係以貫孔連接至該散_ 熱金屬層。 11、如申請專利範圍第1項所述之水平控制 片封装構造,其另包含有-框壩,其係形成該感基t 之上表面周邊,以供接合一透明蓋或一微型攝影模組6. Scope of patent application The chip package structure, wherein the solder resist layer has a peripheral notch formed on the upper surface of the substrate, which surrounds the periphery of the upper surface to facilitate a frame dam to be connected to the substrate. 5. The horizontally controlled image-sensing wafer package structure as described in item 1 of the scope of the patent application, wherein the metal pads are arranged symmetrically in a radial shape or other glue-dispensable shapes. δ. The level-controlled image-sensing wafer package structure described in item 1 of the scope of the patent application, wherein the metal pads and the internal contacts are formed of the same metal layer. 7. The horizontally controlled image-sensing wafer package structure as described in item 1 of the scope of the patent application, wherein the metal gaskets contact the back of the image-sensing wafer and are sealed by the adhesive. 8. The level-controlled image-sensing wafer package structure described in item 1 of the scope of the patent application, wherein a heat-dissipating metal layer is formed on the lower surface of the substrate. 9. The horizontally controlled image-sensing chip package structure as described in item 丨 or 8 of the scope of the patent application, wherein the metal pads include a plurality of thermally conductive pads. ′, 10, the horizontally controlled image sensing wafer package structure as described in item 9 of the scope of the patent application, wherein the thermally conductive pads are connected to the thermal metal layer with through holes. 11. The horizontal control chip package structure described in item 1 of the scope of patent application, further comprising a -frame dam, which forms the periphery of the upper surface of the sensing base t for joining a transparent cover or a miniature camera module 第15頁 1243456 ------ 92115559 六、申請專利範圍 之鏡頭。Page 15 1243456 ------ 92115559 VI. Patent application scope. 12、 如申請專利範圍第11項所i之水平控本厂义影像感測 晶片封裝構造,其中該框場之頂面係形成有複數個凸 點’用以支撐該透明蓋或微型攝影模組之鏡頭。 13、 如申請專利範圍第1項所述之水平控制之影像感測晶 片封裝構造,其中該黏膝體係為液態或黏稠膠態塗施 之熱固性膠體或紫外線固化膠體。 14、如申請專利範圍第1項所述之水平控制之影像感測晶 片封裝構造,其中該基板之該些外接點係設於該基板 之下表面周邊。 15、一種封裝基板,該基板係具有一上表面及一下表 面’該基板之上表面係定義有一黏晶區,該基板係包 含: 複數個内接點,其係設於該基板之上表面且沿該黏 晶區之外周邊環繞排列; 複數個金屬墊片,其係設於該基板之黏晶區,該些 金屬墊片係具有一致之支撐高度;及 複數個外接點,其係設於該基板之下表面,並與對 應之内接點電性導通。 _1 6、如申請專利範圍第丨5項所述之封裝基板,其中該基 板係包含有一防銲層,該防錄層係不覆蓋該些金屬塾 片° 1 7、如申請專利範圍第丨6項所述之封裝基板,其中該防 銲層於該基板之上表面係具有一中央開口,用以顯露12. The horizontally controlled factory-made image-sensing chip package structure as described in item 11 of the scope of the patent application, wherein the top surface of the frame field is formed with a plurality of bumps to support the transparent cover or micro-photographic module. Lens. 13. The horizontally controlled image-sensing wafer package structure as described in item 1 of the scope of the patent application, wherein the sticky knee system is a liquid or viscous colloidal applied thermosetting colloid or ultraviolet curable colloid. 14. The horizontally controlled image-sensing wafer package structure described in item 1 of the scope of the patent application, wherein the external points of the substrate are located around the lower surface of the substrate. 15. A package substrate, the substrate having an upper surface and a lower surface. The upper surface of the substrate defines a sticky crystal region. The substrate includes: a plurality of internal contacts, which are disposed on the upper surface of the substrate and Circumferentially arranged along the outer periphery of the sticky crystal region; a plurality of metal pads, which are provided in the sticky crystal region of the substrate, the metal pads have a uniform supporting height; and a plurality of external points, which are provided in The lower surface of the substrate is electrically connected to the corresponding internal contacts. _1 6. The package substrate as described in item 5 of the patent application scope, wherein the substrate system includes a solder resist layer, and the recording prevention layer does not cover the metal cymbals ° 1 7. As the patent application scope number 6 The package substrate according to the above item, wherein the solder resist layer has a central opening on the upper surface of the substrate for exposing .1243456 年 A 曰.1243456 A ---案號 92115559 六、申請專利範圍 該黏晶區。 1 8、如申請專利範圍第丨6項所述之封裝基板,其中該防 銲層於該基板之上表面係具有一周邊缺口,其係環繞 該上表面之周邊,以利一框壩接合至該基板。 1 9、如申請專利範圍第丨5項所述之封裝基板,其中該呰 金屬墊片係呈放射狀對稱排列或其它可排膠形狀。 20、如申請專利範圍第丨5項所述之封裝基板,其中該些 金屬墊片與該些内接點係由同一金屬層蝕刻形成。 2 1、如申請專利範圍第丨5項所述之封裝基板,其中該基 φ 板之下表面係形成有一散熱金屬層。 22、 如申請專利範圍第15或21項所述之封裝基板,其中 該些金屬墊片係包含複數個導熱墊片。 23、 如申請專利範圍第22項所述之封裝基板,其中該些 導熱墊片係以貫孔連接至該散熱金屬層。 24、 如申請專利範圍第丨5項所述之封裝基板,其中該基 板之上表面係形成有一框壩,以接合一透明蓋。 25、 如申請專利範圍第丨5項所述之封裝基板,其中該基 板之該些外接點係設於該基板之下表面周邊。 26、 一種水平控制之影像感測晶片封裝方法,其包含: _ 提供一基板,該係具有一上表面及一下表面,該基 板之上表面係包含有一黏晶區,該基板係定義有複數 個内接點、複數個水平控制之金屬墊片及複數個外接 點’其中該些内接點係設於該基板之上表面且沿該黏 晶區之外周邊環繞排列,該些金屬墊片係設於該基板--- Case No. 92115559 VI. Scope of patent application The sticky crystal region. 18. The package substrate as described in item 6 of the patent application scope, wherein the solder resist layer has a peripheral notch on the upper surface of the substrate, which surrounds the periphery of the upper surface to facilitate the bonding of a frame dam to The substrate. 19. The package substrate according to item 5 in the scope of the patent application, wherein the 呰 metal pads are arranged symmetrically in a radial shape or other glue-dispensable shapes. 20. The package substrate according to item 5 of the scope of the patent application, wherein the metal pads and the internal contacts are formed by etching the same metal layer. 2 1. The package substrate according to item 5 of the patent application scope, wherein a heat-dissipating metal layer is formed on the lower surface of the base φ plate. 22. The package substrate according to item 15 or 21 of the scope of patent application, wherein the metal pads include a plurality of thermal pads. 23. The package substrate according to item 22 of the scope of patent application, wherein the thermally conductive pads are connected to the heat dissipation metal layer by through holes. 24. The package substrate according to item 5 of the patent application scope, wherein a frame dam is formed on the upper surface of the substrate to join a transparent cover. 25. The package substrate according to item 5 of the scope of application for a patent, wherein the external points of the substrate are located around the lower surface of the substrate. 26. A horizontally controlled image sensing chip packaging method comprising: _ providing a substrate having an upper surface and a lower surface, the upper surface of the substrate including a sticky crystal region, and the substrate defining a plurality of Internal contact points, a plurality of horizontally controlled metal pads and a plurality of external contact points, wherein the internal contact points are arranged on the upper surface of the substrate and are arranged in a circle along the outer periphery of the sticky crystal region; the metal pads are On the substrate 1243456 六、申請專利範圍 之黏晶區,該些金屬墊片係具有一致之支撐高度,該 外接墊係設於該基板之下表面,並與對應之内接點電 性導通; 提供一影像感測晶片,該影像感測晶片係具有一感 測表面及一對應背面,該影像感測晶片之感測表面設 有複數個銲墊,以供電性導接至該基板之内接點;及 以一黏膠體黏固該影像感測晶片之背面至該基板之 黏晶區,藉由該些金屬墊片支撐該影像感測晶片之背 面’以水平控制該影像感測晶片之感測表面。 2 7、如申請專利範圍第2 6項所述之水平控制之影像感測 晶片封裝方法,其中該基板係包含有一防銲層,該防 銲層係不覆蓋該些金屬墊片。. 28、如申請專利範圍第26項所述之水平控制之影像感測 晶片封裝方法,其中該基板係·一體形成於一矩陣基 板0 29、 如申請專利範圍第26或28項所述之水平控制之影像 感測晶片封裝方法,其另包含步驟有:形成一框壩於 該基板之上表面周邊,以供接合一透明蓋或微型攝影 模組之鏡頭。 30、 如申請專利範圍第29項所述之水平控制之影像感測⑩ 晶片封裝方法,其中該框壩之頂面係形成有複數個凸 塊,且該透明蓋係大面積地覆蓋該框壩之頂面且被該 些凸點水平支樓。 31、 如申請專利範圍第26項所述之水平控制之影像感測1243456 VI. The patented sticky crystal area. The metal pads have the same support height. The external pads are located on the lower surface of the substrate and are electrically connected to the corresponding internal contacts. Provide an image sense. A sensing chip, the image sensing chip has a sensing surface and a corresponding back surface, the sensing surface of the image sensing chip is provided with a plurality of solder pads, and is electrically connected to the inner contacts of the substrate; and A viscose is used to fix the back surface of the image sensing chip to the sticky crystal region of the substrate, and the back surface of the image sensing chip is supported by the metal pads to control the sensing surface of the image sensing chip horizontally. 27. The horizontally controlled image-sensing chip packaging method as described in item 26 of the scope of the patent application, wherein the substrate includes a solder mask layer, and the solder mask layer does not cover the metal pads. 28. The level-controlled image sensing chip packaging method as described in item 26 of the scope of patent application, wherein the substrate is integrally formed on a matrix substrate 0 29. The level as described in item 26 or 28 of the scope of patent application The controlled image sensing chip packaging method further includes the steps of: forming a frame dam on the periphery of the upper surface of the substrate for bonding a lens of a transparent cover or a micro camera module. 30. The horizontally controlled image sensing ⑩ chip packaging method as described in item 29 of the scope of the patent application, wherein the top surface of the frame dam is formed with a plurality of bumps, and the transparent cover covers the frame dam in a large area. The top surface is horizontally supported by the bumps. 31. Level-controlled image sensing as described in item 26 of the scope of patent application 第18頁 1243456Page 18 1243456 第19頁Page 19
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