TW202224034A - Chip packaging method and chip package unit - Google Patents

Chip packaging method and chip package unit Download PDF

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Publication number
TW202224034A
TW202224034A TW110116416A TW110116416A TW202224034A TW 202224034 A TW202224034 A TW 202224034A TW 110116416 A TW110116416 A TW 110116416A TW 110116416 A TW110116416 A TW 110116416A TW 202224034 A TW202224034 A TW 202224034A
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Taiwan
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chip
substrate
chips
package
chip packaging
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TW110116416A
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Chinese (zh)
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顏豪疄
黃恒賫
永中 胡
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立錡科技股份有限公司
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Priority to US17/356,810 priority Critical patent/US11469162B2/en
Publication of TW202224034A publication Critical patent/TW202224034A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Chemical & Material Sciences (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The present invention discloses a chip packaging method, which includes: providing a substrate, which includes a plurality of substrate fingers; disposing a plurality of chips with a flip chip mounting on the substrate, and disposing a plurality of vertical heat conducting elements around each of the chips on the substrate; providing a packaging material, to enclose the substrate, the chips, and the vertical heat conducting elements; disposing a metal foil on the packaging material by an adhesive layer, to form a package structure; and cutting the package structure into a plurality of chip package units, one of the chip package units includes one of the chips, the vertical heat conducting elements around the chip, the cut substrate, and the cut metal foil.

Description

晶片封裝方法以及晶片封裝單元Chip packaging method and chip packaging unit

本發明係有關一種晶片封裝方法，特別是指一種封裝過程中，圍繞各晶片的多個垂直導熱結構分別熱連接底材以及金屬薄膜的晶片封裝方法。The invention relates to a chip packaging method, in particular to a chip packaging method in which a plurality of vertical heat-conducting structures surrounding each chip are thermally connected to a substrate and a metal film respectively during the packaging process.

先前技術中，參照圖1，其顯示美國專利案US 9984992的晶片封裝結構，其中包含兩晶片，下方晶片CH設置於底材110上，位於多個打線材100以及其他晶片所環繞形成的法拉第籠(Faraday cage)中，其形成一內部電磁保護結構。打線材100設置於底材110上，與底材110中線路相連，為封裝材料120所包覆，此為防電磁感擾設計。根據圖式，晶片CH散熱主要為往下透過底材110，而往上方的散熱途徑過長，且通過其他晶片，散熱效果有限。In the prior art, referring to FIG. 1 , it shows the chip package structure of US Pat. No. 9,984,992, which includes two chips. The lower chip CH is disposed on the substrate 110 and is located in a Faraday cage surrounded by a plurality of bonding wires 100 and other chips. (Faraday cage), it forms an internal electromagnetic protection structure. The wire rod 100 is disposed on the base material 110 , is connected to the circuit in the base material 110 , and is covered by the packaging material 120 , which is designed to prevent electromagnetic interference. According to the drawings, the heat dissipation of the chip CH mainly passes downward through the substrate 110 , and the heat dissipation path to the upper direction is too long, and through other chips, the heat dissipation effect is limited.

參照圖2，其顯示美國專利案US 9812402的晶片封裝結構。類似於圖1，圖2中打線材100與導電薄膜115環繞形成一法拉第籠，打線材100與底材110中線路相連，以形成防電磁感擾設計。然而，導電薄膜115之外又包含一金屬蓋130，此金屬蓋130雖可加強防電磁感擾，但反而造成晶片產生的熱被積聚在金屬蓋130內，其散熱效果不佳。Referring to FIG. 2 , it shows the chip package structure of US Pat. No. 9,812,402. Similar to FIG. 1 , in FIG. 2 , the wire 100 and the conductive film 115 are surrounded to form a Faraday cage, and the wire 100 is connected to the circuit in the substrate 110 to form an anti-electromagnetic interference design. However, the conductive film 115 also includes a metal cover 130 . Although the metal cover 130 can enhance the protection against electromagnetic interference, the heat generated by the chip is accumulated in the metal cover 130 and the heat dissipation effect is poor.

又參照圖3，其中顯示美國專利案US 7355289的晶片封裝結構，其中為加強晶片CH的熱傳導，在晶片CH上形成多個打線材100，以加強晶片CH散熱效果。其中打線材100外露於晶片CH上方的封裝材料120外側。此設計雖考慮散熱需求，但打線材100離晶片CH距離遠，且打線材100外露於封裝結構外的面積小，散熱效果有限。Referring to FIG. 3 again, the chip package structure of US Pat. No. 7,355,289 is shown, wherein in order to enhance the heat conduction of the chip CH, a plurality of bonding wires 100 are formed on the chip CH to enhance the heat dissipation effect of the chip CH. The bonding wire 100 is exposed outside the packaging material 120 above the chip CH. Although this design considers heat dissipation requirements, the wire bonding material 100 is far away from the chip CH, and the exposed area of the bonding wire material 100 outside the package structure is small, so the heat dissipation effect is limited.

參照圖4，其顯示美國專利案US 6023096的晶片封裝單元，其中位於晶片CH下方的底材110上具有一開孔，開孔下方設有一金屬薄膜120，封裝材料100充填於晶片CH下方、底材110的開孔、以及金屬薄膜120之間。此金屬薄膜120具有加強晶片CH散熱的功能，但此製程十分複雜。首先，底材110上需有開孔，金屬薄膜120設置於未完全硬化的封裝材料100上，其金屬薄膜120設置有相當難度。Referring to FIG. 4 , it shows the chip packaging unit of US Pat. No. 6,023,096, wherein the substrate 110 under the chip CH has an opening, a metal film 120 is disposed under the opening, and the packaging material 100 is filled under the chip CH and the bottom. between the openings of the material 110 and the metal thin films 120 . The metal film 120 has the function of enhancing the heat dissipation of the chip CH, but the process is very complicated. First, the substrate 110 needs to have openings, and the metal thin film 120 is disposed on the encapsulation material 100 which is not fully hardened. It is quite difficult to dispose the metal thin film 120 .

參照圖5，其顯示美國專利案US 6411507的晶片封裝單元，其中藉由依形狀複雜的金屬蓋140，其中金屬蓋140設計為與晶片CH熱接觸。其中金屬蓋140的形狀複雜，其加工有一定難度，金屬蓋140定位步驟中如何能正確放到位置，以達到與晶片CH間具有最佳熱接觸，也是另一技術困擾。此外，因製作技術限制，金屬蓋140有尺寸的下限，無法用於小尺寸的晶片封裝單元。Referring to FIG. 5 , it shows the chip package unit of US Pat. No. 6,411,507, wherein the metal cover 140 is designed to be in thermal contact with the chip CH by means of a metal cover 140 with a complex shape. The shape of the metal cover 140 is complex, and its processing is difficult. How to correctly place the metal cover 140 in the positioning step to achieve the best thermal contact with the wafer CH is another technical problem. In addition, due to the limitation of manufacturing technology, the metal cover 140 has a lower size limit and cannot be used for small-sized chip packaging units.

針對先前技術之缺點，本發明提供一晶片封裝單元，此設計具有過程簡單、製造容易、成本低、不受尺寸限制的優點。In view of the shortcomings of the prior art, the present invention provides a chip packaging unit, which has the advantages of simple process, easy manufacture, low cost, and no size limitation.

就其中一個觀點言，本發明提供了一種晶片封裝方法，以解決前述之困擾。此晶片封裝方法，包含：提供一底材(base material)，包含多個指狀接點(finger)；在底材上設置多個晶片以及圍繞各晶片的多個垂直導熱結構，其中晶片以覆晶(Flip chip)方式設置於底材上，並垂直導熱結構分別設置於對應之指狀接點上，並藉由指狀接點熱連接底材，以形成熱傳路徑；提供一封裝材料，封裝底材、晶片與垂直導熱結構；提供一黏著層，並藉由此黏著層將一金屬薄膜黏著於封裝材料上，以形成一封裝結構；以及切割封裝結構，以形成多個晶片封裝單元，其中各晶片封裝單元中包含各晶片、圍繞各晶片的對應之多個垂直導熱結構、切割後底材以及切割後金屬薄膜。各晶片封裝單元中，晶片所產生的熱，可藉由切割後底材與切割後金屬薄膜傳遞至晶片封裝單元外。垂直導熱結構可進一步加強從晶片至切割後底材與切割後金屬薄膜的熱傳效果。此外，本發明的方法中，可應用至各種尺寸的晶片封裝單元，無需特製的金屬蓋，也無需打線(Wiring)就可具有高效率的熱傳效果。In one aspect, the present invention provides a chip packaging method to solve the aforementioned problems. The chip packaging method includes: providing a base material including a plurality of finger contacts; disposing a plurality of chips on the base material and a plurality of vertical heat conducting structures surrounding each chip, wherein the chips are covered with The flip chip is arranged on the substrate, and the vertical heat-conducting structures are respectively arranged on the corresponding finger joints, and the finger joints are thermally connected to the substrate to form a heat transfer path; an encapsulation material is provided, packaging a substrate, a chip and a vertical heat conduction structure; providing an adhesive layer, and adhering a metal film on the packaging material by the adhesive layer to form a packaging structure; and cutting the packaging structure to form a plurality of chip packaging units, Each chip packaging unit includes each chip, a plurality of corresponding vertical heat conduction structures surrounding each chip, a cut substrate and a cut metal film. In each chip packaging unit, the heat generated by the chip can be transferred to the outside of the chip packaging unit through the diced substrate and the diced metal film. The vertical thermal conductive structure can further enhance the heat transfer effect from the wafer to the diced substrate and the diced metal film. In addition, the method of the present invention can be applied to chip packaging units of various sizes, without the need for a special metal cover, and without the need for wiring, to achieve high-efficiency heat transfer effects.

一實施例中，前述的在底材上設置晶片以及圍繞各晶片的垂直導熱結構的步驟中，包含：在底材上設置晶片之後、設置圍繞各晶片的垂直導熱結構；或者，在底材上設置垂直導熱結構之後、設置垂直導熱結構所圍繞的各晶片。使用者可依照製程的特性與需要，選擇晶片與垂直導熱結構的設置順序。In one embodiment, the aforementioned step of arranging the wafers on the substrate and the vertical thermal conduction structures surrounding the wafers includes: after disposing the wafers on the substrate, disposing the vertical thermal conduction structures surrounding the wafers; or, on the substrate After the vertical thermal conduction structure is arranged, each wafer surrounded by the vertical thermal conduction structure is arranged. The user can select the arrangement sequence of the chip and the vertical thermal conductive structure according to the characteristics and needs of the process.

一實施例中，垂直導熱結構接觸黏著層或金屬薄膜。垂直導熱結構可經由黏著層而連接至金屬薄膜、或者，垂直導熱結構可穿過黏著層而連接至金屬薄膜。In one embodiment, the vertical thermally conductive structure contacts the adhesive layer or the metal film. The vertical thermally conductive structure may be connected to the metal thin film through an adhesive layer, or the vertical thermally conductive structure may be connected to the metal thin film through the adhesive layer.

另一觀點中，本發明提供一種晶片封裝單元，其包含：一底材，其包含多個指狀接點；一晶片，以覆晶方式設置於底材上；多個垂直導熱結構，設置於指狀接點上並圍繞晶片；一封裝材料，封裝底材、晶片與垂直導熱結構；以及一黏著層與一金屬薄膜，金屬薄膜藉由黏著層以黏著於封裝材料上。In another aspect, the present invention provides a chip package unit, which includes: a substrate including a plurality of finger contacts; a chip disposed on the substrate in a flip-chip manner; and a plurality of vertical thermally conductive structures disposed on the substrate The finger contacts are on and around the chip; a packaging material, the packaging substrate, the chip and the vertical thermal conductive structure; and an adhesive layer and a metal film, and the metal film is adhered to the packaging material by the adhesive layer.

底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The following describes in detail with specific embodiments, when it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

本發明中的圖式均屬示意，主要意在表示各電路組成部分間之相互關係，至於形狀與尺寸則並未依照比例繪製。The drawings in the present invention are all schematic, mainly intended to show the relationship between the various circuit components, and the shapes and sizes are not drawn according to scale.

圖6A至6G、7A至7C，顯示本發明中兩個實施例的晶片封裝方法，7A至7C實施例的後續步驟也請參照圖6D至6G。其中，本發明之晶片封裝方法主要包括：包含：提供一底材110(圖6A、7A)，底材110包含多個指狀接點(Substrate finger)，此指狀接點可浮接或連接至底材110的其他線路，圖式中顯示指狀接點的側向剖面圖，從底材110垂直方向的視角上可呈現其指狀接點的幾何特徵；在底材110上設置晶片CH以及圍繞各晶片CH的多個垂直導熱結構205(圖6B、6C、7B、7C)，其中晶片CH以覆晶(Flip chip)方式設置於底材110上(晶片CH的訊號接點位於晶片CH與底材110間的空隙中)，並垂直導熱結構205設置於對應的指狀接點上，藉由指狀接點熱連接底材110，以形成晶片CH往下的熱傳路徑；提供一封裝材料100，封裝底材110、晶片CH與垂直導熱結構205，封裝材料100填入底材110、晶片CH與垂直導熱結構205間的空間(圖6D)，其中封裝材料100可包覆晶片CH的頂面、也可不包覆晶片CH的頂面(圖6D中顯示不包覆的實施例，圖8顯示封裝材料100包覆晶片CH頂面的實施例)；提供一黏著層210，並藉由此黏著層210將一金屬薄膜220黏著於封裝材料100上(圖6E)，以形成一封裝結構，此封裝結構包含晶片CH、垂直導熱結構205、底材110以及金屬薄膜220；以及切割封裝結構(圖6F、6G)，以形成多個晶片封裝單元250，其中各晶片封裝單元250中包含各晶片CH、圍繞各晶片的對應之多個垂直導熱結構205、切割後底材110A以及切割後金屬薄膜220A。各晶片封裝單元250中，晶片CH所產生的熱，可藉由切割後底材110A與切割後金屬薄膜220A傳遞至晶片封裝單元250外。垂直導熱結構205可進一步加強從晶片CH至切割後底材110A與切割後金屬薄膜220A的熱傳效果。此外，本發明的方法中，可應用至各種尺寸的晶片封裝單元，無需類似先前技術中特製的金屬蓋，也無需打線(Wiring)就可產生高效率的熱傳效果。FIGS. 6A to 6G and 7A to 7C show two embodiments of the chip packaging method of the present invention. Please refer to FIGS. 6D to 6G for the subsequent steps of the embodiments 7A to 7C. Wherein, the chip packaging method of the present invention mainly includes: including: providing a substrate 110 (FIG. 6A, 7A), the substrate 110 includes a plurality of finger contacts (Substrate fingers), the finger contacts can be floated or connected For other lines to the substrate 110, the figure shows a side cross-sectional view of the finger joints, and the geometrical characteristics of the finger joints can be presented from the perspective of the vertical direction of the substrate 110; the wafer CH is arranged on the substrate 110 and a plurality of vertical thermally conductive structures 205 surrounding each chip CH (FIGS. 6B, 6C, 7B, 7C), wherein the chip CH is disposed on the substrate 110 in a flip-chip manner (the signal contacts of the chip CH are located on the chip CH the gap between the substrate 110 and the substrate 110 ), and the vertical thermal conductive structure 205 is disposed on the corresponding finger joints, and the finger joints are thermally connected to the substrate 110 to form a heat transfer path down the chip CH; providing a The packaging material 100, the packaging substrate 110, the chip CH and the vertical thermally conductive structure 205, the packaging material 100 fills the space between the substrate 110, the chip CH and the vertical thermally conductive structure 205 (FIG. 6D), wherein the packaging material 100 can cover the chip CH The top surface of the chip CH may also not be covered with the top surface of the chip CH (the non-covered embodiment is shown in FIG. 6D , and the embodiment of the packaging material 100 covering the top surface of the chip CH is shown in FIG. 8 ); an adhesive layer 210 is provided, and by Thereby, the adhesive layer 210 adheres a metal film 220 on the packaging material 100 ( FIG. 6E ) to form a package structure including the chip CH, the vertical thermal conductive structure 205 , the substrate 110 and the metal film 220 ; and the dicing package structure (FIGS. 6F, 6G) to form a plurality of chip package units 250, wherein each chip package unit 250 includes each chip CH, a corresponding plurality of vertical thermally conductive structures 205 surrounding each chip, the diced substrate 110A, and the diced substrate 110A. Metal thin film 220A. In each chip packaging unit 250, the heat generated by the chip CH can be transferred to the outside of the chip packaging unit 250 through the diced substrate 110A and the diced metal film 220A. The vertical thermal conductive structure 205 can further enhance the heat transfer effect from the wafer CH to the diced substrate 110A and the diced metal film 220A. In addition, the method of the present invention can be applied to chip packaging units of various sizes, without the need for special metal covers like those in the prior art, and without the need for wire bonding to generate high-efficiency heat transfer effects.

前述的實施例圖式中，藉由單一個晶片封裝單元250以舉例說明本發明方法的步驟。一實施例中，底材110可為引線框架(Lead frame)。一實施例中，此引線框架可屬於一引線框架條(Lead frame stripe)的一部分。一實施例中，底材110可為一印刷電路板(printed circuit board, PCB)。一實施例中，此印刷電路板可屬於一大範圍電路板其中一部分。In the foregoing embodiment drawings, a single chip packaging unit 250 is used to illustrate the steps of the method of the present invention. In one embodiment, the substrate 110 may be a lead frame. In one embodiment, the lead frame may be part of a lead frame stripe. In one embodiment, the substrate 110 may be a printed circuit board (PCB). In one embodiment, the printed circuit board may be part of a wider range of circuit boards.

需說明的是，一般而言，引線框架通常用於四方平面無引腳 (quad flat no leads, QFN) 封裝與小型封裝(small outline package, SOP)；而印刷電路板通常用於球柵陣列 (ball grid array, BGA) 封裝、平面陣列 (land grid array, LGA) 封裝、晶片尺寸封裝(chip scale package, CSP)，此為本領域中具有通常知識者所熟知，在此不予贅述。It should be noted that, in general, lead frames are usually used in quad flat no leads (QFN) packages and small outline packages (SOP); while printed circuit boards are usually used in ball grid arrays ( Ball grid array (BGA) package, land grid array (LGA) package, and chip scale package (CSP) are well known to those skilled in the art, and will not be described here.

本發明的垂直導熱結構205，可為金屬材質，將晶片CH所產生的熱，通過切割後底材110A以及切割後金屬薄膜220A，以高效率地傳遞至各晶片封裝單元250外。其中，垂直導熱結構205可為不同幾何斷面的延伸結構，斷面例如圓形、橢圓形、方形、三角形、矩形等。The vertical heat conduction structure 205 of the present invention can be made of metal material, and the heat generated by the chip CH is efficiently transferred to the outside of the chip packaging units 250 through the cut substrate 110A and the cut metal film 220A. The vertical heat-conducting structure 205 may be an extension structure with different geometrical cross-sections, such as circular, oval, square, triangular, rectangular, and so on.

一實施例中，前述的在底材110上設置晶片CH以及圍繞各晶片CH的垂直導熱結構205的步驟中，可依需要而有不同的步驟。例如，在底材110上設置晶片CH之後、設置圍繞各晶片CH的垂直導熱結構205(圖6B、6C)。又例如，在底材110上設置垂直導熱結構205之後、設置垂直導熱結構205所圍繞的各晶片CH(圖7B、7C)。使用者可依照製程的特性與需要，選擇晶片CH與垂直導熱結構205的設置順序。In one embodiment, in the aforementioned steps of disposing the chips CH on the substrate 110 and the vertical thermally conductive structures 205 surrounding each chip CH, there may be different steps as required. For example, after the wafers CH are placed on the substrate 110, the vertical thermally conductive structures 205 surrounding each wafer CH are placed (FIGS. 6B, 6C). For another example, after the vertical thermally conductive structure 205 is disposed on the substrate 110, each wafer CH surrounded by the vertical thermally conductive structure 205 is disposed (FIGS. 7B and 7C). The user can select the arrangement sequence of the chip CH and the vertical thermal conductive structure 205 according to the characteristics and needs of the process.

切割後金屬薄膜220A與切割後底材110A的表面積，基本上等同於晶片封裝單元250的頂面積與底面積。如此，晶片封裝單元250可具有最大散熱面積的頂面積與底面積。操作晶片封裝單元250中晶片CH時，切割後金屬薄膜220A與切割後底材110A具有提升其中散熱效率、增加散熱面積、大幅降低熱集中、達到熱分散以及快速傳熱的效果。前述的黏著層210，可包含具高熱傳性能的黏著材料。切割後金屬薄膜220A藉由黏著層210黏固於晶片CH，晶片CH操作過程所產生的熱，可藉由黏著層210傳遞至切割後金屬薄膜220A，然後傳遞至晶片封裝單元250外。The surface areas of the diced metal film 220A and the diced substrate 110A are substantially equal to the top and bottom areas of the chip packaging unit 250 . In this way, the chip package unit 250 can have a top area and a bottom area with the largest heat dissipation area. When operating the chip CH in the chip packaging unit 250, the diced metal film 220A and the diced substrate 110A have the effects of improving the heat dissipation efficiency, increasing the heat dissipation area, greatly reducing heat concentration, achieving heat dispersion and rapid heat transfer. The aforementioned adhesive layer 210 may include an adhesive material with high heat transfer performance. The diced metal film 220A is adhered to the chip CH by the adhesive layer 210 , and the heat generated during the operation of the chip CH can be transferred to the diced metal film 220A through the adhesive layer 210 , and then to the outside of the chip packaging unit 250 .

本發明中，可根據封裝材料100是否包覆晶片CH的頂面(頂面為晶片CH中面對底材110的相反側)，來決定黏著層210是否接觸晶片CH。例如，當封裝材料100包覆晶片CH的頂面，黏著層210不接觸晶片CH的頂面，黏著層210接觸晶片CH頂面上的封裝材料100(圖8)，晶片封裝單元250中晶片CH產生的熱經過頂面上的封裝材料100、黏著層210而傳遞至切割後金屬薄膜220A。又例如，當封裝材料100不包覆晶片CH的頂面，黏著層210接觸晶片CH的頂面(圖6E)，晶片封裝單元250中晶片CH產生的熱可直接經過黏著層210傳遞至切割後金屬薄膜220A。In the present invention, whether the adhesive layer 210 contacts the chip CH can be determined according to whether the packaging material 100 covers the top surface of the chip CH (the top surface is the opposite side of the chip CH facing the substrate 110 ). For example, when the packaging material 100 covers the top surface of the chip CH, the adhesive layer 210 does not contact the top surface of the chip CH, the adhesive layer 210 contacts the packaging material 100 on the top surface of the chip CH ( FIG. 8 ), and the chip CH in the chip packaging unit 250 The generated heat is transferred to the diced metal film 220A through the packaging material 100 and the adhesive layer 210 on the top surface. For another example, when the packaging material 100 does not cover the top surface of the chip CH, and the adhesive layer 210 contacts the top surface of the chip CH ( FIG. 6E ), the heat generated by the chip CH in the chip packaging unit 250 can be directly transferred to the post-cut through the adhesive layer 210 Metal thin film 220A.

一實施例中，前述的切割封裝結構，以形成晶片封裝單元250的步驟中，包含：烘烤黏著層210以黏固金屬薄膜220於晶片CH上，加強金屬薄膜220與晶片CH間的黏固狀態。又一實施例中，又可在封裝結構上進行標印(Marking)，定位後續切割的晶片封裝單元(圖6F)，便於標示位置以進行切割。In one embodiment, the aforementioned step of dicing the package structure to form the chip package unit 250 includes: baking the adhesive layer 210 to adhere the metal film 220 on the chip CH to strengthen the adhesion between the metal film 220 and the chip CH state. In yet another embodiment, marking can be performed on the package structure to locate the chip package unit to be cut subsequently ( FIG. 6F ), so as to mark the position for cutting.

圖6G顯示封裝結構上切割為多個晶片封裝單元250，此切割為已知技術、故不詳述內容。FIG. 6G shows that the package structure is diced into a plurality of chip package units 250 , and this dicing is a known technology, so the details will not be described.

一實施例中，垂直導熱結構205接觸黏著層210或金屬薄膜220。垂直導熱結構205可經由黏著層210而連接金屬薄膜220；或者垂直導熱結構205可穿過黏著層210，而接觸至金屬薄膜220。使用者可依需要，而決定垂直導熱結構205是否接觸至金屬薄膜220。In one embodiment, the vertical thermal conductive structure 205 contacts the adhesive layer 210 or the metal film 220 . The vertical heat-conducting structure 205 can be connected to the metal film 220 through the adhesive layer 210 ; or the vertical heat-conducting structure 205 can pass through the adhesive layer 210 and be in contact with the metal film 220 . The user can decide whether the vertical thermal conductive structure 205 is in contact with the metal film 220 according to the needs.

本發明中的底材110、垂直導熱結構205以及金屬薄膜220間的熱接觸，可形成高效率熱傳的結構，其不同於先前技術中法拉第籠(Faraday cage)，本發明主要特徵之一為垂直導熱結構以及金屬薄膜可不接地，也可不連接訊號。The thermal contact between the substrate 110 , the vertical thermal conductive structure 205 and the metal film 220 in the present invention can form a structure with high heat transfer efficiency, which is different from the Faraday cage in the prior art. One of the main features of the present invention is that The vertical thermal conductive structure and the metal film may not be grounded or connected to the signal.

參照圖6E、8，本發明提供一種晶片封裝單元，其包含：一底材110，其包含多個指狀接點；一晶片CH，以覆晶(Flip chip)方式設置於底材110上；多個垂直導熱結構205，設置於指狀接點上並圍繞晶片CH；一封裝材料100，封裝底材110、晶片CH與垂直導熱結構205，封裝材料100填入底材110、晶片CH與垂直導熱結構205間的空間；以及一黏著層210與一金屬薄膜220，金屬薄膜220藉由黏著層210以黏固於封裝材料100上。6E, 8, the present invention provides a chip packaging unit, which includes: a substrate 110, which includes a plurality of finger contacts; a chip CH, disposed on the substrate 110 in a flip chip manner; A plurality of vertical thermal conductive structures 205 are disposed on the finger joints and surround the chip CH; a packaging material 100, the packaging substrate 110, the chip CH and the vertical thermal conductive structure 205, the packaging material 100 is filled into the substrate 110, the chip CH and the vertical thermal conductive structure 205. The space between the thermally conductive structures 205 ; and an adhesive layer 210 and a metal film 220 , the metal film 220 is adhered to the packaging material 100 by the adhesive layer 210 .

關於晶片封裝單元中各部分的詳細內容，請參見前述晶片封裝方法中的解釋與說明，在此不贅述。For the details of each part in the chip packaging unit, please refer to the explanations and descriptions in the aforementioned chip packaging method, which will not be repeated here.

本發明的晶片封裝方法或晶片封裝單元，可應用於球柵陣列封裝(Ball grid array package，BGA)、平面陣列封裝(Land grid array package，LGA)、晶片尺寸封裝(Chip scale package，CSP)、四方平面無引腳封裝(quad flat no leads, QFN)、或小型封裝(small outline package, SOP)。The chip packaging method or chip packaging unit of the present invention can be applied to ball grid array package (Ball grid array package, BGA), land grid array package (LGA), chip scale package (Chip scale package, CSP), Quad flat no leads (QFN), or small outline package (SOP).

參照圖9，一實施例中，當底材110包含引線框架時，各晶片封裝單元250又可設置於一外接電路板上，以連接對外訊號。Referring to FIG. 9 , in one embodiment, when the substrate 110 includes a lead frame, each chip package unit 250 may be disposed on an external circuit board for connecting to external signals.

以上已針對實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。The present invention has been described above with respect to the embodiments, but the above descriptions are only intended to facilitate the understanding of the content of the present invention by those skilled in the art, and are not intended to limit the scope of rights of the present invention. Within the same spirit of the present invention, various equivalent changes will be devised by those skilled in the art.

100:封裝材料 110:底材 110A:切割後底材 115:導電薄膜 120,220:金屬薄膜 130,140:金屬蓋 205:垂直導熱結構 210:黏著層 250:晶片封裝單元 220A:切割後金屬薄膜 CH:晶片 100: Encapsulation material 110: Substrate 110A: Substrate after cutting 115: Conductive film 120,220: Metal Thin Film 130,140: Metal cover 205: Vertical Thermal Conductivity Structure 210: Adhesive layer 250: Chip package unit 220A: Metal film after cutting CH: wafer

圖1至5顯示先前技術中晶片封裝單元的示意圖。 圖6A至6G、7A至7C顯示根據本發明兩實施例的晶片封裝方法示意圖。 圖8、9顯示根據本發明兩個實施例的晶片封裝單元的示意圖。 1 to 5 show schematic diagrams of chip packaging units in the prior art. 6A to 6G and 7A to 7C show schematic diagrams of chip packaging methods according to two embodiments of the present invention. 8 and 9 show schematic diagrams of chip packaging units according to two embodiments of the present invention.

100:封裝材料 100: Encapsulation material

110:底材 110: Substrate

205:垂直導熱結構 205: Vertical Thermal Conductivity Structure

210:黏著層 210: Adhesive layer

220:金屬薄膜 220: Metal Thin Film

CH:晶片 CH: wafer

Claims (13)

一種晶片封裝方法，包含： 提供一底材(base material)，包含多個指狀接點(finger)； 在該底材上設置多個晶片以及圍繞各該晶片的多個垂直導熱結構，該些晶片以覆晶(Flip chip)方式設置於該底材上，該些垂直導熱結構分別設置於對應之該指狀接點上； 提供一封裝材料，封裝該底材、該些晶片與該些垂直導熱結構； 藉由一黏著層，將一金屬薄膜黏著於該封裝材料上，以形成一封裝結構；以及 切割該封裝結構，以形成多個晶片封裝單元，其中各該晶片封裝單元中包含各該晶片、圍繞各該晶片的對應之該些垂直導熱結構、切割後該底材以及切割後該金屬薄膜。 A chip packaging method, comprising: providing a base material including a plurality of fingers; A plurality of chips and a plurality of vertical heat-conducting structures surrounding each of the chips are disposed on the substrate, the chips are disposed on the substrate in a flip-chip manner, and the vertical heat-conducting structures are respectively disposed on the corresponding on the finger contacts; providing an encapsulation material for encapsulating the substrate, the chips and the vertical thermally conductive structures; Adhering a metal film on the packaging material through an adhesive layer to form a packaging structure; and The packaging structure is cut to form a plurality of chip packaging units, wherein each of the chip packaging units includes each of the chips, the corresponding vertical thermally conductive structures surrounding each of the chips, the cut substrate and the cut metal film. 如請求項1所述之晶片封裝方法，其中該底材包含一引線框架(Lead frame)、或一印刷電路板。The chip packaging method of claim 1, wherein the substrate comprises a lead frame or a printed circuit board. 如請求項2所述之晶片封裝方法，其中當該底材包含該引線框架，各該晶片封裝單元設置於一外接電路板上。The chip packaging method of claim 2, wherein when the substrate includes the lead frame, each of the chip packaging units is disposed on an external circuit board. 如請求項2所述之晶片封裝方法，其中當該底材包含該引線框架，該引線框架位於一引線框架條(Lead frame stripe)中。The chip packaging method of claim 2, wherein when the substrate includes the lead frame, the lead frame is located in a lead frame stripe. 如請求項1所述之晶片封裝方法，其中該些垂直導熱結構為金屬材質。The chip packaging method of claim 1, wherein the vertical thermally conductive structures are made of metal. 如請求項1所述之晶片封裝方法，其中前述的在該底材上設置該些晶片以及圍繞各該晶片的該些垂直導熱結構的步驟中，包含：在該底材上設置該些晶片之後，設置圍繞各該晶片的該些垂直導熱結構；或者，在該底材上設置該些垂直導熱結構之後，設置該些垂直導熱結構所圍繞的各該晶片。The chip packaging method according to claim 1, wherein the step of disposing the chips on the substrate and the vertical thermally conductive structures surrounding the chips includes: after disposing the chips on the substrate , disposing the vertical heat-conducting structures surrounding each of the wafers; or, after disposing the vertical heat-conducting structures on the substrate, disposing each of the wafers surrounded by the vertical heat-conducting structures. 如請求項1所述之晶片封裝方法，其中切割後該金屬薄膜的表面積，基本上等同於該晶片封裝單元的頂面積。The chip packaging method according to claim 1, wherein the surface area of the metal film after cutting is substantially equal to the top area of the chip packaging unit. 如請求項1所述之晶片封裝方法，其中該黏著層接觸各該晶片，而將該金屬薄膜黏著於該封裝材料與各該晶片上。The chip packaging method of claim 1, wherein the adhesive layer contacts each of the chips, and the metal film is adhered to the packaging material and each of the chips. 如請求項1所述之晶片封裝方法，其中前述的切割該封裝結構，以形成該些晶片封裝單元的步驟中，更包含：在該封裝結構上進行標印(Marking)，以定位後續切割的該些晶片封裝單元。The chip packaging method according to claim 1, wherein the aforementioned step of dicing the package structure to form the chip package units further comprises: marking on the package structure to locate the subsequent cutting the chip packaging units. 如請求項1所述之晶片封裝方法，其中該些垂直導熱結構接觸該黏著層或該金屬薄膜。The chip packaging method of claim 1, wherein the vertical thermally conductive structures contact the adhesive layer or the metal film. 一種晶片封裝單元，包含： 一底材(base material)，其包含多個指狀接點(finger)； 一晶片，以覆晶(Flip chip)方式設置於該底材上； 多個垂直導熱結構，設置於該些指狀接點上並圍繞該晶片； 一封裝材料，封裝該底材、該晶片與該些垂直導熱結構；以及 一黏著層與一金屬薄膜，該金屬薄膜藉由該黏著層以黏固於該封裝材料上。 A chip packaging unit, comprising: a base material comprising a plurality of fingers; a chip, disposed on the substrate in a flip chip manner; a plurality of vertical thermally conductive structures disposed on the finger contacts and surrounding the chip; an encapsulation material encapsulating the substrate, the chip and the vertical thermally conductive structures; and an adhesive layer and a metal film, the metal film is fixed on the packaging material by the adhesive layer. 如請求項11所述之晶片封裝單元，其中該些垂直導熱結構接觸該黏著層或該金屬薄膜。The chip package unit of claim 11, wherein the vertical thermally conductive structures contact the adhesive layer or the metal film. 如請求項11所述之晶片封裝單元，可應用於球柵陣列(ball grid array, BGA)封裝、平面陣列 (land grid array, LGA) 封裝、晶片尺寸封裝(chip scale package, CSP) 、四方平面無引腳 (quad flat no leads, QFN) 封裝、或小型封裝(small outline package, SOP)。The chip package unit according to claim 11 can be applied to ball grid array (BGA) package, land grid array (LGA) package, chip scale package (CSP), square plane No leads (quad flat no leads, QFN) package, or small outline package (small outline package, SOP).
TW110116416A 2020-12-07 2021-05-06 Chip packaging method and chip package unit TW202224034A (en)

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