CN117855060B - Semiconductor packaging structure and method - Google Patents
Semiconductor packaging structure and method Download PDFInfo
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- CN117855060B CN117855060B CN202410257508.3A CN202410257508A CN117855060B CN 117855060 B CN117855060 B CN 117855060B CN 202410257508 A CN202410257508 A CN 202410257508A CN 117855060 B CN117855060 B CN 117855060B
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 157
- 238000000926 separation method Methods 0.000 claims description 26
- 239000000084 colloidal system Substances 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 21
- 238000001746 injection moulding Methods 0.000 description 8
- 238000000465 moulding Methods 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention provides a semiconductor packaging structure and a method, which relate to the technical field of semiconductor devices, wherein the method comprises the following steps: a plurality of alignment marks are formed in the edge area of the front surface of the strip. And then taking the alignment marks as references, and forming grid marks on the surface of the plastic package body on the strip. And then, attaching a metal cover on the surface of the plastic package body by taking the alignment mark and the grid mark as references. In this way, in the metal cover mounting process, the metal cover mounting position is accurate by means of the alignment of the boundaries of the meshes in the grid marks. After the metal cover is attached, the deflected metal cover can be rapidly observed through the boundary of the mesh where the metal cover is positioned, so that the position of the metal cover can be corrected in time. Avoid causing the wafer extravagant, help improving the encapsulation yield, reduce the encapsulation cost.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a semiconductor packaging structure and a semiconductor packaging method.
Background
The thermal output molded flip chip scale package (Heat Export Molding FLIP CHIP CHIP SCALE PACKAGE, HEMOLDFCCSP) is a flip chip scale package that is attached to an exposed metal cap and simultaneously filled with injection molding. The packaging form not only has the advantages of high integration, miniaturization and high density of the traditional packaging form, but also has higher structural strength and heat dissipation performance. The conventional package may be, for example, a Flip Chip scale package (FLIP CHIP CHIP SCALE PACKAGE, FCCSP), a Flip Ball grid array (Flip Chip Ball GRID ARRAY WITH HEAT SPREAD, HFCBGA) package having heat dissipation characteristics, or the like. Of course, HEmoldFCCSP packages also have correspondingly higher processing requirements.
Fig. 1 is a schematic diagram of a package structure of HEmoldFCCSP packages provided in the prior art. As shown in fig. 1, a HEmoldFCCSP package structure is shown, which includes an existing substrate 1, an existing solder ball 4 is distributed on the back surface of the existing substrate 1, and an existing plastic package body 2 and an existing metal cover 3 are sequentially disposed on the front surface of the existing substrate 1. Only a single package is shown in fig. 1, but in HEmoldFCCSP, the whole strip is required to be processed in batch, so that a plurality of metal covers are required to be attached to the top layer of the plastic package for heat dissipation.
Fig. 2 is a top view of a HEmoldFCCSP package provided in the prior art. As shown in fig. 2, the conventional metal cap 3 is required to be smaller in size than the package because the overall size of the package is small. In the step of attaching the existing metal cover 3, since there is almost no effective reference point on the front surface of the existing tape 5, there are often cases where the existing metal cover 3 is not accurately aligned and the attachment is deviated. And is not easily observed when the existing metal cover 3 is attached and deflected. Fig. 3 is a schematic top view of a prior art single package product with a metal lid deflected. For example, in fig. 3, deflection of the existing metal cover 3 is typically observed only when the full version of the existing strip has been cured and cut into individual packaged products. At this time, the existing tape is cut, so that the existing packaging product with the metal cover attached and deflected can only be scrapped, and serious wafer waste and cost loss are caused.
Disclosure of Invention
The present invention is directed to a semiconductor package structure and a method for overcoming the above-mentioned drawbacks of the prior art.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the invention is as follows:
In one aspect of the embodiment of the present invention, a semiconductor packaging method is provided, including: providing a strip comprising a product area having an array of products and an edge area located at a periphery of the product area; forming a plurality of alignment marks in the edge area of the front surface of the strip, wherein each alignment mark is positioned on a separation line between two adjacent columns or two adjacent rows of the product array; forming a plastic package body covering the product array in the product area of the strip; taking the alignment mark as a reference, and forming a grid mark on the surface of the plastic package body so that a product is distributed in each mesh of the grid mark; and (3) attaching a metal cover corresponding to each product on the surface of the plastic package body by taking the alignment mark and the grid mark as references.
Optionally, the edge region is an annular region surrounding the product region.
Optionally, each two alignment marks are used as a group, each group of alignment marks is distributed on opposite sides of the product area, and each group of alignment marks is located on the same separation line.
Optionally, with the alignment mark as a reference, a grid mark is formed on the surface of the plastic package body, including: and taking the alignment mark as a reference, forming a grid mark on the surface of the plastic package body by using laser, wherein the plurality of transverse line burning marks and the plurality of longitudinal line burning marks are intersected.
Optionally, the grid mark corresponds positively to the cut line of the strip in a direction perpendicular to the strip.
Optionally, after attaching the metal cover corresponding to each product on the surface of the plastic package body with reference to the alignment mark and the grid mark, the method further includes: the strip is cut along the dicing lanes to eliminate grid marks.
Optionally, after attaching the metal cover corresponding to each product on the surface of the plastic package body with reference to the alignment mark and the grid mark, the method further includes: acquiring position information of each metal cover in a mesh where each metal cover is positioned; comparing the position information with the target position information to determine an offset value of each metal cover; and if the offset value is greater than the threshold value, re-attaching the metal cover.
Optionally, acquiring the position information of each metal cover in the respective mesh comprises: acquiring edge contour lines of each metal cover in the direction perpendicular to the strip; and obtaining the position information of the metal cover in the mesh where the metal cover is positioned according to the distance information between the edge contour line of the metal cover and the boundary line of the mesh where the metal cover is positioned.
Optionally, if the offset value is greater than the threshold value, reattaching the metal cover includes: if the offset value is greater than the threshold value, the metal cover is re-attached before the colloid of the metal cover adhered to the plastic package body is solidified.
In another aspect of the embodiments of the present invention, a semiconductor package structure is provided, which is obtained by using any one of the above methods.
The beneficial effects of the invention include:
The invention provides a semiconductor packaging structure and a method, which enable the mounting position of a metal cover to be accurate by adding an alignment mark and a grid mark which can be used as references. After the metal cover is attached, the inclined metal cover can be rapidly observed through the boundary of the mesh where the metal cover is positioned, so that the position of the metal cover can be conveniently and timely corrected. Avoid causing the wafer extravagant, help improving the encapsulation yield, reduce the encapsulation cost.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a package structure of HEmoldFCCSP packages provided in the prior art;
FIG. 2 is a top view of a HEmoldFCCSP package provided in the prior art;
FIG. 3 is a schematic top view of a prior art single package product with a metal lid deflected;
Fig. 4 is a schematic flow chart of a semiconductor packaging method according to the present invention;
FIG. 5 is a schematic top view of a strip according to the present invention;
FIG. 6 is a schematic diagram illustrating a semiconductor packaging method according to the present invention;
FIG. 7 is a second schematic diagram illustrating a semiconductor packaging method according to the present invention;
FIG. 8 is a third schematic diagram illustrating a semiconductor packaging method according to the present invention;
FIG. 9 is a schematic diagram showing a semiconductor packaging method according to the present invention;
FIG. 10 is a schematic diagram illustrating a state of another semiconductor packaging method according to the present invention;
FIG. 11 is a second schematic diagram illustrating a semiconductor package method according to another embodiment of the present invention;
FIG. 12 is a third schematic diagram illustrating a semiconductor package method according to another embodiment of the present invention;
FIG. 13 is a schematic diagram showing a state of another semiconductor packaging method according to the present invention;
Fig. 14 is a schematic structural diagram of a semiconductor package structure according to the present invention.
Icon: 1-an existing substrate; 2-the existing plastic package body; 3-existing metal covers; 31-an existing first metal cover; 32-an existing second metal cover; 4-the existing solder balls; 5-existing strips; 6-an existing marker; 100-bands; 101-product area; 102-edge area; 103-a product to be packaged; 1031-a first product to be packaged; 1032-a second product to be packaged; 110-alignment marks; 120-plastic package body; 130-grid marking; 1301-first mesh; 1302-a second mesh; 131-cross line marking; 132-vertical line mark; 140-a metal cover; 1401-a first metal cap; 1402-a second metal cover; 150-cutting the path; 160-angle marks; 171-dashed line; 172-separation lines; 1721-a first separation line; 173-a first direction; 174-first distance; 175-second distance.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. It should be noted that, under the condition of no conflict, the features of the embodiments of the present invention may be combined with each other, and the combined embodiments still fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "center", "upper", "lower", "left", "right", "inner", "outer", etc. are directions or positional relationships based on those shown in the drawings, or those conventionally put in use of the product of the present invention, are merely for convenience of description and simplicity of description, and thus should not be construed as limiting the present invention.
Fig. 1 is a schematic diagram of a package structure of HEmoldFCCSP packages provided in the prior art, as shown in fig. 1, in HEmoldFCCSP packages, heat dissipation can be performed by attaching an existing metal cover 3 to a top surface of an existing plastic package 2. Because the HEmoldFCCSP packaging process requires batch processing of the whole existing strip, a plurality of existing metal covers 3 are often attached to the top surface of the existing plastic package 2. Because of the small size of the individual packaged products, the existing metal lids 3 may be smaller in size than the individual packaged products, which tends to exacerbate the problem of the subsequent prior art metal lids 3 being less observable when deflected.
Specifically, fig. 2 is a top view of a HEmoldFCCSP package provided in the prior art. As shown in fig. 2, an existing mark 6 is typically provided at each of the four corners of the front face of the existing strip 5. In the process of attaching the existing metal cover 3, the existing marks 6 at the four corners hardly play a reference role for the attachment of the existing metal cover 3. In particular, when the existing metal cover 3 is attached at a position distant from the existing mark 6, the existing mark 6 is more difficult to perform a reference function. This makes it difficult to perform effective alignment of the mounting of the existing metal cover 3, and often cases where the alignment of the existing metal cover 3 is inaccurate and the mounting is deviated. And after the existing metal cap 3 is attached to be deflected, it is difficult to observe which existing metal cap 3 is deflected because there is no effective reference around the existing metal cap 3.
Referring to fig. 2, at this time, a plurality of existing metal covers 3 have been attached to the top surface of the plastic package. Referring to fig. 2, a partially enlarged portion, an enlarged area of which is located at a position near the center of the top surface of the entire existing plastic package 2, is located at a distance from the existing mark 6 of the corner position, and two of the plurality of existing metal lids 3, an existing first metal lid 31 and an existing second metal lid 32, respectively, are shown in the enlarged area. It can be seen that the existing first metal cover 31 and the existing second metal cover 32 located in the enlarged area are significantly deflected, and it is difficult to observe that the existing first metal cover 31 and the existing second metal cover 32 are deflected by the existing mark 6 of the corner position.
Because the existing mark 6 at the corner position does not provide a valid reference, it is generally only when the full version of the existing strip 5 has completed curing and is cut into individual packaged products that it is possible to observe whether the existing metal lids 3 are deflected by the edges of the individual packaged products. It will be appreciated that the existing metal cap 3 is skewed relative to the existing metal cap 3, that the existing metal cap 3 is not skewed, meaning that the existing metal cap 3 is centered on the top surface of the individual packaged product, and that the edge lines of the existing metal cap 3 are parallel to the edge lines of the existing plastic package 2 in a top view.
Specifically, fig. 3 is a schematic top view of a single package product with a metal lid deflection as provided in the prior art. Fig. 3 shows that the existing metal cover 3 in a single packaged product is deflected in different situations: fig. 3 (a) shows a case where the existing metal cover 3 in the single packaged product is inclined at an angle to the existing plastic package 2. Or (b) in fig. 3 shows a case where the existing metal cover 3 in the single packaged product is not evenly covered with the existing plastic package body 2, for example, in a top view of fig. 3, the existing metal cover 3 in (b) is covered at a position closer to the upper side edge of the existing plastic package body 2. Or (c) in fig. 3 shows another uneven case in which the existing metal cover 3 covers a position closer to the upper left corner of the existing plastic package 2. Of course, there are other possibilities for the positional relationship between the existing metal cover 3 and the existing plastic package 2, and the present invention is not limited to this.
Further, as is clear from the above description of each case of fig. 3, since the dicing of the existing tape is already completed at this time, the packaged product of the existing metal cap 3 mounting deflection cannot be corrected, and only the discard process can be performed, resulting in serious wafer waste and cost loss.
Based on the above-mentioned problems in HEmoldFCCSP packages, an aspect of an embodiment of the present invention provides a semiconductor packaging method. Fig. 4 is a flow chart of a semiconductor packaging method according to the present invention, and referring to fig. 4, the method includes:
Step 10: a strip is provided that includes a product region having an array of products and an edge region located at a periphery of the product region.
Fig. 5 is a schematic top view of a strip according to the present invention. Referring to fig. 5, a strip 100 is first provided, a plurality of products (for convenience of distinction, the products at this time are called products to be packaged 103 because the packaging is not completed) are provided on the strip 100, and the plurality of products to be packaged 103 are distributed by an array to form a product array. For example, as shown in fig. 5, the number of rows of the product array on the strip is 6 rows and the number of columns is 8 columns, and the total number of the products 103 to be packaged is 48.
For ease of understanding, as shown in fig. 5, the area of the strip 100 on which the product array is distributed is referred to as the product area 101. Correspondingly, the peripheral area of the strip 100 outside the product area 101 is defined as the edge area 102. For example, the boundaries of the product region 101 and the edge region 102 directly collide, in other words, the product region 101 and the edge region 102 may be separated by a dashed line 171 in fig. 5. It should be understood that the dashed line 171 is a virtual reference line that is merely used to illustrate the inventive arrangements, and thus the dashed line 171 may not be embodied in the actual structure of the strip 100.
Step 20: a plurality of alignment marks are formed in the edge area of the front surface of the strip, and each alignment mark is positioned on a separation line between two adjacent columns or two adjacent rows of the product array.
Fig. 6 is a schematic diagram illustrating a state of a semiconductor packaging method according to the present invention. Referring to fig. 6, a plurality of alignment marks 110 are formed on the front surface of the strip 100, and the plurality of alignment marks 110 are distributed in the edge region 102.
For ease of description, as shown in FIG. 6, separation lines 172 are introduced for separating adjacent rows or columns in the array of products (separation lines 172 are virtual reference lines that are merely used to understand aspects of the invention. Separation lines 172 may not be embodied in the actual structure of strip 100). Specifically, referring to the partially enlarged portion in fig. 6, two of the plurality of products to be packaged 103, respectively, a first product to be packaged 1031 and a second product to be packaged 1032 are shown therein. The first product to be packaged 1031 is located at the intersection of column 4 and row 2 and the second product to be packaged 1032 is located at the intersection of column 5 and row 2. There is a first separation line 1721 (belonging to one of the plurality of separation lines 172) between the first product to be packaged 1031 and the second product to be packaged 1032, and a first distance 174 from the first separation line 1721 to the first product to be packaged 1031 is equal to a second distance 175 from the first separation line 1721 to the second product to be packaged 1032. In other words, the first separation line 1721 is located at a center line between the first product to be packaged 1031 and the second product to be packaged 1032. Accordingly, the first separation line 1721 is located at a center line position between the 4 th column of products to be packaged and the 5 th column of products to be packaged. By analogy, any one of the separation lines 172 is located at the centerline of two adjacent columns or two adjacent rows of products to be packaged.
With continued reference to fig. 6, each alignment mark 110 is located on a separation line 172 between two adjacent columns or rows in the product array. Therefore, the rows and columns of the product array can be marked by the plurality of alignment marks 110. Therefore, on one hand, a datum point can be provided for the formation of the subsequent grid marks, so that the positions of the grid marks are accurate, and on the other hand, the accurate mounting and alignment of the metal cover can be facilitated.
Step 30: and forming a plastic package body covering the product array in the product area of the strip.
Fig. 7 is a second schematic diagram of a semiconductor packaging method according to the present invention. Referring to fig. 7, in order to mold the products to be packaged on the strip 100, a molding body 120 may be formed in a product area of the strip 100 by a package injection molding process, so that the molding body 120 covers all the products to be packaged. Because the plastic package 120 covers all the products to be packaged, as shown in fig. 7, the plastic package 120 completely shields all the products to be packaged in a top view.
In the plastic package process, a plastic package body mold can be used for facilitating the molding of the plastic package body. The specific plastic packaging process comprises the following steps: the injection molding area of the plastic package body mold can be made to completely cover all the products to be packaged. It should be noted that the boundary of the injection molding region is located inside all the alignment marks 110, so as to avoid the injection molding region covering the alignment marks 110.
The plastic package 120 covering all the products to be packaged is then formed by injection molding in a plastic package mold. After the molded body 120 is formed, the mold of the molded body may be removed, as shown in fig. 7, and finally the molded body 120 is left on the strip.
Since the boundary of the injection molding area is located at the inner sides of all the alignment marks 110, after the plastic package body 120 is formed by injection molding, all the alignment marks 110 can be exposed relative to the plastic package body 120, so that the alignment reference function is conveniently achieved. It should be appreciated that the plastic package 120 may be formed of a plastic material known in the art, such as epoxy, etc.
Step 40: and taking the alignment mark as a reference, and forming a grid mark on the surface of the plastic package body so that one product is distributed in each mesh of the grid mark.
Fig. 8 is a third schematic state diagram of a semiconductor packaging method according to the present invention. With reference to fig. 6, 7 and 8, the positional relationship between the separation line 172 and the products 103 to be packaged in two adjacent columns or two adjacent rows has been clarified through the foregoing step 20, and the positions of the plurality of alignment marks 110 are also determined by means of the separation line 172, so that the plurality of alignment marks 110 can accurately locate the columns and rows in the product array. At this time, the grid marks 130 on the surface of the plastic package may be formed by using the plurality of alignment marks 110 as reference points.
Referring to fig. 8, the grid mark 130 includes a plurality of transversal marks 131 and a plurality of longitudinal marks 132 intersecting each other. Wherein, in the top view direction, the horizontal line marks 131 may coincide with the separation lines 172 between the adjacent two rows of products 103 to be packaged, and the vertical line marks 132 may coincide with the separation lines 172 between the adjacent two columns of products 103 to be packaged. The position of the product 103 to be packaged can be accurately marked based on the mesh obtained by the intersection of the transverse line marks 131 and the longitudinal line marks 132, i.e., one product 103 to be packaged is distributed in each mesh. For example, in fig. 8, a portion of the products 103 to be packaged covered by the molding body 120 in column 1 of the product array is shown, each of the products 103 to be packaged shown being located in one of the meshes.
Although the product array is covered by the molding compound 120, the alignment marks 110 that can mark the rows and columns in the product array are still exposed, so the grid marks 130 formed by using the alignment marks 110 as reference points can accurately mark the rows and columns in the product array. The position of each product 103 to be packaged can be accurately calibrated even through meshes. This serves as a critical reference for the grid mark 130 during subsequent attachment of the metal cover.
Step 50: and (3) attaching a metal cover corresponding to each product on the surface of the plastic package body by taking the alignment mark and the grid mark as references.
Fig. 9 is a schematic diagram illustrating a state of a semiconductor packaging method according to the present invention. After forming the grid marks 130 through step 40, as shown in fig. 9, when attaching the metal caps 140, the alignment marks 110 and the grid marks 130 may be referred to at the same time, and one metal cap 140 may be attached in each mesh of the grid marks 130. And since the positional relationship between the grid mark 130 and the product array has been clarified in step 40, the mounting position of the metal cap 140 can be determined by using the mesh boundary to which the metal cap 140 is to be mounted during the mounting of the metal cap 140. After the mounting of the metal cap 140 is completed, the metal cap 140 and the product to be packaged, which are positioned in the same mesh, are aligned in a top view.
Specifically, referring to the partially enlarged portion in fig. 9, two of the plurality of metal lids 140, a first metal lid 1401 and a second metal lid 1402, respectively, are shown. The first metal cover 1401 is located at a position where the 3 rd column intersects with the 4 th row, and the second metal cover 1402 is located at a position where the 4 th column intersects with the 4 th row. In the process of attaching the first metal cover 1401, the approximate position of the first metal cover 1401 to be attached may be determined as the first mesh 1301 of the grid mark 130, and then the first metal cover 1401 may be attached in the first mesh 1301 with reference to the boundary line around the first mesh 1301. Since the peripheral boundary line of first mesh 1301 is very close to the peripheral edge line of first metal cover 1401, the peripheral boundary line of first mesh 1301 can be very effectively referred to the mounting of first metal cover 1401.
As can be seen from the partially enlarged portion in fig. 9, the mounted first metal cover 1401 is centered within the first mesh 1301, and the upper edge line of the first metal cover 1401 is parallel to the upper boundary line of the first mesh 1301, the lower edge line of the first metal cover 1401 is parallel to the lower boundary line of the first mesh 1301, the left edge line of the first metal cover 1401 is parallel to the left boundary line of the first mesh 1301, and the right edge line of the first metal cover 1401 is parallel to the right boundary line of the first mesh 1301.
The process of mounting second metal cover 1402 in second mesh 1302 and the effect after mounting are the same as those described above with reference to first metal cover 1401 and first mesh 1301.
After the metal cover 140 is attached, whether the metal cover 140 is deflected or not can be rapidly observed through the boundary of the mesh where the metal cover 140 is located. If the deflection occurs, the metal cap 140 may be positionally corrected before the glue to which the metal cap 140 is attached is cured. Thereby avoiding the occurrence of a metal cap 140 application deflection in the individual packaged products after the strip 100 is cut into individual packaged products.
In summary, the semiconductor packaging method of the invention can ensure that the mounting position of the metal cover is accurate. After the metal cover is attached, the deflected metal cover can be rapidly observed through the grid marks, so that the position of the metal cover can be conveniently and timely corrected. The situation that the metal cover mounting deflection is not easy to observe because the mark can not provide effective reference is avoided. Thereby avoiding wafer waste, being beneficial to improving the packaging yield and reducing the packaging cost.
It should be noted that the product region appearing in the above embodiment may have various shape patterns. For example, as shown in fig. 5, the product area 101 is a rectangular area. Or in the embodiment not shown in the drawings, the product area may be a circular area, a triangular area, or the like, which is not particularly limited by the present invention and may be reasonably selected as required. Similarly, the edge regions that occur in the above embodiments may also have various shape patterns. For example, as shown in fig. 5, the edge region 102 is an annular region that surrounds the product region 101. Or in an embodiment not shown in the figures, the edge region may be an L-shaped or arcuate region. Similarly, the invention is not particularly limited, and can be reasonably selected according to the needs.
From the foregoing, it will be appreciated that the presence of the alignment marks is critical to the formation of the grid marks. It is necessary to further describe the process of forming the above-described grid marks for the alignment marks. In forming the grid mark 130 according to the alignment mark 110 through the step 40, there may be various implementations, and for better understanding, some examples thereof will be described below with reference to the accompanying drawings:
Example one
Referring to fig. 6, for more convenience in forming the grid marks, every two alignment marks 110 may be grouped together. Two alignment marks 110 within the same group are located on the same separation line 172.
Referring to fig. 7 and 8, when forming the transverse line marks 131 on the surface of the plastic package 120, the transverse line marks 131 can be accurately formed by using two alignment marks 110 distributed transversely in a group as two reference points based on a two-point one-line principle. Likewise, the longitudinal line marks 132 can also be formed by two alignment marks 110 distributed longitudinally in a group.
Thus, in this example, the alignment marks 110 may be distributed around the product array, which may facilitate and accurately form the grid marks 130.
Finally, as shown in fig. 9, the metal cover 140 is mounted based on the alignment marks 110 and the grid marks 130.
Example two
Fig. 10 is a schematic diagram illustrating a state of another semiconductor packaging method according to the present invention. Referring to fig. 10, the alignment marks 110 within each group in example one may also be reduced to one. I.e., there is only one alignment mark 110 within each group. Different alignment marks 110 are located at different separation lines 172. Furthermore, it is also possible to make the separation lines 172 between the adjacent two rows of products 103 in the strip 100 extend in the lateral direction, and the separation lines 172 between the adjacent two columns of products 103 in the strip 100 extend in the longitudinal direction.
Fig. 11 is a second schematic diagram of a state of another semiconductor packaging method according to the present invention, and fig. 12 is a third schematic diagram of a state of another semiconductor packaging method according to the present invention. Referring to fig. 11 and 12, when the transverse line marks 131 are formed on the surface of the molding compound 120, they may be formed by means of the alignment marks 110 and along transverse scribe lines. Likewise, the longitudinal line marks 132 may be formed by the alignment marks 110 and along the longitudinal scribe lines.
Thus, the alignment marks 110 may be distributed only on the adjacent sides of the product array, which also enables the formation of grid marks 130.
Fig. 13 is a schematic diagram illustrating a state of another semiconductor packaging method according to the present invention. Finally, as shown in fig. 13, the metal cover 140 is mounted based on the alignment marks 110 and the grid marks 130.
The grid marks 130 may be formed from the alignment marks 110 by the above example. It should be clear that the grid mark 130 should be clearly visible after formation, for effective reference. At the same time, the process steps for forming the grid mark 130 should be simplified as much as possible, and the impact of the grid mark 130 on the actual packaged product should be reduced. The present invention meets the above-described needs by employing laser cauterization marks as the grid mark 130. Specific:
Referring to fig. 8 or 12, a plurality of cross-line cautery marks and a plurality of longitudinal-line cautery marks intersecting each other are formed on the surface of the molding compound 120 by using a laser. The transverse line burn mark may be the transverse line mark 131, and the longitudinal line burn mark may be the longitudinal line mark 132.
Through the foregoing embodiments, the mounting of the plurality of metal covers 140 can be completed on the surface of the plastic package 120, and the mounting position of the metal covers 140 can also be made accurate. After this, the strip 100 may be cut so that a plurality of individual packaged products can be obtained.
Fig. 14 is a schematic structural diagram of a semiconductor package structure according to the present invention. To facilitate accurate cutting of the strip 100, a cutting street 150 is also provided on the back of the strip 100, as shown in fig. 14. Thus, when the dicing saw cuts the tape 100, the dicing can be performed along the dicing street 150. Of course, in other embodiments, the dicing street 150 may be located on the front side of the tape 100, and the present invention is not limited thereto, as long as it can be used to dice the tape 100. It should be appreciated that the dicing streets 150 may be formed using processes well known in the art.
The aforementioned mesh marks 130 formed on the surface of the plastic package 120 are laser burn marks, and the mesh marks 130 may be eliminated by a dicing process of a dicing saw considering that the mesh marks 130 are not beneficial for the final single package product. Specific:
by positively associating the grid mark 130 with the scribe line 150 in a direction along the vertical strip 100. For example, as shown in fig. 14, a first direction 173 of the vertical strip 100 is introduced, and the dicing streets 150 cover the grid marks 130 in the first direction 173. Thus, the grid marks 130 are also eliminated along the dicing saw cutting the strip 100 along the dicing lanes 150, thereby avoiding the grid marks 130 from affecting the packaged product.
The metal cover 140 can be attached to the surface of the plastic package 120 through the steps 10 to 50. After that, it is also possible to determine whether the already mounted metal cover 140 is deflected. The judging method comprises the following steps:
And acquiring the position information of each metal cover in the mesh where each metal cover is positioned. The offset value of each metal cap is determined by comparing the positional information and the target positional information. A threshold value is then introduced as a criterion. If the offset value of the metal cover exceeds the threshold value, the metal cover is judged to be deflected, and the metal cover needs to be re-attached at the moment until the re-attached metal cover is smaller than the threshold value. If the offset value is less than the threshold value, the metal cap is considered not to be deflected. The threshold value may be set according to the allowed position deviation, which is not limited by the present invention.
When the position information of the metal covers in the mesh is acquired, the edge contour line of each metal cover may be acquired first in the top view direction. Then, distance information between the edge contour line of the metal cover and the boundary line of the mesh in which the metal cover is located is calculated. From this, the position information of the metal cover in the mesh is obtained.
In some possible embodiments, as shown in fig. 5-13, the alignment marks 110 may be cross-shaped marks. When the grid mark 130 is formed by using the alignment mark 110, the cross point of the alignment mark 110 can be used as a reference point. The alignment mark 110 may be an observable mark pattern such as a protrusion or a depression.
In some possible embodiments, as shown in fig. 5 to 13, corner marks 160 may be formed at four corners of the product array in addition to the alignment marks 110, so as to better perform an alignment reference.
In another aspect of the embodiments of the present invention, a semiconductor package structure is provided, which is obtained by using any one of the above semiconductor packaging methods. In the packaging process, by introducing the alignment marks and the grid marks, effective references can be formed, and the position accuracy of the metal cover during alignment and mounting is conveniently improved. After the metal cover is attached, the inclined metal cover can be rapidly observed through the boundary of the mesh where the metal cover is positioned, so that the position of the metal cover can be corrected in time. Therefore, the situation that the metal cover is deflected in the finally obtained semiconductor packaging structure is avoided, the waste of wafers is avoided, the packaging yield is improved, and the packaging cost is reduced.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method of packaging a semiconductor, the method comprising:
Providing a strip comprising a product area having an array of products and an edge area located at a periphery of the product area;
A plurality of alignment marks are formed in the edge area of the front surface of the strip, and each alignment mark is positioned on a separation line between two adjacent columns or two adjacent rows of the product array;
forming a plastic package body covering the product array in a product area of the strip;
taking the alignment marks as references, and forming grid marks on the surface of the plastic package body so that one product is distributed in each mesh of the grid marks;
Taking the alignment marks and the grid marks as references, and attaching a metal cover corresponding to each product on the surface of the plastic package body;
The grid marks positively correspond to the cutting lines of the strip along the direction perpendicular to the strip;
After the metal cover corresponding to each product is attached to the surface of the plastic package body by taking the alignment mark and the grid mark as references, the method further comprises:
Cutting the strip along the dicing lanes to eliminate the grid marks.
2. The semiconductor package method of claim 1, wherein the edge region is a ring-shaped region surrounding the product region.
3. The method of claim 2, wherein each two of the plurality of alignment marks are arranged as a group, each group of alignment marks is disposed on opposite sides of the product region, and each group of alignment marks is disposed on the same separation line.
4. The semiconductor packaging method according to claim 1, wherein the step of forming a grid mark on the surface of the plastic package body with the alignment mark as a reference comprises:
and taking the alignment mark as a reference, forming the grid mark on the surface of the plastic package body by using laser, wherein the plurality of transverse line burning marks and the plurality of longitudinal line burning marks are intersected.
5. The semiconductor packaging method according to any one of claims 1 to 4, wherein after attaching a metal cap corresponding to each of the products to the surface of the plastic package with the alignment mark and the grid mark as references, the method further comprises:
acquiring position information of each metal cover in a mesh where the metal cover is positioned;
comparing the position information with target position information to determine an offset value of each metal cover;
And if the offset value is larger than a threshold value, re-attaching the metal cover.
6. The method of claim 5, wherein said obtaining positional information of each of said metal lids in a respective one of said cells comprises:
Acquiring edge contour lines of each metal cover in the direction perpendicular to the strip;
And obtaining the position information of the metal covers in the meshes according to the distance information between the edge contour line of the metal cover and the boundary line of the meshes in which the metal cover is positioned.
7. The semiconductor packaging method according to claim 5, wherein the re-attaching the metal cap if the offset value is greater than a threshold value comprises:
and if the offset value is greater than the threshold value, re-attaching the metal cover before the colloid of the metal cover adhered to the plastic package body is solidified.
8. A semiconductor package structure obtained by the semiconductor packaging method according to any one of claims 1 to 7.
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