TW201911491A - Stack type sensor package structure - Google Patents
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- TW201911491A TW201911491A TW106137154A TW106137154A TW201911491A TW 201911491 A TW201911491 A TW 201911491A TW 106137154 A TW106137154 A TW 106137154A TW 106137154 A TW106137154 A TW 106137154A TW 201911491 A TW201911491 A TW 201911491A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
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- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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- H01L2924/181—Encapsulation
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Abstract
Description
本發明涉及一種感測器封裝結構，尤其涉及一種堆疊式感測器封裝結構。 The present invention relates to a sensor package structure, and more particularly to a stacked sensor package structure.
現有的感測器封裝結構在內部設置有多個晶片時，所述多個晶片的設置方式會影響打線的穩定度，並有可能造成感測器封裝結構中的各種缺陷。舉例來說，當感測器封裝結構中包含有尺寸較大的一感測晶片與尺寸較小的一半導體晶片，並且所述感測晶片是黏於半導體晶片上方時，在感測晶片邊緣打線則需要較大的力量，如此常會造成感測晶片損傷。 When the existing sensor package structure has a plurality of wafers disposed therein, the arrangement of the plurality of wafers may affect the stability of the wire bonding, and may cause various defects in the sensor package structure. For example, when the sensor package structure includes a larger sensing die and a smaller semiconductor wafer, and the sensing wafer is adhered to the semiconductor wafer, the edge of the sensing wafer is wired. Larger forces are required, which often results in sensor wafer damage.
於是，本發明人認為上述缺陷可改善，乃特潛心研究並配合科學原理的運用，終於提出一種設計合理且有效改善上述缺陷的本發明。 Accordingly, the inventors believe that the above-mentioned defects can be improved, and that the invention has been studied with great interest and with the use of scientific principles, and finally proposes a present invention which is rational in design and effective in improving the above-mentioned defects.
本發明實施例在於提供一種堆疊式感測器封裝結構，其能有效地改善現有感測器封裝結構所可能產生的缺陷。 Embodiments of the present invention provide a stacked sensor package structure that can effectively improve defects that may occur in an existing sensor package structure.
本發明實施例公開一種堆疊式感測器封裝結構，包括：一基板，所述基板包含相對的一上表面與一下表面，並且所述基板在所述上表面形成有多個焊墊；至少一半導體晶片，安裝於所述基板；一支架，固定於所述基板的所述上表面並且位在多個所述焊墊的內側，至少一所述半導體晶片位於所述支架與所述基板所包圍的空間內並且未接觸所述支架，所述支架包含有位於至少一所 述半導體晶片上方的一承載平面；一感測晶片，所述感測晶片的尺寸大於至少一所述半導體晶片的尺寸，所述感測晶片包含有相對的一頂面與一底面，所述感測晶片在所述頂面設有多個連接墊，所述感測晶片的所述底面固定於所述承載平面；多條金屬線，多條所述金屬線的一端分別連接於多個所述焊墊，並且多條所述金屬線的另一端分別連接於多個所述連接墊；一透光層，所述透光層具有相對的一第一表面與一第二表面，所述第二表面包含有面向於所述感測晶片的一中心區及呈環狀且圍繞在所述中心區外側的一支撐區；一支撐體，所述支撐體呈環狀，所述支撐體設置於所述感測晶片的所述頂面與所述支架的所述承載平面的至少其中之一，所述支撐體的頂緣頂抵於所述透光層的所述支撐區；以及一封裝體(package compound)，所述封裝體設置於所述基板的所述上表面並包覆於所述支架的外側緣、所述透光層的至少部分外側緣、及所述支撐體的外側緣；其中，每條所述金屬線的至少部分埋置於所述封裝體內。 The embodiment of the present invention discloses a stacked sensor package structure, including: a substrate, the substrate includes an upper surface and a lower surface, and the substrate is formed with a plurality of pads on the upper surface; at least one a semiconductor wafer mounted on the substrate; a bracket fixed to the upper surface of the substrate and located inside the plurality of pads, at least one of the semiconductor wafers being surrounded by the bracket and the substrate And not contacting the bracket, the bracket includes a bearing plane located above at least one of the semiconductor wafers; a sensing wafer having a size larger than a size of at least one of the semiconductor wafers, The sensing wafer includes an opposite top surface and a bottom surface, the sensing wafer is provided with a plurality of connection pads on the top surface, and the bottom surface of the sensing wafer is fixed on the bearing plane; a plurality of the metal wires are respectively connected to the plurality of the pads, and the other ends of the plurality of wires are respectively connected to the plurality of the connection pads; a light transmissive layer, the The light transmissive layer has a first surface and a second surface, the second surface includes a central region facing the sensing wafer and a support region annular and surrounding the outer portion of the central region a support body, the support body is annular, and the support body is disposed on at least one of the top surface of the sensing wafer and the bearing plane of the bracket, the top of the support body a rib top abutting the support region of the light transmissive layer; and a package compound disposed on the upper surface of the substrate and covering the outer edge of the bracket At least a portion of the outer edge of the light transmissive layer and an outer edge of the support; wherein at least a portion of each of the metal lines is embedded within the package.
本發明實施例所公開的堆疊式感測器封裝結構中，基板上設置有支架，故可提升整體的結構強度，並使感測晶片能夠設置在穩定度較高的支架上，藉以控制其平整度。再者，由於感測晶片的打線區受到支架的穩固支撐，所以上述多條金屬線在打線成形的過程中，能夠有效地連接感測晶片的打線區，並避免造成其他元件的損傷。 In the stacked sensor package structure disclosed in the embodiment of the present invention, the substrate is provided with a bracket, so that the overall structural strength can be improved, and the sensing wafer can be disposed on the bracket with higher stability, thereby controlling the flatness thereof. degree. Moreover, since the wire bonding region of the sensing wafer is stably supported by the bracket, the plurality of metal wires can be effectively connected to the wire bonding region of the sensing wafer during the wire forming process, and the damage of other components is avoided.
另，所述堆疊式感測器封裝結構的感測晶片與半導體晶片被支架所隔開，以使感測晶片比較不會被半導體晶片產生的熱能直接影響，而所述半導體晶片產生的熱能還能通過基板的傳導而逸散，藉以有效地提升堆疊式感測器封裝結構的散熱效能。 In addition, the sensing wafer of the stacked sensor package structure and the semiconductor wafer are separated by the bracket, so that the sensing wafer is not directly affected by the thermal energy generated by the semiconductor wafer, and the thermal energy generated by the semiconductor wafer is further It can be dissipated through the conduction of the substrate, thereby effectively improving the heat dissipation performance of the stacked sensor package structure.
此外，在本發明的其中一個實施例中，支架上設有貫孔，在烘烤支架與基板間的黏膠(未標示)時，支架與基板間的空氣會受熱膨脹，並能通過貫孔排出，進而保持支架的(承載平面)平 整度。 In addition, in one embodiment of the present invention, the bracket is provided with a through hole. When the adhesive (not labeled) between the bracket and the substrate is baked, the air between the bracket and the substrate is thermally expanded and can pass through the through hole. Discharge, thereby maintaining the flatness of the carrier (bearing plane).
為能更進一步瞭解本發明的特徵及技術內容，請參閱以下有關本發明的詳細說明與附圖，但是此等說明與附圖僅用來說明本發明，而非對本發明的保護範圍作任何的限制。 For a better understanding of the features and technical aspects of the present invention, reference should be made to the accompanying claims limit.
100‧‧‧堆疊式感測器封裝結構 100‧‧‧Stacked sensor package structure
1‧‧‧基板 1‧‧‧Substrate
11‧‧‧上表面 11‧‧‧ upper surface
111‧‧‧焊墊 111‧‧‧ solder pads
112‧‧‧容置槽 112‧‧‧ accommodating slots
113‧‧‧打線區域 113‧‧‧Line area
12‧‧‧下表面 12‧‧‧ Lower surface
13‧‧‧焊球 13‧‧‧ solder balls
2‧‧‧半導體晶片(第一半導體晶片) 2‧‧‧Semiconductor wafer (first semiconductor wafer)
21‧‧‧金屬球 21‧‧‧metal ball
22‧‧‧底部填充劑 22‧‧‧Bottom filler
2’‧‧‧第二半導體晶片 2'‧‧‧Second semiconductor wafer
2’’‧‧‧第三半導體晶片 2''‧‧‧ Third semiconductor wafer
3‧‧‧支架 3‧‧‧ bracket
31‧‧‧環形座體 31‧‧‧Ring body
32‧‧‧承載板 32‧‧‧Bearing board
321‧‧‧承載平面 321‧‧‧bearing plane
322‧‧‧貫孔 322‧‧‧through holes
33‧‧‧缺口 33‧‧‧ gap
4‧‧‧感測晶片 4‧‧‧Sensor wafer
41‧‧‧頂面 41‧‧‧ top surface
411‧‧‧感測區 411‧‧‧Sense area
412‧‧‧打線區 412‧‧‧Line area
4121‧‧‧連接墊 4121‧‧‧Connecting mat
413‧‧‧承載區 413‧‧‧bearing area
42‧‧‧底面 42‧‧‧ bottom
43‧‧‧側邊部位 43‧‧‧ Side parts
5‧‧‧金屬線 5‧‧‧Metal wire
6‧‧‧透光層 6‧‧‧Transparent layer
61‧‧‧第一表面 61‧‧‧ first surface
62‧‧‧第二表面 62‧‧‧ second surface
621‧‧‧中心區 621‧‧‧Central District
622‧‧‧支撐區 622‧‧‧Support area
623‧‧‧固定區 623‧‧‧fixed area
63‧‧‧階梯部 63‧‧‧Steps
7‧‧‧支撐體 7‧‧‧Support
71‧‧‧第一支撐部 71‧‧‧First support
72‧‧‧第二支撐部 72‧‧‧Second support
73‧‧‧支撐層 73‧‧‧Support layer
74‧‧‧接合層 74‧‧‧Connection layer
8‧‧‧封裝體 8‧‧‧Package
81‧‧‧頂面 81‧‧‧ top surface
82‧‧‧液態封膠 82‧‧‧Liquid sealant
821‧‧‧頂面 821‧‧‧ top surface
83‧‧‧模製封膠 83‧‧‧Molded sealant
831‧‧‧頂面 831‧‧‧ top
9、9’‧‧‧密封膠 9, 9'‧‧‧ Sealant
E‧‧‧被動電子元件 E‧‧‧Passive electronic components
C‧‧‧內埋式晶片 C‧‧‧ buried chip
D‧‧‧防溢流距離 D‧‧‧Anti-overflow distance
圖1為本發明堆疊式感測器封裝結構實施例一的剖視示意圖。 1 is a cross-sectional view showing a first embodiment of a stacked sensor package structure according to the present invention.
圖2為本發明堆疊式感測器封裝結構實施例二的剖視示意圖。 2 is a cross-sectional view showing a second embodiment of a stacked sensor package structure according to the present invention.
圖3為本發明堆疊式感測器封裝結構實施例三的剖視示意圖。 3 is a cross-sectional view showing a third embodiment of a stacked sensor package structure according to the present invention.
圖4為本發明堆疊式感測器封裝結構實施例四的剖視示意圖。 4 is a cross-sectional view showing a fourth embodiment of a stacked sensor package structure according to the present invention.
圖5A為本發明堆疊式感測器封裝結構實施例五的剖視示意圖(一)。 5A is a cross-sectional view (1) of a fifth embodiment of a stacked sensor package structure according to the present invention.
圖5B為本發明堆疊式感測器封裝結構實施例五的剖視示意圖(二)。 5B is a cross-sectional view (2) of a fifth embodiment of a stacked sensor package structure according to the present invention.
圖6為本發明堆疊式感測器封裝結構實施例六的剖視示意圖。 6 is a cross-sectional view showing a sixth embodiment of a stacked sensor package structure according to the present invention.
圖7為本發明堆疊式感測器封裝結構實施例七的剖視示意圖。 FIG. 7 is a cross-sectional view showing a seventh embodiment of a stacked sensor package structure according to the present invention.
圖8為本發明堆疊式感測器封裝結構實施例八的剖視示意圖。 FIG. 8 is a cross-sectional view showing the eighth embodiment of the stacked sensor package structure of the present invention.
圖9為本發明堆疊式感測器封裝結構實施例九的剖視示意圖。 FIG. 9 is a cross-sectional view showing a ninth embodiment of a stacked sensor package structure according to the present invention.
圖10為本發明堆疊式感測器封裝結構實施例十的剖視示意圖。 FIG. 10 is a cross-sectional view showing a tenth embodiment of a stacked sensor package structure according to the present invention.
圖11為本發明堆疊式感測器封裝結構實施例十一的剖視示意圖。 11 is a cross-sectional view showing the eleventh embodiment of the stacked sensor package structure of the present invention.
圖12為本發明堆疊式感測器封裝結構實施例十二的剖視示意圖。 FIG. 12 is a cross-sectional view showing the twelveth embodiment of the stacked sensor package structure of the present invention.
圖13為本發明堆疊式感測器封裝結構實施例十三的剖視示意圖。 FIG. 13 is a cross-sectional view showing the thirteenth embodiment of the stacked sensor package structure of the present invention.
圖14A為本發明堆疊式感測器封裝結構實施例十四的剖視示意圖(一)。 14A is a cross-sectional view (1) of a fourteenth embodiment of a stacked sensor package structure according to the present invention.
圖14B為本發明堆疊式感測器封裝結構實施例十四的剖視示意圖(二)。 14B is a cross-sectional view (II) of the fourteenth embodiment of the stacked sensor package structure of the present invention.
圖15為本發明堆疊式感測器封裝結構實施例十五的剖視示意圖。 15 is a cross-sectional view showing the fifteenth embodiment of the stacked sensor package structure of the present invention.
圖16為本發明堆疊式感測器封裝結構實施例十六的剖視示意圖。 16 is a cross-sectional view showing the sixteenth embodiment of the stacked sensor package structure of the present invention.
圖17為本發明堆疊式感測器封裝結構實施例十七的剖視示意圖。 17 is a cross-sectional view showing the seventeenth embodiment of the stacked sensor package structure of the present invention.
圖18為本發明堆疊式感測器封裝結構實施例十八的剖視示意圖。 18 is a cross-sectional view showing the eighteenth embodiment of the stacked sensor package structure of the present invention.
圖19為本發明堆疊式感測器封裝結構實施例十九的剖視示意圖。 19 is a cross-sectional view showing the nineteenth embodiment of the stacked sensor package structure of the present invention.
圖20為本發明堆疊式感測器封裝結構實施例二十的剖視示意圖。 20 is a cross-sectional view showing a twenty-second embodiment of a stacked sensor package structure according to the present invention.
請參閱圖1至圖19，為本發明的實施例，需先說明的是，本實施例對應附圖所提及的相關數量與外型，僅用來具體地說明本發明的實施方式，以便於了解本發明的內容，而非用來侷限本發明的保護範圍。需額外說明的是，下述多個實施例所公開的技術特徵能夠彼此相互參考與轉用，以構成本發明所未繪示的其他實施例。 Please refer to FIG. 1 to FIG. 19 for an embodiment of the present invention. It should be noted that the related embodiments of the present invention are only used to specifically describe the embodiments of the present invention so that It is to be understood that the scope of the invention is not intended to limit the scope of the invention. It is to be noted that the technical features disclosed in the following various embodiments can be referred to each other and used interchangeably to constitute other embodiments not illustrated in the present invention.
如圖1所示，其為本發明的實施例一，本實施例公開一種堆疊式感測器封裝結構100，尤其是指一種影像感測器封裝結構100，但本發明不受限於此。所述堆疊式感測器封裝結構100於本實施例中包含有一基板1、設置於所述基板1上的一半導體晶片2、設置於所述基板1上並位於上述半導體晶片2外側的一支架3、設置於所述支架3上的一感測晶片4、電性連接所述感測晶片4與基板1的多條金屬線5、位置對應於所述感測晶片4的一透光層6、用來維持所述感測晶片4與透光層6相對位置的一支撐體7、及設置於所述基板1並包覆於所述支架3、支撐體7與透光層6的一封裝體8(package compound)。以下將分別介紹本實施例堆疊式感測器封裝結構100中的各個構件構造與其連接關係。 As shown in FIG. 1 , it is a first embodiment of the present invention. The present embodiment discloses a stacked sensor package structure 100 , and more particularly, an image sensor package structure 100 , but the invention is not limited thereto. In this embodiment, the stacked sensor package structure 100 includes a substrate 1 , a semiconductor wafer 2 disposed on the substrate 1 , and a support disposed on the substrate 1 and located outside the semiconductor wafer 2 . 3. A sensing wafer 4 disposed on the bracket 3, a plurality of metal wires 5 electrically connected to the sensing wafer 4 and the substrate 1, and a light transmissive layer 6 corresponding to the sensing wafer 4. a support body 7 for maintaining the relative position of the sensing wafer 4 and the light transmissive layer 6, and a package disposed on the substrate 1 and covering the bracket 3, the support body 7 and the light transmissive layer 6. Body (package compound). The respective component configurations and their connection relationships in the stacked sensor package structure 100 of the present embodiment will be separately described below.
所述基板1於本實施例中可以是塑膠基板、陶瓷基板、導線架(lead frame)、或是其他板狀材料，但本發明對此不加以限制。 其中，上述基板1包含相對的一上表面11與一下表面12，並且所述基板1在上表面11形成有間隔排列的多個焊墊111。再者，所述基板1在下表面12也形成有多個焊墊(未標示)，藉以用來分別焊接多顆焊球13。也就是說，所述多個焊球13呈陣列排列在上述基板1的下表面12，並且本實施例的基板1是以具備球柵陣列封裝(Ball Grid Array，BGA)的構造作一說明，但本發明不受限於此。 In this embodiment, the substrate 1 may be a plastic substrate, a ceramic substrate, a lead frame, or other plate-like material, but the invention is not limited thereto. The substrate 1 includes a pair of upper surface 11 and a lower surface 12, and the substrate 1 is formed with a plurality of pads 111 arranged at intervals on the upper surface 11. Furthermore, the substrate 1 is also formed with a plurality of pads (not labeled) on the lower surface 12 for soldering the plurality of solder balls 13 respectively. That is, the plurality of solder balls 13 are arranged in an array on the lower surface 12 of the substrate 1, and the substrate 1 of the present embodiment is described as a structure having a Ball Grid Array (BGA). However, the invention is not limited thereto.
所述半導體晶片2於本實施例中安裝於基板1的上表面11，並且上述半導體晶片2以打線電性連接於基板1，但本發明不受限於此。再者，所述半導體晶片2的類型可依據設計者的需求而加以改變，例如：所述半導體晶片2可以是一處理器晶片或是一記憶體晶片。 The semiconductor wafer 2 is mounted on the upper surface 11 of the substrate 1 in the present embodiment, and the semiconductor wafer 2 is electrically connected to the substrate 1 by wire bonding, but the invention is not limited thereto. Moreover, the type of the semiconductor wafer 2 can be changed according to the needs of the designer. For example, the semiconductor wafer 2 can be a processor chip or a memory chip.
所述支架3於本實施例中的材質為玻璃且為一體成形的單件式構造，也就是說，所述支架3可以是在一承載板的中間挖設一方槽而製造形成，但本發明不以此為限。舉例來說，所述支架3的材質也可以是具有高導熱的剛性材質(如：陶瓷或金屬)。其中，所述支架3固定於所述基板1的上表面並且位在上述多個焊墊111的內側，並且所述支架3與基板1所包圍的(封閉狀)空間內佈滿空氣，而所述半導體晶片2位於上述支架3與基板1所包圍的空間內並且未接觸該支架3。 The bracket 3 is made of glass in the embodiment and is a one-piece structure integrally formed. That is to say, the bracket 3 can be manufactured by cutting a groove in the middle of a carrier plate, but the invention is formed. Not limited to this. For example, the material of the bracket 3 may also be a rigid material with high thermal conductivity (such as ceramic or metal). The bracket 3 is fixed on the upper surface of the substrate 1 and is located inside the plurality of pads 111, and the (closed) space surrounded by the bracket 3 and the substrate 1 is filled with air. The semiconductor wafer 2 is located in the space surrounded by the above-mentioned bracket 3 and the substrate 1 and does not contact the bracket 3.
更詳細地說，所述支架3包含有一環形座體31及一體連接於所述環形座體31頂緣的一承載板32，而所述環形座體31的底緣固定於上述基板1的上表面11。其中，所述支架3可以通過一黏合膠層(未標示)將環形座體31固定於基板1上，並且上述黏合膠層可以是一光固化黏著膠(UV curing epoxy)、一熱固化黏著膠(thermal curing epoxy)、混合上述光固化黏著膠與熱固化黏著膠 之一混合型黏著膠、或是一黏著膠膜(attach film)，本發明並不以此為限制。 In more detail, the bracket 3 includes an annular seat body 31 and a carrier plate 32 integrally connected to the top edge of the annular seat body 31, and the bottom edge of the annular seat body 31 is fixed on the substrate 1 Surface 11. The bracket 3 can be fixed to the substrate 1 by an adhesive layer (not labeled), and the adhesive layer can be a UV curing epoxy or a heat curing adhesive. (thermal curing epoxy), mixing one of the above-mentioned photocurable adhesive and heat-curing adhesive, or an adhesive film, the invention is not limited thereto.
再者，所述承載板32的外表面(也就是圖1中的承載板32頂面)位於上述半導體晶片2的上方並且定義為一承載平面321。也就是說，本實施例是以平整度較佳的承載板32表面來作為承載所述感測晶片4的承載平面321，藉以確保感測晶片4的平整度。另，所述支架3具備有較佳的結構剛性，藉以能有效地降低所述堆疊式感測器封裝結構100的翹曲程度。 Furthermore, the outer surface of the carrier plate 32 (that is, the top surface of the carrier plate 32 in FIG. 1) is located above the semiconductor wafer 2 and is defined as a carrier plane 321 . That is to say, in this embodiment, the surface of the carrier 32 is preferably used as the bearing plane 321 for carrying the sensing wafer 4, thereby ensuring the flatness of the sensing wafer 4. In addition, the bracket 3 is provided with a good structural rigidity, so that the degree of warpage of the stacked sensor package structure 100 can be effectively reduced.
此外，所述支架3也可依據設計者的需求而加以改調其構造(如下述實施例所載)。舉例來說：支架3也可以形成有貫孔，其具體說明如實施例十九所載。 In addition, the bracket 3 can also be modified according to the needs of the designer (as set forth in the following embodiments). For example, the bracket 3 can also be formed with a through hole, which is specifically described in the nineteenth embodiment.
所述感測晶片4於本實施例中是以一影像感測晶片來作說明，並且所述感測晶片4的尺寸大於上述半導體晶片2的尺寸，但本發明對感測晶片4的類型不加以限制。其中，所述感測晶片4包含有相對的一頂面41與一底面42、及垂直地相連於上述頂面41與底面42的一外側緣(未標示)。所述頂面41包含有一感測區411、位於上述感測區411外側的一打線區412、及位於所述感測區411與打線區412之間的一承載區413。並且感測晶片4在上述打線區412設有多個連接墊4121，也就是說，上述多個連接墊4121位於所述感測區411的外側。 The sensing wafer 4 is illustrated by an image sensing wafer in this embodiment, and the size of the sensing wafer 4 is larger than the size of the semiconductor wafer 2, but the type of the sensing wafer 4 is not in the present invention. Limit it. The sensing wafer 4 includes an opposite top surface 41 and a bottom surface 42 and an outer edge (not labeled) perpendicularly connected to the top surface 41 and the bottom surface 42. The top surface 41 includes a sensing area 411 , a tapping area 412 located outside the sensing area 411 , and a bearing area 413 between the sensing area 411 and the wiring area 412 . The sensing wafer 4 is provided with a plurality of connection pads 4121 in the above-mentioned wire-bonding region 412, that is, the plurality of connection pads 4121 are located outside the sensing region 411.
更詳細地說，所述感測區411於本實施例中大致呈矩形(如：正方形或長方形)，並且上述感測區411的中心可以是頂面41的中心(如：圖1)或是與頂面41中心留有一距離(圖中未示出)。所述打線區412於本實施例中呈方環狀，並且上述打線區412的每個部位的寬度較佳是大致相同，但打線區412的具體外型可以依據設計者或製造者的需求而加以調整，在此不加以限制。舉例來說，在本發明未繪示的其他實施例中，所述打線區412也可以 是位在感測區411一側的直線狀區域或L形區域、或是位在感測區411相反兩側的兩個直線狀區域。 In more detail, the sensing region 411 is substantially rectangular (eg, square or rectangular) in this embodiment, and the center of the sensing region 411 may be the center of the top surface 41 (eg, FIG. 1) or There is a distance from the center of the top surface 41 (not shown). The wire bonding area 412 is square in the embodiment, and the width of each portion of the wire bonding area 412 is preferably substantially the same, but the specific shape of the wire bonding area 412 may be according to the needs of the designer or the manufacturer. Adjust it and do not limit it here. For example, in other embodiments not shown in the present invention, the wire bonding region 412 may also be a linear region or an L-shaped region located on one side of the sensing region 411 or opposite to the sensing region 411. Two linear areas on each side.
再者，所述感測晶片4的底面42固定於所述支架3的承載平面321上，並且感測晶片4底面42的周邊部位較佳是設置於環形座體31的上方。其中，本實施例中的感測晶片4是通過黏晶膠(Die Attach Epoxy，未標示)來將其底面42固定於支架3的承載平面321上，但具體設置方式不受限於此。 Moreover, the bottom surface 42 of the sensing wafer 4 is fixed on the bearing plane 321 of the bracket 3, and the peripheral portion of the bottom surface 42 of the sensing wafer 4 is preferably disposed above the annular seat body 31. The sensing wafer 4 in this embodiment is fixed to the bearing plane 321 of the bracket 3 by die attach adhesive (not shown), but the specific arrangement is not limited thereto.
所述多條金屬線5的一端分別連接於基板1的多個焊墊111，並且多條金屬線5的另一端分別連接於感測晶片4的多個連接墊4121。上述每條金屬線5可以通過反打(reverse bond)或是正打(forward bond)的方式所形成。進一步地說，當每條金屬線5採用反打方式時，上述感測晶片4的頂面41與每條金屬線5的相鄰部位能夠形成有小於等於45度的一夾角(未標示)，以使每條金屬線5的頂點能夠位在較低的高度位置，進而避免觸碰到透光層6，但本發明不受限於此。 One ends of the plurality of metal wires 5 are respectively connected to the plurality of pads 111 of the substrate 1 , and the other ends of the plurality of metal wires 5 are respectively connected to the plurality of connection pads 4121 of the sensing wafer 4 . Each of the above metal wires 5 can be formed by a reverse bond or a forward bond. Further, when each of the metal wires 5 is in a reverse-pushing manner, the top surface 41 of the sensing wafer 4 and the adjacent portion of each of the metal wires 5 can form an angle (not labeled) of 45 degrees or less. The vertices of each of the metal wires 5 can be positioned at a lower height position, thereby avoiding the light transmissive layer 6, but the invention is not limited thereto.
所述透光層6於本實施例中呈透明狀且以平板狀的玻璃作一說明，但本發明對透光層6的類型不加以限制。舉例來說，所述透光層6也可以是由透光(或透明)塑膠材質所形成。其中，所述透光層6具有相對(如：位於相反兩面)的一第一表面61與一第二表面62、及垂直地相連於第一表面61與第二表面62的一外側緣(未標示)。本實施例的第一表面61與第二表面62為尺寸相同的矩形(如：正方形或長方形)，並且所述透光層6的第二表面62面積小於上述感測晶片4的頂面41面積，但不受限於此。 The light transmissive layer 6 is transparent in the present embodiment and is described as a flat glass. However, the present invention does not limit the type of the light transmissive layer 6. For example, the light transmissive layer 6 may also be formed of a light transmissive (or transparent) plastic material. The light transmissive layer 6 has a first surface 61 and a second surface 62 opposite to each other (eg, on opposite sides), and an outer edge perpendicularly connected to the first surface 61 and the second surface 62 (not Mark). The first surface 61 and the second surface 62 of the embodiment are rectangular (eg, square or rectangular) of the same size, and the second surface 62 of the transparent layer 6 has an area smaller than the area of the top surface 41 of the sensing wafer 4. , but not limited to this.
進一步地說，所述透光層6是通過支撐體7而設置於感測晶片4上方，並且透光層6的第二表面62是大致平行且面向於所述感測晶片4的頂面41。進一步地說，所述第二表面62包含有面向 於上述感測晶片4的一中心區621、呈環狀且圍繞在所述中心區621外側的一支撐區622、及位於所述支撐區622外側的一固定區623。其中，所述感測晶片4的感測區411正投影於第二表面62而形成有一投影區域(未標示)，並且所述投影區域即相當於第二表面62的中心區，但本發明不以此為限。抵接於上述支撐體7的第二表面62部位即相當於支撐區622，在上述中心區621與支撐區622以外的第二表面62部位即相當於所述固定區623。 Further, the light transmissive layer 6 is disposed above the sensing wafer 4 through the support body 7, and the second surface 62 of the light transmissive layer 6 is substantially parallel and faces the top surface 41 of the sensing wafer 4. . Further, the second surface 62 includes a central region 621 facing the sensing wafer 4, a support region 622 that is annular and surrounds the outside of the central region 621, and is located at the support region 622. A fixed area 623 on the outside. Wherein, the sensing region 411 of the sensing wafer 4 is projected onto the second surface 62 to form a projection area (not labeled), and the projection area corresponds to the central area of the second surface 62, but the present invention does not This is limited to this. The portion of the second surface 62 that abuts against the support body 7 corresponds to the support region 622, and the second surface 62 portion other than the central region 621 and the support region 622 corresponds to the fixed region 623.
另，上述透光層6的第二表面62較佳是鄰設但未接觸於每條金屬線5，每條金屬線5的頂點相較於基板1上表面11的高度較佳是小於所述透光層6第二表面62相較於基板1上表面11的高度，但不受限於此。 In addition, the second surface 62 of the light transmissive layer 6 is preferably adjacent but not in contact with each of the metal wires 5, and the height of the apex of each of the metal wires 5 is preferably smaller than the height of the upper surface 11 of the substrate 1. The second surface 62 of the light transmissive layer 6 is higher than the height of the upper surface 11 of the substrate 1, but is not limited thereto.
所述支撐體7於本實施例中呈環狀且其材質例如是玻璃接合樹脂(Glass Mount Epoxy，GME)，但本發明不受限於此。其中，所述支撐體7的底緣設置於上述感測晶片4的頂面41的承載區413，也就是說，所述支撐體7的底緣位於上述感測區411與多個連接墊4121之間。所述支撐體7的頂緣頂抵於上述透光層6的支撐區622，也就是說，所述支撐體7並未接觸透光層6的中心區621與固定區623。藉此，所述堆疊式感測器封裝結構100能通過上述支撐體7，而使所述透光層6的第二表面62大致平行於感測晶片4的頂面41，並使透光層6的第二表面62與感測晶片4的頂面41能被保持在一預設距離。 The support body 7 is annular in the present embodiment and is made of, for example, a glass-bonding resin (Glass Mount Epoxy, GME), but the invention is not limited thereto. The bottom edge of the support body 7 is disposed on the bearing area 413 of the top surface 41 of the sensing wafer 4, that is, the bottom edge of the support body 7 is located in the sensing area 411 and the plurality of connection pads 4121 between. The top edge of the support body 7 abuts against the support region 622 of the light transmissive layer 6, that is, the support body 7 does not contact the central region 621 and the fixed region 623 of the light transmissive layer 6. Thereby, the stacked sensor package structure 100 can pass the support body 7 such that the second surface 62 of the light transmissive layer 6 is substantially parallel to the top surface 41 of the sensing wafer 4 and the light transmissive layer The second surface 62 of the 6 and the top surface 41 of the sensing wafer 4 can be maintained at a predetermined distance.
所述封裝體8於本實施例中是以一液態封膠(liquid compound)來說明，但本發明不受限於此。其中，所述封裝體8設置於基板1的上表面11並包覆於所述支撐體7的外側緣、支架3的外側緣與部分承載平面321、感測晶片4的外側緣與打線區412、支撐體7的外側緣、以及透光層6的固定區623與外側緣。 進一步地說，上述封裝體8的頂面81大致呈斜面狀或曲面狀，所述封裝體8頂面81的邊緣相連於所述透光層6的邊緣(如：第一表面61的邊緣)，以使所述封裝體8頂面與透光層6的第一表面61形成有呈銳角的一切角，但本發明不受限於此。另，上述每條金屬線5及每個焊墊111皆埋置於上述封裝體8內。 The package 8 is illustrated in the present embodiment as a liquid compound, but the invention is not limited thereto. The package body 8 is disposed on the upper surface 11 of the substrate 1 and covers the outer edge of the support body 7 , the outer edge of the bracket 3 and the partial bearing plane 321 , the outer edge of the sensing wafer 4 and the wire bonding region 412 . , the outer edge of the support body 7, and the fixed area 623 and the outer edge of the light transmissive layer ã ‚ Further, the top surface 81 of the package body 8 is substantially beveled or curved, and the edge of the top surface 81 of the package 8 is connected to the edge of the light transmissive layer 6 (eg, the edge of the first surface 61). The top surface of the package 8 and the first surface 61 of the light transmissive layer 6 are formed with an acute angle, but the invention is not limited thereto. In addition, each of the metal wires 5 and each of the pads 111 are buried in the package body 8.
依上所述，在本實施例所公開的堆疊式感測器封裝結構100中，基板1上設置支架3，故可提升整體的結構強度，並使感測晶片4能夠設置在穩定度較高的支架3上，藉以控制其平整度。再者，由於感測晶片4的打線區412受到支架3的穩固支撐，所以上述多條金屬線5在打線成形的過程中，能夠有效地連接在感測晶片4的打線區412，而避免造成其他元件的損傷。 As described above, in the stacked sensor package structure 100 disclosed in the embodiment, the bracket 3 is disposed on the substrate 1, so that the overall structural strength can be improved, and the sensing wafer 4 can be set at a higher stability. On the bracket 3, to control its flatness. Moreover, since the wire bonding region 412 of the sensing wafer 4 is stably supported by the bracket 3, the plurality of metal wires 5 can be effectively connected to the wire bonding region 412 of the sensing wafer 4 during the wire forming process, thereby avoiding Damage to other components.
另，所述堆疊式感測器封裝結構100的感測晶片4與半導體晶片2被支架3所隔開，以使感測晶片4比較不會被半導體晶片2產生的熱能直接影響，並且所述半導體晶片2產生的熱能還能通過基板1及其下表面12上的金屬球21的傳導而逸散，藉以有效地提升堆疊式感測器封裝結構100的散熱效能。 In addition, the sensing wafer 4 of the stacked sensor package structure 100 and the semiconductor wafer 2 are separated by the bracket 3 so that the sensing wafer 4 is not directly affected by the thermal energy generated by the semiconductor wafer 2, and The thermal energy generated by the semiconductor wafer 2 can also be dissipated through the conduction of the metal balls 21 on the substrate 1 and its lower surface 12, thereby effectively improving the heat dissipation performance of the stacked sensor package structure 100.
如圖2所示，其為本發明的實施例二，本實施例與上述實施例一類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述支架3。以下將說明本實施例與上述實施例一的差異處。 As shown in FIG. 2, which is the second embodiment of the present invention, the present embodiment is similar to the first embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: Bracket 3. The difference between this embodiment and the above-described first embodiment will be described below.
於本實施例中，所述支架3的環形座體31與承載板32並非是一體成形的構造，所述環形座體31例如是以一黏合膠層(未標示)而連接於承載板32的周緣，並且環形座體31的外側緣是切齊於承載板32的外側緣，但本發明不受限於此。其中，所述黏合膠層可以是一光固化黏著膠、一熱固化黏著膠、混合上述光固化 黏著膠與熱固化黏著膠之一混合型黏著膠、或是一黏著膠膜，本發明在此不加以限制。 In this embodiment, the annular seat body 31 and the carrier plate 32 of the bracket 3 are not integrally formed. The annular seat body 31 is connected to the carrier plate 32 by, for example, an adhesive layer (not shown). The periphery, and the outer edge of the annular seat body 31 is aligned with the outer edge of the carrier plate 32, but the invention is not limited thereto. The adhesive layer may be a photocurable adhesive, a heat-curing adhesive, a mixed adhesive of the photocurable adhesive and the heat-curing adhesive, or an adhesive film. The invention is here. No restrictions.
進一步地說，由於所述環形座體31與承載板32並非是一體成形的構造，所以上述環形座體31的材質可以是相同或相異於上述承載板32的材質。舉例來說，所述承載板32或環形座體31的材質可以選用熱膨脹係數(Coefficient of thermal expansion，CTE)小於10的剛性材料。例如：玻璃材質(CTE=7.2ppm/℃)、矽基材(CTE=2.6ppm/℃)、金屬、或陶瓷，本發明在此不加以限制。 Further, since the annular seat body 31 and the carrier plate 32 are not integrally formed, the material of the annular seat body 31 may be the same or different from the material of the carrier plate 32. For example, the material of the carrier plate 32 or the annular seat body 31 may be a rigid material having a coefficient of thermal expansion (CTE) of less than 10. For example, glass material (CTE = 7.2 ppm / ° C), enamel substrate (CTE = 2.6 ppm / ° C), metal, or ceramic, the invention is not limited herein.
如圖3所示，其為本發明的實施例三，本實施例與上述實施例二類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：本實施例的堆疊式感測器封裝結構100進一步包含有多個被動電子元件E。以下將說明本實施例與上述實施例二的差異處。 As shown in FIG. 3, which is the third embodiment of the present invention, the embodiment is similar to the second embodiment, and the same portions of the two embodiments are not described again. The main difference between the two embodiments is: the implementation The stacked sensor package structure 100 of the example further includes a plurality of passive electronic components E. The difference between this embodiment and the above-described second embodiment will be described below.
於本實施例中，所述多個被動電子元件E安裝於所述基板1的上表面11，並且上述多個被動電子元件E中的部分被動電子元件E位於基板1與支架3所包圍的空間內並與半導體晶片2呈間隔設置，而其餘的被動電子元件E則可以位於上述支架3的外側並且埋置於所述封裝體8內。 In this embodiment, the plurality of passive electronic components E are mounted on the upper surface 11 of the substrate 1 , and a portion of the plurality of passive electronic components E are located in a space surrounded by the substrate 1 and the bracket 3 . The semiconductor chip 2 is disposed inside and spaced apart from the semiconductor wafer 2, and the remaining passive electronic components E may be located outside the bracket 3 and embedded in the package 8.
如圖4所示，其為本發明的實施例四，本實施例與上述實施例二類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：本實施例的堆疊式感測器封裝結構100進一步包含有一密封膠9。以下將說明本實施例與上述實施例二的差異處。 As shown in FIG. 4, which is the fourth embodiment of the present invention, the present embodiment is similar to the above-mentioned second embodiment, and the same portions of the two embodiments are not described again, and the main difference between the two embodiments is: the implementation The stacked sensor package structure 100 further includes a sealant 9. The difference between this embodiment and the above-described second embodiment will be described below.
於本實施例中，所述支架3與基板1所包圍的空間內部分充 填上述密封膠9，以使所述半導體晶片2埋置於密封膠9內。進一步地說，當所述環形座體31固定於基板1的上表面11，但尚未連接於承載板32時，所述環形座體31內能充填密封膠9，藉以埋置所述半導體晶片2，而後再將所述承載板32固定於環形座體31的頂緣。 In the present embodiment, the inside of the space surrounded by the holder 3 and the substrate 1 is filled with the above-mentioned sealant 9 so that the semiconductor wafer 2 is buried in the sealant 9. Further, when the annular seat body 31 is fixed to the upper surface 11 1⁄4 of the substrate 1 but not connected to the carrier plate 32, the ring body 31 can be filled with a sealant 9 to embed the semiconductor wafer 2 The carrier plate 32 is then fixed to the top edge of the annular seat body 31.
如圖5A和圖5B所示，其為本發明的實施例五，本實施例與上述實施例二類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述支架3。以下將說明本實施例與上述實施例二的差異處。 As shown in FIG. 5A and FIG. 5B, which is the fifth embodiment of the present invention, the present embodiment is similar to the above-mentioned second embodiment, and the same portions of the two embodiments are not described again, and the main difference between the two embodiments is that : the stent 3. The difference between this embodiment and the above-described second embodiment will be described below.
於本實施例中，所述支架3自其承載平面321的外緣凹設形成有呈環狀的一缺口33，並且所述缺口33位在感測晶片4的外側。其中，所述缺口33自承載平面321的凹設深度可依據設計者的需求而加以變化，本發明在此不加以限制。舉例來說，所述缺口33可以是僅凹設於上述支架3的承載板32(如：圖5A)，或者所述缺口33也可以自支架3的承載板32凹設至環形座體31(如：圖5B)。 In the present embodiment, the bracket 3 is recessed from the outer edge of the bearing plane 321 to form a notch 33 which is annular, and the notch 33 is located outside the sensing wafer 4. The recessed depth of the notch 33 from the bearing plane 321 can be changed according to the needs of the designer, and the invention is not limited herein. For example, the notch 33 may be a carrier plate 32 that is only recessed in the bracket 3 (eg, FIG. 5A), or the notch 33 may also be recessed from the carrier 32 of the bracket 3 to the annular seat 31 ( Such as: Figure 5B).
如圖6所示，其為本發明的實施例六，本實施例與上述實施例二類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述透光層6。以下將說明本實施例與上述實施例二的差異處。 As shown in FIG. 6, which is the sixth embodiment of the present invention, the present embodiment is similar to the above-mentioned second embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: Light transmissive layer 6. The difference between this embodiment and the above-described second embodiment will be described below.
於本實施例中，所述透光層6的頂部周緣也可以形成有一階梯部63，以供所述封裝體8附著於所述階梯部63上。其中，上述階梯部的具體構造可依據設計者的需求而加以變化，本發明在此不加以限制。舉例來說，所述階梯部63可以是環形、L形、或長 條狀。 In the embodiment, a step portion 63 may be formed on the top periphery of the light transmissive layer 6 for the package body 8 to be attached to the step portion 63. The specific configuration of the step portion may be changed according to the needs of the designer, and the present invention is not limited thereto. For example, the step portion 63 may be annular, L-shaped, or elongated.
如圖7所示，其為本發明的實施例七，本實施例與上述實施例二類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述支撐體7。以下將說明本實施例與上述實施例二的差異處。 As shown in FIG. 7 , which is the seventh embodiment of the present invention, the present embodiment is similar to the above-mentioned second embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: Support body 7. The difference between this embodiment and the above-described second embodiment will be described below.
於本實施例中，所述支撐體7的頂緣頂抵於透光層6的支撐區622，並且所述支撐體7的底緣設置於感測晶片4頂面41的打線區412。其中，上述支撐體7包覆所述多個連接墊4121及每條金屬線5的部分，而每條金屬線5的其餘部分埋置於所述封裝體8內。換個角度來說，本實施例中的感測晶片4頂面41僅具有感測區411及位於感測區411外側的打線區412，而不具有承載區413。換個角度來說，所述感測晶片4頂面41也可以視為打線區412與承載區413重合。 In the present embodiment, the top edge of the support body 7 abuts against the support region 622 of the light transmissive layer 6, and the bottom edge of the support body 7 is disposed on the wire bonding region 412 of the top surface 41 of the sensing wafer 4. The support body 7 covers the plurality of connection pads 4121 and portions of each of the metal wires 5, and the remaining portion of each of the metal wires 5 is buried in the package body 8. In other words, the top surface 41 of the sensing wafer 4 in this embodiment has only the sensing region 411 and the wiring region 412 located outside the sensing region 411 without the bearing region 413. In other words, the top surface 41 of the sensing wafer 4 can also be regarded as the bonding area 412 coincident with the carrying area 413.
如圖8所示，其為本發明的實施例八，本實施例與上述實施例七類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述支撐體7。以下將說明本實施例與上述實施例七的差異處。 As shown in FIG. 8, which is the eighth embodiment of the present invention, the present embodiment is similar to the above-mentioned seventh embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: Support body 7. The difference between this embodiment and the above-described seventh embodiment will be described below.
於本實施例中，所述支撐體7的頂緣頂抵於透光層6的支撐區622，並且所述支撐體7底緣的部分設置於感測晶片4的頂面、並包覆多個連接墊4121及每條金屬線5的部分，而每條金屬線5的其餘部分埋置於所述封裝體8內。 In this embodiment, the top edge of the support body 7 abuts against the support region 622 of the light transmissive layer 6, and a portion of the bottom edge of the support body 7 is disposed on the top surface of the sensing wafer 4 and is coated. The pads 4121 are connected to portions of each of the metal wires 5, and the remaining portion of each of the metal wires 5 is buried in the package 8.
更詳細地說，所述感測晶片4的一側邊部位43(如：圖8中的感測晶片4右側邊部位)未設有任何連接墊4121，並且所述支撐體7包含有一第一支撐部71與一第二支撐部72。其中，所述第 一支撐部71的頂緣頂抵於所述透光層6的支撐區622，所述第一支撐部71的底緣設置於上述感測晶片4頂面41的打線區412、並包覆多個連接墊4121及每條金屬線5的部分。所述第二支撐部72的頂緣頂抵於所述透光層6的支撐區622，所述第二支撐部72的底緣設置於所述承載平面321並且鄰近上述側邊部位43，並且所述第二支撐部72未接觸任一條金屬線5。 In more detail, one side portion 43 of the sensing wafer 4 (such as the right side portion of the sensing wafer 4 in FIG. 8) is not provided with any connection pads 4121, and the support body 7 includes a first portion. The support portion 71 and a second support portion 72. The top edge of the first support portion 71 abuts against the support region 622 of the light transmissive layer 6. The bottom edge of the first support portion 71 is disposed on the wire bonding region 412 of the top surface 41 of the sensing wafer 4. And covering a plurality of connection pads 4121 and portions of each of the metal wires 5. The top edge of the second support portion 72 abuts against the support region 622 of the light transmissive layer 6 , and the bottom edge of the second support portion 72 is disposed on the bearing plane 321 and adjacent to the side portion 43 , and The second support portion 72 does not contact any of the metal wires 5.
再者，所述第二支撐部72於本實施例中是以相互堆疊的兩層式構造來說明，但本發明不受限於此。舉例來說，在本發明未繪示的其他實施例中，所述第二支撐部72也可以是一體成形的單件式構造。 Furthermore, the second support portion 72 is illustrated in a two-layer configuration in which it is stacked on each other in the present embodiment, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the second support portion 72 may also be an integrally formed one-piece construction.
另，所述第一支撐部71與第二支撐部72可以是一體相連的構造，例如：先成形第二支撐部72的底層構造，而後再成形彼此相連呈環狀的第一支撐部71與第二支撐部72的頂層構造，並且第二支撐部72的頂層構造堆疊於上述底層構造；或者，所述第一支撐部71與第二支撐部72也可以是彼此分離的構造，本發明在此不加以限制。 In addition, the first supporting portion 71 and the second supporting portion 72 may be integrally connected, for example, the bottom structure of the second supporting portion 72 is formed first, and then the first supporting portion 71 connected to each other in an annular shape is formed. The top layer of the second support portion 72 is configured, and the top layer structure of the second support portion 72 is stacked on the bottom layer structure; or the first support portion 71 and the second support portion 72 may be separated from each other, and the present invention is This is not limited.
此外，本實施例雖是以所述感測晶片4的一側邊部位43未設有任何連接墊4121來說明，而所述第二支撐部72則對應於上述側邊部位43設置，但本發明不受限於此。舉例來說，在本發明未繪示的其他實施例中，所述感測晶片4也可以是在至少兩個側邊部位43未設有任何連接墊4121。 In addition, in this embodiment, the one side portion 43 of the sensing wafer 4 is not provided with any connection pads 4121, and the second support portion 72 is disposed corresponding to the side portion 43. The invention is not limited thereto. For example, in other embodiments not shown in the present invention, the sensing wafer 4 may also be provided with no connection pads 4121 in at least two side portions 43.
如圖9所示，其為本發明的實施例九，本實施例與上述實施例八類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述支撐體7。以下將說明本實施例與上述實施例八的差異處。 As shown in FIG. 9, which is the ninth embodiment of the present invention, the present embodiment is similar to the above-mentioned eighth embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: Support body 7. The difference between this embodiment and the above-described eighth embodiment will be described below.
於本實施例中，所述支撐體7設置在上述支架3的承載平面 321並且位於所述感測晶片4的外側緣，所述支撐體7包覆每條金屬線5的部分，而每條金屬線5的其餘部分埋置於所述封裝體8內。更詳細地說，所述支撐體7包含有一支撐層73及一接合層74。所述支撐層73設置在上述支架3的承載平面321、並位於所述感測晶片4的外側緣，所述支撐層73未接觸任一個金屬線5。所述接合層74設置於支撐層73上，並且接合層74的頂緣頂抵於所述透光層6的支撐區622，每個金屬線5的局部埋置於接合層74內。其中，所述支撐層73相較於承載平面321的一高度大致等於所述感測晶片4的頂面41相較於承載平面321的一高度，並且每個金屬線5的局部埋置於接合層74內，但本發明不受限於此。 In this embodiment, the support body 7 is disposed on the bearing plane 321 of the bracket 3 and located at the outer edge of the sensing wafer 4, and the support body 7 covers a portion of each of the metal wires 5, and each of the strips The remaining portion of the metal line 5 is embedded in the package 8. In more detail, the support body 7 includes a support layer 73 and a bonding layer 74. The support layer 73 is disposed on the bearing plane 321 of the bracket 3 and located on the outer edge of the sensing wafer 4, and the supporting layer 73 does not contact any of the metal wires 5. The bonding layer 74 is disposed on the support layer 73, and the top edge of the bonding layer 74 abuts against the support region 622 of the light transmissive layer 6, and a portion of each of the metal wires 5 is buried in the bonding layer 74. The height of the support layer 73 compared to the bearing plane 321 is substantially equal to a height of the top surface 41 of the sensing wafer 4 compared to the bearing plane 321 , and a portion of each of the metal wires 5 is buried. Within layer 74, the invention is not limited thereto.
此外，所述支撐體7的支撐層73及接合層74於本實施例中是以兩個構件來說明，但本發明不受限於此。舉例來說，在本發明未繪示的其他實施例中，所述支撐層73及接合層74也可以是一體成形的單件式構件。 Further, the support layer 73 and the bonding layer 74 of the support body 7 are described in terms of two members in the present embodiment, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the support layer 73 and the bonding layer 74 may also be an integrally formed one-piece member.
再者，本實施例的支撐體7雖是以支撐層73相連於感測晶片4的外側緣，但在本發明未繪示的其他實施例中，所述支撐體7與感測晶片4的外側緣之間也可以留有一間隙。 Furthermore, the support body 7 of the present embodiment is connected to the outer edge of the sensing wafer 4 by the support layer 73, but in other embodiments not shown in the present invention, the support body 7 and the sensing wafer 4 are A gap can also be left between the outer edges.
如圖10所示，其為本發明的實施例十，本實施例與上述實施例八類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述封裝體8。以下將說明本實施例與上述實施例八的差異處。 As shown in FIG. 10, which is the tenth embodiment of the present invention, the present embodiment is similar to the above-mentioned eighth embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: Package 8. The difference between this embodiment and the above-described eighth embodiment will be described below.
於本實施例中，所述封裝體8包含有一液態封膠82以及一模製封膠83(molding compound)，由於本實施例的液態封膠82已於上述實施例中說明，所以在此不加以贅述。再者，所述模製封膠83形成於上述液態封膠82的頂面821，並且所述模製封膠83的頂面831平行於所述透光層6的第一表面61，並且模製封膠83 的頂面831低於所述透光層6的第一表面61並相隔有大致50μm至100μm之一防溢流距離D。 In this embodiment, the package body 8 includes a liquid sealant 82 and a molding compound 83. Since the liquid sealant 82 of the embodiment has been described in the above embodiment, it is not Repeat them. Moreover, the molding sealant 83 is formed on the top surface 821 of the liquid sealant 82, and the top surface 831 of the mold sealant 83 is parallel to the first surface 61 of the light transmissive layer 6, and the mold The top surface 831 of the sealant 83 is lower than the first surface 61 of the light transmissive layer 6 and is separated by an anti-overflow distance D of approximately 50 μm to 100 μm.
如圖11所示，其為本發明的實施例十一，本實施例與上述實施例七類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述封裝體8。以下將說明本實施例與上述實施例七的差異處。 As shown in FIG. 11 , which is the eleventh embodiment of the present invention, the present embodiment is similar to the above-mentioned seventh embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are: The package 8 is described. The difference between this embodiment and the above-described seventh embodiment will be described below.
於本實施例中，所述封裝體8為一模製封膠83。其中，所述模製封膠83(封裝體8)設置於基板1的上表面11並包覆於所述支撐體7的外側緣、支架3的外側緣與部分承載平面321、感測晶片4的外側緣、以及所述透光層6的固定區623與部分外側緣。再者，所述模製封膠83(封裝體8)的頂面831呈平面狀且低於所述透光層6的第一表面61並相隔有大致50μm至100μm的一防溢流距離D。 In the embodiment, the package 8 is a molded seal 83. The molding sealant 83 (the package 8) is disposed on the upper surface 11 of the substrate 1 and covers the outer edge of the support body 7, the outer edge of the bracket 3 and the partial bearing plane 321 , and the sensing wafer 4 . The outer edge, and the fixed area 623 and the partial outer edge of the light transmissive layer 6. Furthermore, the top surface 831 of the molding encapsulant 83 (package 8) is planar and lower than the first surface 61 of the light transmissive layer 6 and separated by an anti-overflow distance D of approximately 50 μm to 100 μm. .
如圖12所示，其為本發明的實施例十二，本實施例與上述實施例二類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：本實施例堆疊式感測器封裝結構100包含有多個半導體晶片2。以下將說明本實施例與上述實施例二的差異處。 As shown in FIG. 12, which is the twelfth embodiment of the present invention, the present embodiment is similar to the above-mentioned second embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are: Embodiment Stacked sensor package structure 100 includes a plurality of semiconductor wafers 2. The difference between this embodiment and the above-described second embodiment will be described below.
於本實施例中，所述多個半導體晶片2呈彼此堆疊地設置於基板1的上表面11，並且每個半導體晶片2皆打線連接於所述基板1的上表面11，藉以使每個半導體晶片2與基板1達成電性連接，但本發明不受限於此。 In the embodiment, the plurality of semiconductor wafers 2 are stacked on the upper surface 11 of the substrate 1 on each other, and each of the semiconductor wafers 2 is wire-bonded to the upper surface 11 of the substrate 1 so that each semiconductor is The wafer 2 is electrically connected to the substrate 1, but the invention is not limited thereto.
如圖13所示，其為本發明的實施例十三，本實施例與上述實施例十二類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：本實施例堆疊式感測器封裝結構100進一步包含有一內埋式晶片C。以下將說明本實施例與上述實施例十二的差異處。 As shown in FIG. 13 , which is the thirteenth embodiment of the present invention, the present embodiment is similar to the above-mentioned embodiment 12, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: The stacked sensor package structure 100 of the present embodiment further includes a buried wafer C. The difference between this embodiment and the above-described embodiment 12 will be described below.
於本實施例中，所述內埋式晶片C埋置於上述基板1內，並且在本發明未繪示的其他實施例中，埋置於基板1內的內埋式晶片C數量也可以是多個。 In the embodiment, the embedded wafer C is embedded in the substrate 1 , and in other embodiments not shown in the present invention, the number of embedded wafers C embedded in the substrate 1 may also be Multiple.
如圖14A及圖14B所示，其為本發明的實施例十四，本實施例與上述實施例七類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述半導體晶片2。以下將說明本實施例與上述實施例七的差異處。 As shown in FIG. 14A and FIG. 14B, which is the fourteenth embodiment of the present invention, the present embodiment is similar to the above-mentioned seventh embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are shown. In the semiconductor wafer 2. The difference between this embodiment and the above-described seventh embodiment will be described below.
於本實施例中，所述半導體晶片2非為打線連接於基板1。更詳細地說，所述半導體晶片2是以多個金屬球21焊接於基板1的上表面11，藉以使半導體晶片2與基板1之間達成電性連接。再者，所述半導體晶片2與上述基板1之間也可以選擇性地充填有一底部填充劑22(underfill)，而多個所述金屬球21埋置於所述底部填充劑22內(如：圖14B)。 In the embodiment, the semiconductor wafer 2 is not connected to the substrate 1 by wire bonding. In more detail, the semiconductor wafer 2 is soldered to the upper surface 11 of the substrate 1 by a plurality of metal balls 21, thereby electrically connecting the semiconductor wafer 2 and the substrate 1. Furthermore, the semiconductor wafer 2 and the substrate 1 may be selectively filled with an underfill 22, and a plurality of the metal balls 21 are buried in the underfill 22 (eg: Figure 14B).
如圖15所示，其為本發明的實施例十五，本實施例與上述實施例十二類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述基板1。以下將說明本實施例與上述實施例十二的差異處。 As shown in FIG. 15, which is the fifteenth embodiment of the present invention, the present embodiment is similar to the above-mentioned embodiment twelve, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: The substrate 1. The difference between this embodiment and the above-described embodiment 12 will be described below.
於本實施例中，所述基板1上表面11凹設形成有一容置槽112，所述多個半導體晶片2位於上述容置槽112內，並且每個半 導體晶片2皆打線連接於所述容置槽112的槽底，藉以使每個半導體晶片2與基板1達成電性連接。 In this embodiment, the upper surface 11 of the substrate 1 is recessed and formed with a receiving groove 112. The plurality of semiconductor wafers 2 are located in the receiving groove 112, and each of the semiconductor wafers 2 is wire-bonded to the capacitor. The groove bottom of the groove 112 is disposed so that each semiconductor wafer 2 is electrically connected to the substrate 1.
如圖16所示，其為本發明的實施例十六，本實施例與上述實施例十五類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述基板1。以下將說明本實施例與上述實施例十五的差異處。 As shown in FIG. 16, which is the sixteenth embodiment of the present invention, the present embodiment is similar to the above-mentioned embodiment fifteen, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: The substrate 1. The difference between this embodiment and the above-described embodiment fifteen will be described below.
於本實施例中，所述基板1的上表面11在上述支架3與容置槽112之間留有一打線區域113，並且多個所述半導體晶片2的至少其中一個半導體晶片2(如：在圖16中位於上方的半導體晶片2)打線連接於所述打線區域113，而其餘半導體晶片2(如：在圖16中位於下方的半導體晶片2)則打線連接於所述容置槽112的槽底，藉以使每個半導體晶片2與基板1達成電性連接。 In the embodiment, the upper surface 11 of the substrate 1 has a wire bonding region 113 between the bracket 3 and the receiving groove 112, and at least one of the semiconductor wafers 2 of the plurality of semiconductor wafers 2 (eg, The semiconductor wafer 2) located above in FIG. 16 is wire-bonded to the wire-bonding region 113, and the remaining semiconductor wafer 2 (such as the semiconductor wafer 2 located below in FIG. 16) is wire-bonded to the groove of the accommodating groove 112. The bottom is such that each semiconductor wafer 2 is electrically connected to the substrate 1.
如圖17所示，其為本發明的實施例十七，本實施例與上述實施例十五類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述支架3。以下將說明本實施例與上述實施例十五的差異處。 As shown in FIG. 17, which is the seventeenth embodiment of the present invention, the present embodiment is similar to the above-mentioned fifteenth embodiment, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: The bracket 3. The difference between this embodiment and the above-described embodiment fifteen will be described below.
於本實施例中，所述支架3進一步限定為黏固於所述基板1的上表面11的一承載板32，並且所述承載板32的外表面定義為承載平面321。其中，所述承載板32的周緣例如是以一黏合膠層(未標示)而連接於所述基板1的上表面11、並封閉上述容置槽112，但本發明不受限於此。進一步地說，所述黏合膠層可以是一光固化黏著膠、一熱固化黏著膠、混合上述光固化黏著膠與熱固化黏著膠之一混合型黏著膠、或是一黏著膠膜，本發明在此不加以限制。 In the present embodiment, the bracket 3 is further defined as a carrier plate 32 adhered to the upper surface 11 of the substrate 1, and an outer surface of the carrier plate 32 is defined as a bearing plane 321 . The periphery of the carrier 32 is connected to the upper surface 11 of the substrate 1 by an adhesive layer (not shown), and the accommodating groove 112 is closed, but the invention is not limited thereto. Further, the adhesive layer may be a photocurable adhesive, a heat curing adhesive, a mixed adhesive of the photocurable adhesive and the heat curing adhesive, or an adhesive film. The invention There is no limit here.
如圖18所示，其為本發明的實施例十八，本實施例與上述實施例十七類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：本實施例的堆疊式感測器封裝結構100進一步包含有一密封膠9’。以下將說明本實施例與上述實施例十七的差異處。 As shown in FIG. 18, which is the eighteenth embodiment of the present invention, the present embodiment is similar to the above-mentioned embodiment seventeen, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: The stacked sensor package structure 100 of this embodiment further includes a sealant 9'. The difference between this embodiment and the above-described embodiment 17 will be described below.
於本實施例中，所述容置槽112充填上述密封膠9’，以使所述半導體晶片2埋置於所述密封膠9’內。 In the embodiment, the accommodating groove 112 is filled with the sealant 9' to embed the semiconductor wafer 2 in the sealant 9'.
如圖19所示，其為本發明的實施例十九，本實施例與上述實施例一類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：所述支架3。以下將說明本實施例與上述實施例一的差異處。 As shown in FIG. 19, which is the nineteenth embodiment of the present invention, the present embodiment is similar to the above-mentioned first embodiment, and the same portions of the two embodiments are not described again, and the main difference between the two embodiments is: Said bracket 3. The difference between this embodiment and the above-described first embodiment will be described below.
於本實施例中，所述支架3的承載板32設有一貫孔322，並且所述感測晶片4遮蔽上述貫孔322。其中，本實施例的貫孔322位置不在所述半導體晶片2的正上方，但本發明貫孔322形成在支架3的具體位置不受限於此。藉此，在烘烤支架3與基板1間的黏著膠(未標示)、以使所述支架3固定於基板1上表面11的過程中，上述支架3與基板1間的空氣受熱膨脹，並能通過所述貫孔322排氣，進而保持支架3的(承載平面321)平整度。 In the embodiment, the carrier 32 of the bracket 3 is provided with a uniform hole 322, and the sensing wafer 4 shields the through hole 322. The position of the through hole 322 of the present embodiment is not directly above the semiconductor wafer 2, but the specific position of the through hole 322 of the present invention formed on the bracket 3 is not limited thereto. Thereby, in the process of baking the adhesive (not labeled) between the bracket 3 and the substrate 1 to fix the bracket 3 to the upper surface 11 of the substrate 1, the air between the bracket 3 and the substrate 1 is thermally expanded, and The through hole 322 can be exhausted, thereby maintaining the flatness of the carrier 3 (bearing plane 321).
如圖20所示，其為本發明的實施例二十，本實施例與上述實施例十九類似，兩個實施例的相同處則不再加以贅述，而兩個實施例的主要差異在於：本實施例堆疊式感測器封裝結構100包含有至少三個半導體晶片2、2’、2’’。以下將說明本實施例與上述 實施例十九的差異處。 As shown in FIG. 20, which is the embodiment 20 of the present invention, the present embodiment is similar to the above-mentioned embodiment 19, and the same portions of the two embodiments are not described again, and the main differences between the two embodiments are as follows: The stacked sensor package structure 100 of the present embodiment includes at least three semiconductor wafers 2, 2', 2". The difference between this embodiment and the above-described embodiment 19 will be described below.
於本實施例中，所述三個半導體晶片2、2’、2’’能分別運用不同的固定技術、並且分別命名為一第一半導體晶片2、一第二半導體晶片2’、及一第三半導體晶片2’’，藉以區隔彼此而利於說明，但所述「第一」、「第二」、與「第三」並不具有其他物理意義。 In this embodiment, the three semiconductor wafers 2, 2', 2" can be respectively used with different fixing technologies, and are respectively named as a first semiconductor wafer 2, a second semiconductor wafer 2', and a first The three semiconductor wafers 2'' are used to illustrate each other, but the "first", "second", and "third" do not have other physical meanings.
所述第一半導體晶片2是以多個金屬球21焊接於基板1的上表面11，藉以使第一半導體晶片2與基板1之間達成電性連接。再者，所述第一半導體晶片2與上述基板1之間充填有一底部填充劑22(underfill)，而多個所述金屬球21埋置於所述底部填充劑22內。 The first semiconductor wafer 2 is soldered to the upper surface 11 of the substrate 1 by a plurality of metal balls 21, thereby electrically connecting the first semiconductor wafer 2 and the substrate 1. Furthermore, an underfill 22 is filled between the first semiconductor wafer 2 and the substrate 1 , and a plurality of the metal balls 21 are buried in the underfill 22 .
所述第二半導體晶片2’堆疊於第一半導體晶片2上、並打線連接於所述基板1的上表面11，藉以使第二半導體晶片2’與基板1達成電性連接。 The second semiconductor wafer 2' is stacked on the first semiconductor wafer 2 and is wire-bonded to the upper surface 11 of the substrate 1, whereby the second semiconductor wafer 2' is electrically connected to the substrate 1.
所述第三半導體晶片2’’設置於所述基板1的上表面11並且位於上述相互堆疊的第一半導體晶片2與第二半導體晶片2’的一側，所述第三半導體晶片2’’打線連接於所述基板1的上表面11，藉以使第三半導體晶片2’’與基板1達成電性連接。 The third semiconductor wafer 2 ′′ is disposed on the upper surface 11 of the substrate 1 and on one side of the first semiconductor wafer 2 and the second semiconductor wafer 2 ′ stacked on each other, the third semiconductor wafer 2 ′′ The wire is connected to the upper surface 11 of the substrate 1 to electrically connect the third semiconductor wafer 2'' with the substrate 1.
需說明的是，所述第一半導體晶片2、第二半導體晶片2’、及第三半導體晶片2’’的類型可依據設計者的需求而加以調整變化，例如：影像信號處理器(image signal processor，ISP)、快閃記憶體(flash memory)、或微控制器(micro controller)，本發明在此不加以限制。 It should be noted that the types of the first semiconductor chip 2, the second semiconductor wafer 2', and the third semiconductor wafer 2" may be adjusted according to the needs of the designer, for example, an image signal processor (image signal processor) Processor, ISP), flash memory, or micro controller, the invention is not limited herein.
以上所述僅為本發明的優選可行實施例，並非用來侷限本發明的保護範圍，凡依本發明申請專利範圍所做的均等變化與修飾，皆應屬本發明的權利要求書的保護範圍。 The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. The equivalents and modifications made by the scope of the present invention should fall within the scope of the claims of the present invention. .
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