JP6563538B2 - Multilayer sensor mounting structure - Google Patents
Multilayer sensor mounting structure Download PDFInfo
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- JP6563538B2 JP6563538B2 JP2018022773A JP2018022773A JP6563538B2 JP 6563538 B2 JP6563538 B2 JP 6563538B2 JP 2018022773 A JP2018022773 A JP 2018022773A JP 2018022773 A JP2018022773 A JP 2018022773A JP 6563538 B2 JP6563538 B2 JP 6563538B2
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- 239000000758 substrate Substances 0.000 claims description 84
- 239000004065 semiconductor Substances 0.000 claims description 74
- 239000010410 layer Substances 0.000 claims description 61
- 230000005540 biological transmission Effects 0.000 claims description 43
- 239000000565 sealant Substances 0.000 claims description 20
- 239000012790 adhesive layer Substances 0.000 claims description 15
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 15
- 150000001875 compounds Chemical class 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 7
- 239000003795 chemical substances by application Substances 0.000 claims description 6
- 230000002265 prevention Effects 0.000 claims description 5
- 238000000465 moulding Methods 0.000 claims description 4
- 230000004308 accommodation Effects 0.000 claims 1
- 238000003475 lamination Methods 0.000 description 19
- 238000001514 detection method Methods 0.000 description 13
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000002184 metal Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- 239000004593 Epoxy Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000016 photochemical curing Methods 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 238000009510 drug design Methods 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
本発明は、センサ実装構造に関し、特に積層型センサ実装構造に関する。 The present invention relates to a sensor mounting structure, and more particularly to a stacked sensor mounting structure.
従来のセンサ実装構造は内部に複数のチップが設けられている場合、前記複数のチップの設置方式はワイヤボンディングの安定性に影響し、センサ実装構造における各種のデメリットを招く可能性がある。例えば、センサ実装構造にサイズの大きなセンシングチップとサイズの小さな半導体チップとを備え、前記センシングチップが半導体チップの上方に貼り付けられる場合、センシングチップのエッジにワイヤボンディングすると、大きな力が必要となる。このようにセンシングチップにダメージを与えることが多い。 When a conventional sensor mounting structure includes a plurality of chips, the installation method of the plurality of chips affects the stability of wire bonding and may cause various disadvantages in the sensor mounting structure. For example, when a sensor mounting structure includes a large-sized sensing chip and a small-sized semiconductor chip, and the sensing chip is attached above the semiconductor chip, a large force is required when wire bonding is performed on the edge of the sensing chip. . In this way, the sensing chip is often damaged.
それで、本発明者は上記デメリットが改善できると考えているので、鋭意検討し学理の応用に合わせて、設計が合理であり上記デメリットを効果的に改善する本発明をようやく提出した。 Therefore, the present inventor thinks that the above disadvantages can be improved, and therefore has intensively studied and submitted the present invention which has a rational design and effectively improves the above disadvantages in accordance with the application of science.
本発明の実施例は、従来のセンサ実装構造に生じ得るデメリットを効果的に改善できる積層型センサ実装構造を提供する。 Embodiments of the present invention provide a stacked sensor mounting structure that can effectively improve the disadvantages that may occur in a conventional sensor mounting structure.
本発明の実施例では、対向する上面と下面とを備え、前記上面に複数のパッドが形成されている基板と、前記基板に取り付けられる少なくとも一つの半導体チップと、前記基板の前記上面に固定されるとともに複数の前記パッドの内側に位置するフレームであって、少なくとも一つの前記半導体チップが前記フレームと前記基板によって囲まれる空間内に位置し前記フレームに接触せず、少なくとも一つの前記半導体チップ上方に位置する載置平面を備えるフレームと、サイズが少なくとも一つの前記半導体チップのサイズよりも大きく、対向する天面と底面とを備え、前記天面に複数の接続パッドが設けられており、前記底面が前記載置平面に固定されるセンシングチップと、一端がそれぞれ複数の前記パッドに接続され、他端がそれぞれ複数の前記接続パッドに接続される複数本のワイヤと、対向する第１の表面と第２の表面とを有し、前記第２の表面が前記センシングチップに向かっている中心エリアと環状を呈しており前記中心エリアの外側を取り囲む支持エリアとを備える光透過層と、環状を呈しており、前記センシングチップの前記天面と前記フレームの前記載置平面との少なくとも一つに設けられ、頂縁が前記光透過層の前記支持エリアに当接される支持体と、前記基板の前記上面に設けられるとともに前記フレームの外側縁、前記光透過層の少なくとも一部の外側縁、及び前記支持体の外側縁を被覆する実装体（ｐａｃｋａｇｅ ｃｏｍｐｏｕｎｄ）であって、各前記ワイヤの少なくとも一部が前記実装体に埋め込まれる実装体とを備える積層型センサ実装構造が開示されている。 In an embodiment of the present invention, a substrate having an upper surface and a lower surface facing each other, wherein a plurality of pads are formed on the upper surface, at least one semiconductor chip attached to the substrate, and fixed to the upper surface of the substrate. And at least one of the semiconductor chips is located in a space surrounded by the frame and the substrate, does not contact the frame, and is located above the at least one semiconductor chip. A frame including a mounting plane located at the top, a size larger than the size of at least one of the semiconductor chips, and a top surface and a bottom surface facing each other, and a plurality of connection pads are provided on the top surface, A sensing chip whose bottom surface is fixed to the mounting plane, one end is connected to each of the plurality of pads, and the other end is each A plurality of wires connected to the number of the connection pads, and a first surface and a second surface facing each other, wherein the second surface has an annular shape with a central area facing the sensing chip A light-transmitting layer having a support area surrounding the outside of the central area, and having an annular shape, provided on at least one of the top surface of the sensing chip and the mounting plane of the frame. A support having an edge in contact with the support area of the light transmission layer; an outer edge of the frame; an outer edge of at least a portion of the light transmission layer; and the support provided on the upper surface of the substrate. A stacked sensor mounting structure including a mounting body that covers an outer edge of the mounting body, wherein at least a part of each wire is embedded in the mounting body. It is shown.
本発明の実施例に開示される積層型センサ実装構造において、基板にフレームが設けられているので、全体の構造強度を向上でき、センシングチップが安定性の高いフレームに設けられ得ることにより、その平坦度を制御する。なお、センシングチップのワイヤボンディングエリアがフレームによって強固に支持されるので、上記複数本のワイヤは、ワイヤボンディング成形の過程において、センシングチップのワイヤボンディングエリアに効果的に接続され、他の部品にダメージを与えることを回避することが可能である。 In the stacked sensor mounting structure disclosed in the embodiments of the present invention, since the frame is provided on the substrate, the overall structural strength can be improved, and the sensing chip can be provided on the highly stable frame. Control the flatness. In addition, since the wire bonding area of the sensing chip is firmly supported by the frame, the plurality of wires are effectively connected to the wire bonding area of the sensing chip in the process of wire bonding forming, and other parts are damaged. It is possible to avoid giving.
また、前記積層型センサ実装構造のセンシングチップと半導体チップがフレームによって離隔されるので、センシングチップは、半導体チップによる熱エネルギーにより直接影響されず、前記半導体チップによる熱エネルギーはさらに基板の伝導を介して散逸できることで、積層型センサ実装構造の放熱効率を効果的に向上させる。 In addition, since the sensing chip and the semiconductor chip of the stacked sensor mounting structure are separated by a frame, the sensing chip is not directly influenced by the thermal energy by the semiconductor chip, and the thermal energy by the semiconductor chip further passes through the conduction of the substrate. The heat dissipation efficiency of the stacked sensor mounting structure is effectively improved.
なお、本発明の一実施例において、フレームに貫通孔が設けられており、フレームと基板間の粘着剤をベークする（図示せず）場合、フレームと基板間の空気は加熱されて膨張し、貫通孔を介して排気され、さらにフレーム（載置平面）の平坦度を保持することができる。 In one embodiment of the present invention, the frame is provided with a through hole, and when the adhesive between the frame and the substrate is baked (not shown), the air between the frame and the substrate is heated to expand, The air is exhausted through the through hole, and the flatness of the frame (mounting plane) can be maintained.
本発明の特徴及び技術内容がより一層判るように、以下本発明に関する詳細な説明と添付図面を参照するが、これらの説明と添付図面は本発明を説明するためのものに過ぎず、本発明の保護範囲が何ら制限されない。 For a better understanding of the features and technical contents of the present invention, reference will now be made to the detailed description of the invention and the accompanying drawings, which are set forth merely to illustrate the invention, and to which the present invention pertains. There is no limitation on the scope of protection.
図１乃至図２２を参照する。図１乃至図２２は本発明の実施例であり、本実施例の対応する添付図面に記載される関連数と外形は、本発明の実施の態様を具体的に説明し、本発明の内容が分かりやすくするためのものに過ぎず、本発明の保護範囲を限定するものではないことをまず明らかにしておく。なお、本発明で示していない他の実施例を構成するように、下記の複数の実施例に開示される技術特徴は互いに参考と転用され得る。 Please refer to FIG. 1 to FIG. 1 to 22 show an embodiment of the present invention, and the related numbers and outlines described in the accompanying drawings corresponding to the present embodiment specifically describe the embodiment of the present invention. First, it will be clarified that it is merely for the sake of clarity and does not limit the protection scope of the present invention. It should be noted that the technical features disclosed in the following embodiments can be used as references and diverted so as to constitute other embodiments not shown in the present invention.
［実施例１］
図１に示すように、それは本発明の実施例１であり、本実施例は、積層型センサ実装構造１００を開示し、特に画像センサ実装構造１００に関するが、本発明はこれに制限されない。前記積層型センサ実装構造１００は、本実施例において基板１と、前記基板１に設けられる半導体チップ２と、前記基板１に設けられるとともに上記半導体チップ２の外側に位置するフレーム３と、前記フレーム３に設けられるセンシングチップ４と、前記センシングチップ４と基板１を電気的に接続させる複数本のワイヤ５と、位置が前記センシングチップ４に対応する光透過層６と、前記センシングチップ４と光透過層６との相対的位置を維持するための支持体７と、前記基板１に設けられるとともに前記フレーム３、支持体７及び光透過層６を被覆する実装体８（ｐａｃｋａｇｅ ｃｏｍｐｏｕｎｄ）とを備える。以下に本実施例の積層型センサ実装構造１００中の各部材の構造及びその接続関係をそれぞれ説明する。
[Example 1]
As shown in FIG. 1, it is Embodiment 1 of the present invention, and this embodiment discloses a stacked sensor mounting structure 100, and particularly relates to an image sensor mounting structure 100, but the present invention is not limited thereto. In this embodiment, the laminated sensor mounting structure 100 includes a substrate 1, a semiconductor chip 2 provided on the substrate 1, a frame 3 provided on the substrate 1 and positioned outside the semiconductor chip 2, and the frame. 3, a plurality of wires 5 for electrically connecting the sensing chip 4 and the substrate 1, a light transmitting layer 6 corresponding to the sensing chip 4, the sensing chip 4 and the light A support body 7 for maintaining a relative position with the transmission layer 6 and a mounting body 8 (package compound) provided on the substrate 1 and covering the frame 3, the support body 7 and the light transmission layer 6 are provided. . Hereinafter, the structure of each member in the stacked sensor mounting structure 100 of this embodiment and the connection relationship thereof will be described.
前記基板１は本実施例においてプラスチック基板、セラミック基板、リードフレーム（ｌｅａｄ ｆｒａｍｅ）、又は他の板状材料であってもよいが、本発明はこれを制限するものではない。なかでも、上記基板１は対向する上面１１と下面１２とを備え、上面１１には間隔を置いて配列される複数のパッド１１１が形成されている。なお、前記基板１は、下面１２にも複数のパッド（図示せず）が形成されていることで、それぞれ複数の半田ボール１３を溶接させるためのものである。つまり、前記複数の半田ボール１３が上記基板１の下面１２にアレイ状に配列され、本実施例の基板１についてボールグリッドアレイ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ、ＢＧＡ）を備える構造により説明するが、本発明はこれに制限されない。 The substrate 1 may be a plastic substrate, a ceramic substrate, a lead frame, or another plate-like material in the present embodiment, but the present invention is not limited thereto. In particular, the substrate 1 includes an upper surface 11 and a lower surface 12 facing each other, and a plurality of pads 111 arranged at intervals are formed on the upper surface 11. The substrate 1 has a plurality of pads (not shown) formed on the lower surface 12 so that a plurality of solder balls 13 are welded to each other. That is, the plurality of solder balls 13 are arranged in an array on the lower surface 12 of the substrate 1, and the substrate 1 of this embodiment will be described with a structure including a ball grid array (BALL Grid Array, BGA). This is not a limitation.
前記半導体チップ２は、本実施例において基板１の上面１１に取り付けられ、ワイヤボンディングで基板１に電気的に接続されるが、本発明はこれに制限されない。なお、前記半導体チップ２のタイプは設計者の要求に従い変更してもよく、例えば、前記半導体チップ２はプロセッサチップ又はメモリーチップであってもよい。 In this embodiment, the semiconductor chip 2 is attached to the upper surface 11 of the substrate 1 and is electrically connected to the substrate 1 by wire bonding. However, the present invention is not limited to this. The type of the semiconductor chip 2 may be changed according to a designer's request. For example, the semiconductor chip 2 may be a processor chip or a memory chip.
前記フレーム３の本実施例における材質はガラスであり、一体成形されたワンピース構造である。つまり、前記フレーム３は、載置板の中間に矩形溝が穿設されて製造形成されてもよいが、本発明はこれに限定されるものではない。例えば、前記フレーム３の材質は高熱伝導率を有する剛性材質（例えば、セラミック又は金属）であってもよい。なかでも、前記フレーム３が前記基板１の上面に固定されるとともに上記複数のパッド１１１の内側に位置し、前記フレーム３と基板１によって囲まれる（閉塞状）空間内が空気に満たされており、前記半導体チップ２が上記フレーム３と基板１によって囲まれる空間内に位置し前記フレーム３に接触しない。 The material of the frame 3 in this embodiment is glass and has a one-piece structure formed integrally. That is, the frame 3 may be manufactured by forming a rectangular groove in the middle of the mounting plate, but the present invention is not limited to this. For example, the material of the frame 3 may be a rigid material (for example, ceramic or metal) having high thermal conductivity. In particular, the frame 3 is fixed to the upper surface of the substrate 1 and is located inside the plurality of pads 111, and the space enclosed by the frame 3 and the substrate 1 is filled with air. The semiconductor chip 2 is located in a space surrounded by the frame 3 and the substrate 1 and does not contact the frame 3.
より詳しくは、前記フレーム３は、環状台座３１と前記環状台座３１の頂縁に一体的に接続される載置板３２とを備え、前記環状台座３１の底縁が上記基板１の上面１１に固定される。なかでも、前記フレーム３は接着剤層（図示せず）を介して環状台座３１を基板１に固定することができ、上記接着剤層は、光硬化型粘着剤（ＵＶ ｃｕｒｉｎｇ ｅｐｏｘｙ）、熱硬化型粘着剤（ｔｈｅｒｍａｌ ｃｕｒｉｎｇ ｅｐｏｘｙ）、上記光硬化型粘着剤と熱硬化型粘着剤とが混合された混合型粘着剤、又は粘着剤膜（ａｔｔａｃｈ ｆｉｌｍ）であってもよく、本発明はこれに制限されるものではない。 More specifically, the frame 3 includes an annular pedestal 31 and a mounting plate 32 integrally connected to the top edge of the annular pedestal 31, and the bottom edge of the annular pedestal 31 is on the upper surface 11 of the substrate 1. Fixed. Among them, the frame 3 can fix the annular pedestal 31 to the substrate 1 through an adhesive layer (not shown), and the adhesive layer is made of a photocuring adhesive (UV curing epoxy), thermosetting. It may be a type adhesive (thermal curing epoxy), a mixed type adhesive obtained by mixing the photo-curing type adhesive and the thermosetting type adhesive, or an adhesive film. It is not limited.
なお、前記載置板３２の外面（即ち図１中の載置板３２の天面）が上記半導体チップ２の上方に位置し載置平面３２１と定義されている。つまり、本実施例は平坦度の好ましい載置板３２の表面を前記センシングチップ４を載置する載置平面３２１とすることにより、センシングチップ４の平坦度を確保する。また、前記フレーム３は好ましい構造の剛性を備えることで、前記積層型センサ実装構造１００の反りの度合いを効果的に低減できる。 The outer surface of the mounting plate 32 (that is, the top surface of the mounting plate 32 in FIG. 1) is defined above the semiconductor chip 2 and defined as a mounting plane 321. That is, in the present embodiment, the flatness of the sensing chip 4 is ensured by setting the surface of the mounting plate 32 having a preferable flatness as the mounting plane 321 on which the sensing chip 4 is mounted. In addition, since the frame 3 has the rigidity of a preferable structure, the degree of warpage of the stacked sensor mounting structure 100 can be effectively reduced.
なお、前記フレーム３は設計者の要求に従いその構造を変更してもよい（下記の実施例に記載される通りである）。例えば、フレーム３には貫通孔が形成されていてもよく、その具体的説明は実施例１９に記載される通りである。 The structure of the frame 3 may be changed according to the designer's request (as described in the following embodiment). For example, a through hole may be formed in the frame 3, and a specific description thereof is as described in the nineteenth embodiment.
前記センシングチップ４は、本実施例において画像センシングチップで説明し、そのサイズが上記半導体チップ２のサイズよりも大きいが、本発明はセンシングチップ４のタイプを制限しない。なかでも、前記センシングチップ４は、対向する天面４１と底面４２と、上記天面４１と底面４２に垂直に接続されている外側縁（図示せず）とを備える。前記天面４１は、検知エリア４１１と、上記検知エリア４１１の外側に位置するワイヤボンディングエリア４１２と、前記検知エリア４１１とワイヤボンディングエリア４１２との間に位置する載置エリア４１３とを備える。そして、センシングチップ４は上記ワイヤボンディングエリア４１２に複数の接続パッド４１２１が設けられており、つまり、上記複数の接続パッド４１２１が前記検知エリア４１１の外側に位置する。 The sensing chip 4 is described as an image sensing chip in the present embodiment, and the size thereof is larger than the size of the semiconductor chip 2, but the present invention does not limit the type of the sensing chip 4. Among other things, the sensing chip 4 includes a top surface 41 and a bottom surface 42 facing each other, and an outer edge (not shown) connected perpendicularly to the top surface 41 and the bottom surface 42. The top surface 41 includes a detection area 411, a wire bonding area 412 positioned outside the detection area 411, and a placement area 413 positioned between the detection area 411 and the wire bonding area 412. The sensing chip 4 is provided with a plurality of connection pads 4121 in the wire bonding area 412, that is, the plurality of connection pads 4121 are located outside the detection area 411.
より詳しくは、前記検知エリア４１１は、本実施例において略矩形状（例えば、正方形又は長方形）を呈しており、上記検知エリア４１１の中心が天面４１の中心であってもよく（例えば、図１）、又は天面４１の中心と距離を置いている（図示せず）。前記ワイヤボンディングエリア４１２は、本実施例において角リング状を呈しており、その各部位の幅はほぼ一致していることが好ましいが、その具体的外形は設計者又は製造者の要求に従い調整してもよく、ここで制限されていない。例えば、本発明で示していない他の実施例において、前記ワイヤボンディングエリア４１２は検知エリア４１１の一側に位置する直線状領域又はＬ字状領域、又は検知エリア４１１の反対の両側に位置する二つの直線状領域であってもよい。 More specifically, the detection area 411 has a substantially rectangular shape (for example, a square or a rectangle) in the present embodiment, and the center of the detection area 411 may be the center of the top surface 41 (for example, FIG. 1) or a distance from the center of the top surface 41 (not shown). In the present embodiment, the wire bonding area 412 has a rectangular ring shape, and the widths of the respective parts are preferably substantially the same, but the specific outer shape is adjusted according to the requirements of the designer or manufacturer. There is no limit here. For example, in another embodiment not shown in the present invention, the wire bonding area 412 is a linear region or an L-shaped region located on one side of the detection area 411, or two opposite sides of the detection area 411. There may be two linear regions.
なお、前記センシングチップ４の底面４２は、前記フレーム３の載置平面３２１に固定されるとともに、その周辺部位が好ましくは環状台座３１の上方に設けられる。なかでも、本実施例中のセンシングチップ４はダイ接着剤（Ｄｉｅ Ａｔｔａｃｈ Ｅｐｏｘｙ、図示せず）を介してその底面４２をフレーム３の載置平面３２１に固定するが、具体的設置方式はこれに限定されるものではない。 The bottom surface 42 of the sensing chip 4 is fixed to the mounting plane 321 of the frame 3, and its peripheral portion is preferably provided above the annular pedestal 31. Among them, the sensing chip 4 in the present embodiment fixes its bottom surface 42 to the mounting plane 321 of the frame 3 through a die adhesive (Die Attach Epoxy, not shown). It is not limited.
前記複数本のワイヤ５は一端がそれぞれ基板１の複数のパッド１１１に接続され、他端がそれぞれセンシングチップ４の複数の接続パッド４１２１に接続される。上記各ワイヤ５は、逆ボンディング（ｒｅｖｅｒｓｅ ｂｏｎｄ）又は正ボンディング（ｆｏｒｗａｒｄ ｂｏｎｄ）の方式により形成されてもよい。さらに、各ワイヤ５が逆ボンディング方式を用いる場合、上記センシンチップ４の天面４１と各ワイヤ５との隣接部位には４５度以下の夾角（図示せず）が形成され得るので、各ワイヤ５の頂点が低い高さ位置に位置し、さらに光透過層６に触れることを回避することが可能であるが、本発明はこれに制限されない。 One end of each of the plurality of wires 5 is connected to the plurality of pads 111 of the substrate 1, and the other end thereof is connected to the plurality of connection pads 4121 of the sensing chip 4. Each wire 5 may be formed by reverse bonding or forward bonding. Further, when each wire 5 uses a reverse bonding method, a depression angle (not shown) of 45 degrees or less can be formed at a portion adjacent to the top surface 41 of the sensor chip 4 and each wire 5. Although it is possible to avoid that the vertex of is located at a low height position and further touch the light transmission layer 6, the present invention is not limited to this.
前記光透過層６は、本実施例において透明状を呈しており、平板状のガラスで説明するが、本発明は光透過層６のタイプを制限しない。例えば、前記光透過層６は光透過型（又は透明の）プラスチック材質から形成されてもよい。なかでも、前記光透過層６は、対向する（例えば、反対の両面に位置する）第１の表面６１と第２の表面６２と、第１の表面６１と第２の表面６２に垂直に接続されている外側縁（図示せず）とを有する。本実施例の第１の表面６１と第２の表面６２は同じサイズの矩形（例えば、正方形又は長方形）であり、前記光透過層６の第２の表面６２の面積が上記センシングチップ４の天面４１の面積よりも小さいが、これに限定されるものではない。 In the present embodiment, the light transmission layer 6 is transparent and will be described with a flat glass, but the present invention does not limit the type of the light transmission layer 6. For example, the light transmission layer 6 may be formed of a light transmission type (or transparent) plastic material. In particular, the light transmission layer 6 is perpendicularly connected to the first surface 61 and the second surface 62 facing each other (for example, located on opposite surfaces), and the first surface 61 and the second surface 62. And an outer edge (not shown). In the present embodiment, the first surface 61 and the second surface 62 are rectangular of the same size (for example, a square or a rectangle), and the area of the second surface 62 of the light transmission layer 6 is the top of the sensing chip 4. Although it is smaller than the area of the surface 41, it is not limited to this.
さらに、前記光透過層６は支持体７を介してセンシングチップ４の上方に設けられ、その第２の表面６２が前記センシングチップ４の天面４１と略平行であり、かつそれに向かっている。さらに、前記第２の表面６２は、上記センシングチップ４に向かっている中心エリア６２１と、環状を呈しており前記中心エリア６２１の外側を取り囲む支持エリア６２２と、前記支持エリア６２２の外側に位置する固定エリア６２３とを備える。なかでも、前記センシングチップ４の検知エリア４１１が第２の表面６２に正投影し投影領域（図示せず）が形成されており、前記投影領域は、第２の表面６２の中心エリアに相当するが、本発明はこれに限定されるものではない。上記支持体７に当接される第２の表面６２部位は支持エリア６２２に相当し、上記中心エリア６２１と支持エリア６２２以外における第２の表面６２部位は前記固定エリア６２３に相当する。 Further, the light transmission layer 6 is provided above the sensing chip 4 with the support 7 interposed therebetween, and the second surface 62 thereof is substantially parallel to the top surface 41 of the sensing chip 4 and faces it. Further, the second surface 62 is located outside the support area 622, a center area 621 facing the sensing chip 4, a support area 622 that has an annular shape and surrounds the outside of the center area 621. And a fixed area 623. Among these, the detection area 411 of the sensing chip 4 is orthographically projected onto the second surface 62 to form a projection area (not shown), and the projection area corresponds to the central area of the second surface 62. However, the present invention is not limited to this. The second surface 62 portion in contact with the support 7 corresponds to the support area 622, and the second surface 62 portion other than the center area 621 and the support area 622 corresponds to the fixed area 623.
また、上記光透過層６の第２の表面６２は、好ましくは各ワイヤ５に隣接設置されるがそれに接触せず、各ワイヤ５の頂点の基板１の上面１１に対する高さは、好ましくは前記光透過層６の第２の表面６２の基板１の上面１１に対する高さよりも小さいが、これに限定されるものではない。 Further, the second surface 62 of the light transmission layer 6 is preferably installed adjacent to each wire 5 but does not contact it, and the height of the apex of each wire 5 with respect to the upper surface 11 of the substrate 1 is preferably as described above. Although it is smaller than the height of the second surface 62 of the light transmission layer 6 with respect to the upper surface 11 of the substrate 1, it is not limited to this.
前記支持体７は、本実施例において環状を呈しており、その材質は例えばガラス接着樹脂（Ｇｌａｓｓ Ｍｏｕｎｔ Ｅｐｏｘｙ、ＧＭＥ）であるが、本発明はこれに制限されない。なかでも、前記支持体７の底縁が上記センシングチップ４の天面４１の載置エリア４１３に設けられ、つまり、前記支持体７の底縁が上記検知エリア４１１と複数の接続パッド４１２１との間に位置する。前記支持体７の頂縁が上記光透過層６の支持エリア６２２に当接され、つまり、前記支持体７が光透過層６の中心エリア６２１と固定エリア６２３に接触しない。これにより、前記積層型センサ実装構造１００は、上記支持体７を介して、前記光透過層６の第２の表面６２がセンシングチップ４の天面４１に略平行となることが可能であり、光透過層６の第２の表面６２とセンシングチップ４の天面４１が所定の距離に保持され得る。 In the present embodiment, the support body 7 has an annular shape, and the material thereof is, for example, glass adhesive resin (GME), but the present invention is not limited thereto. Among them, the bottom edge of the support 7 is provided in the mounting area 413 of the top surface 41 of the sensing chip 4, that is, the bottom edge of the support 7 is between the detection area 411 and the plurality of connection pads 4121. Located between. The top edge of the support 7 is brought into contact with the support area 622 of the light transmission layer 6, that is, the support 7 does not contact the central area 621 and the fixed area 623 of the light transmission layer 6. Thereby, the stacked sensor mounting structure 100 can have the second surface 62 of the light transmission layer 6 substantially parallel to the top surface 41 of the sensing chip 4 via the support 7. The second surface 62 of the light transmission layer 6 and the top surface 41 of the sensing chip 4 can be held at a predetermined distance.
前記実装体８は、本実施例において液状シール剤（ｌｉｑｕｉｄ ｃｏｍｐｏｕｎｄ）で説明するが、本発明はこれに制限されない。なかでも、前記実装体８が基板１の上面１１に設けられるとともに前記支持体７の外側縁、フレーム３の外側縁と一部の載置平面３２１、センシングチップ４の外側縁とワイヤボンディングエリア４１２、支持体７の外側縁、及び光透過層６の固定エリア６２３と外側縁を被覆する。さらに、上記実装体８の天面８１は、略斜面状又は曲面状を呈しており、そのエッジが前記光透過層６のエッジ（例えば、第１の表面６１のエッジ）に接続されているので、前記実装体８の天面が光透過層６の第１の表面６１と、鋭角をなす接線角度を形成しているが、本発明はこれに制限されない。また、上記各ワイヤ５及び各パッド１１１は全て上記実装体８に埋め込まれる。 The mounting body 8 will be described as a liquid compound in the present embodiment, but the present invention is not limited to this. Among them, the mounting body 8 is provided on the upper surface 11 of the substrate 1 and the outer edge of the support 7, the outer edge of the frame 3 and a part of the mounting plane 321, the outer edge of the sensing chip 4 and the wire bonding area 412. The outer edge of the support 7 and the fixed area 623 and the outer edge of the light transmission layer 6 are covered. Further, the top surface 81 of the mounting body 8 has a substantially slope shape or curved surface shape, and the edge thereof is connected to the edge of the light transmission layer 6 (for example, the edge of the first surface 61). Although the top surface of the mounting body 8 forms an acute angle with the first surface 61 of the light transmission layer 6, the present invention is not limited to this. The wires 5 and the pads 111 are all embedded in the mounting body 8.
上述したように、本実施例に開示される積層型センサ実装構造１００において、基板１にフレーム３が設けられるので、全体の構造強度を向上でき、センシングチップ４が安定性の高いフレーム３に設けられ得ることにより、その平坦度を制御する。なお、センシングチップ４のワイヤボンディングエリア４１２がフレーム３によって強固に支持されるので、上記複数本のワイヤ５は、ワイヤボンディング成形の過程において、センシングチップ４のワイヤボンディングエリア４１２に効果的に接続され、他の部品にダメージを与えることを回避することが可能である。 As described above, since the frame 3 is provided on the substrate 1 in the multilayer sensor mounting structure 100 disclosed in the present embodiment, the overall structural strength can be improved, and the sensing chip 4 is provided on the highly stable frame 3. It can control the flatness. Since the wire bonding area 412 of the sensing chip 4 is firmly supported by the frame 3, the plurality of wires 5 are effectively connected to the wire bonding area 412 of the sensing chip 4 in the process of wire bonding molding. It is possible to avoid damaging other parts.
また、前記積層型センサ実装構造１００のセンシングチップ４と半導体チップ２がフレーム３によって離隔されるので、センシングチップ４は、半導体チップ２による熱エネルギーにより直接影響されず、前記半導体チップ２による熱エネルギーはさらに基板１及びその下面１２における金属ボール２１の伝導を介して散逸できることで、積層型センサ実装構造１００の放熱効率を効果的に向上させる。 In addition, since the sensing chip 4 and the semiconductor chip 2 of the stacked sensor mounting structure 100 are separated by the frame 3, the sensing chip 4 is not directly affected by the thermal energy from the semiconductor chip 2, and the thermal energy from the semiconductor chip 2 is not affected. Further, the heat dissipation efficiency of the stacked sensor mounting structure 100 is effectively improved by being dissipated through conduction of the metal balls 21 on the substrate 1 and the lower surface 12 thereof.
［実施例２］
図２に示すように、それは本発明の実施例２であり、本実施例は上記実施例１とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記フレーム３である。以下に本実施例と上記実施例１との相違点を説明する。
[Example 2]
As shown in FIG. 2, this is the second embodiment of the present invention, which is substantially the same as the first embodiment, and the description of the same points of the two embodiments is omitted, but the main differences are the same. Is the frame 3. The difference between the present embodiment and the first embodiment will be described below.
本実施例において、前記フレーム３の環状台座３１と載置板３２は一体成形された構造ではなく、前記環状台座３１は例えば接着剤層（図示せず）で載置板３２の周縁に接続され、その外側縁が載置板３２の外側縁に切り揃えられるが、本発明はこれに制限されない。なかでも、前記接着剤層は、光硬化型粘着剤、熱硬化型粘着剤、上記光硬化型粘着剤と熱硬化型粘着剤とが混合された混合型粘着剤、又は粘着剤膜であってもよく、本発明はここで制限されていない。 In the present embodiment, the annular pedestal 31 and the mounting plate 32 of the frame 3 are not integrally formed, and the annular pedestal 31 is connected to the periphery of the mounting plate 32 by, for example, an adhesive layer (not shown). The outer edge is trimmed to the outer edge of the mounting plate 32, but the present invention is not limited to this. Among them, the adhesive layer is a photocurable pressure-sensitive adhesive, a thermosetting pressure-sensitive adhesive, a mixed pressure-sensitive adhesive in which the photocurable pressure-sensitive adhesive and the thermosetting pressure-sensitive adhesive are mixed, or a pressure-sensitive adhesive film. Of course, the invention is not limited here.
さらに、前記環状台座３１と載置板３２は一体成形された構造ではないので、上記環状台座３１の材質は上記載置板３２の材質と同じでも、又は異なってもよい。例えば、前記載置板３２又は環状台座３１の材質は、熱膨張係数（Ｃｏｅｆｆｉｃｉｅｎｔ ｏｆ ｔｈｅｒｍａｌ ｅｘｐａｎｓｉｏｎ、ＣＴＥ）が１０よりも小さい剛性材料、例えば、ガラス材質（ＣＴＥ＝７．２ｐｐｍ／°Ｃ）、シリコン基材（ＣＴＥ＝２．６ｐｐｍ／°Ｃ）、金属、又はセラミックを選んで用いてもよく、本発明はここで制限されていない。 Further, since the annular pedestal 31 and the mounting plate 32 are not integrally formed, the material of the annular pedestal 31 may be the same as or different from the material of the mounting plate 32 described above. For example, the mounting plate 32 or the annular pedestal 31 is made of a rigid material having a coefficient of thermal expansion (CTE) smaller than 10, for example, a glass material (CTE = 7.2 ppm / ° C.), silicon. A substrate (CTE = 2.6 ppm / ° C.), metal, or ceramic may be selected and used, and the present invention is not limited here.
［実施例３］
図３に示すように、それは本発明の実施例３であり、本実施例は上記実施例２とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は本実施例の積層型センサ実装構造１００が複数の受動電子部品Ｅをさらに備えることである。以下に本実施例と上記実施例２との相違点を説明する。
[Example 3]
As shown in FIG. 3, it is the third embodiment of the present invention, which is substantially the same as the second embodiment, and the explanation of the same points of the two embodiments is omitted, but the main differences are as follows. Is that the stacked sensor mounting structure 100 of the present embodiment further includes a plurality of passive electronic components E. The difference between the present embodiment and the second embodiment will be described below.
本実施例において、前記複数の受動電子部品Ｅが前記基板１の上面１１に取り付けられ、その中の一部の受動電子部品Ｅは基板１とフレーム３によって囲まれる空間内に位置し、半導体チップ２と間隔を置いて設けられ、他の受動電子部品Ｅは上記フレーム３の外側に位置するとともに前記実装体８に埋め込まれてもよい。 In the present embodiment, the plurality of passive electronic components E are attached to the upper surface 11 of the substrate 1, and some of the passive electronic components E are located in a space surrounded by the substrate 1 and the frame 3, and the semiconductor chip The other passive electronic component E may be located outside the frame 3 and embedded in the mounting body 8.
［実施例４］
図４に示すように、それは本発明の実施例４であり、本実施例は上記実施例２とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は本実施例の積層型センサ実装構造１００がシーラント９をさらに備えることである。以下に本実施例と上記実施例２との相違点を説明する。
[Example 4]
As shown in FIG. 4, this is the fourth embodiment of the present invention, which is almost the same as the second embodiment, and the explanation of the same points of the two embodiments is omitted, but the main difference is the same. Is that the laminated sensor mounting structure 100 of the present embodiment further includes a sealant 9. The difference between the present embodiment and the second embodiment will be described below.
本実施例において、前記フレーム３と基板１によって囲まれる空間には上記シーラント９が部分的に充填されているので、前記半導体チップ２がシーラント９に埋め込まれる。さらに、前記環状台座３１が基板１の上面１１に固定されるが、載置板３２に接続されていない場合、前記環状台座３１にシーラント９を充填できることで、前記半導体チップ２を埋め込んでから、前記載置板３２を環状台座３１の頂縁に固定する。 In this embodiment, since the sealant 9 is partially filled in the space surrounded by the frame 3 and the substrate 1, the semiconductor chip 2 is embedded in the sealant 9. Furthermore, when the annular pedestal 31 is fixed to the upper surface 11 of the substrate 1 but is not connected to the mounting plate 32, the annular pedestal 31 can be filled with the sealant 9, so that the semiconductor chip 2 is embedded. The mounting plate 32 is fixed to the top edge of the annular pedestal 31.
［実施例５］
図５と図６に示すように、それらは本発明の実施例５であり、本実施例は上記実施例２とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記フレーム３である。以下に本実施例と上記実施例２との相違点を説明する。
[Example 5]
As shown in FIGS. 5 and 6, these are the fifth embodiment of the present invention, which is substantially the same as the second embodiment, and the description of the same points of the two embodiments is omitted. The main difference is the frame 3. The difference between the present embodiment and the second embodiment will be described below.
本実施例において、前記フレーム３はその載置平面３２１の外縁から環状を呈する切欠き３３を凹設形成しており、前記切欠き３３がセンシングチップ４の外側に位置する。なかでも、前記切欠き３３の載置平面３２１からの凹設の深さは、設計者の要求に従い変更してもよく、本発明はここで制限されていない。例えば、前記切欠き３３は、上記フレーム３の載置板３２のみに凹設されてもよく（例えば、図５）、又はフレーム３の載置板３２から環状台座３１に凹設されてもよい（例えば、図６）。 In the present embodiment, the frame 3 is formed with a notch 33 having an annular shape from the outer edge of the mounting plane 321, and the notch 33 is located outside the sensing chip 4. In particular, the depth of the recess from the mounting plane 321 of the notch 33 may be changed according to the requirements of the designer, and the present invention is not limited here. For example, the notch 33 may be recessed only on the mounting plate 32 of the frame 3 (for example, FIG. 5), or may be recessed from the mounting plate 32 of the frame 3 on the annular pedestal 31. (For example, FIG. 6).
図７に示すように、それは本発明の実施例６であり、本実施例は上記実施例２とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記光透過層６である。以下に本実施例と上記実施例２との相違点を説明する。 As shown in FIG. 7, this is the sixth embodiment of the present invention, which is almost the same as the second embodiment, and the explanation of the same points of the two embodiments is omitted, but the main differences are the same. Is the light transmission layer 6. The difference between the present embodiment and the second embodiment will be described below.
本実施例において、前記実装体８が前記階段部６３に付着するように、前記光透過層６の頂部周縁には階段部６３が形成されていてもよい。なかでも、上記階段部の具体的構造は、設計者の要求に従い変更してもよく、本発明はここで制限されていない。例えば、前記階段部６３は、環状、Ｌ字状、又は長尺状であってもよい。 In this embodiment, a stepped portion 63 may be formed on the periphery of the top of the light transmission layer 6 so that the mounting body 8 adheres to the stepped portion 63. In particular, the specific structure of the stepped portion may be changed according to the requirements of the designer, and the present invention is not limited here. For example, the stepped portion 63 may be annular, L-shaped, or elongated.
［実施例７］
図８に示すように、それは本発明の実施例７であり、本実施例は上記実施例２とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記支持体７である。以下に本実施例と上記実施例２との相違点を説明する。
[Example 7]
As shown in FIG. 8, this is the seventh embodiment of the present invention, which is almost the same as the second embodiment, and the explanation of the same points of the two embodiments is omitted, but the main difference is the same. Is the support 7. The difference between the present embodiment and the second embodiment will be described below.
本実施例において、前記支持体７は頂縁が光透過層６の支持エリア６２２に当接され、その底縁がセンシングチップ４の天面４１のワイヤボンディングエリア４１２に設けられる。なかでも、上記支持体７は前記複数の接続パッド４１２１と各ワイヤ５の一部を被覆し、各ワイヤ５の他の一部が前記実装体８に埋め込まれる。別の観点からは、本実施例中のセンシングチップ４の天面４１は、検知エリア４１１と、検知エリア４１１の外側に位置するワイヤボンディングエリア４１２のみを有し、載置エリア４１３を有しない。別の観点からは、前記センシングチップ４の天面４１は、ワイヤボンディングエリア４１２と載置エリア４１３とが重なり合うと見なされてもよい。 In the present embodiment, the support 7 has a top edge in contact with the support area 622 of the light transmission layer 6 and a bottom edge provided in the wire bonding area 412 of the top surface 41 of the sensing chip 4. In particular, the support 7 covers the plurality of connection pads 4121 and a part of each wire 5, and the other part of each wire 5 is embedded in the mounting body 8. From another viewpoint, the top surface 41 of the sensing chip 4 in the present embodiment has only the detection area 411 and the wire bonding area 412 positioned outside the detection area 411, and does not have the placement area 413. From another viewpoint, the top surface 41 of the sensing chip 4 may be regarded as the wire bonding area 412 and the mounting area 413 overlapping.
［実施例８］
図９に示すように、それは本発明の実施例８であり、本実施例は上記実施例７とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記支持体７である。以下に本実施例と上記実施例７との相違点を説明する。
[Example 8]
As shown in FIG. 9, this is the eighth embodiment of the present invention, which is almost the same as the seventh embodiment, and the description of the same points of the two embodiments is omitted, but the main differences are the same. Is the support 7. The difference between the present embodiment and the above embodiment 7 will be described below.
本実施例において、前記支持体７は頂縁が光透過層６の支持エリア６２２に当接され、その底縁の一部がセンシングチップ４の天面に設けられ、複数の接続パッド４１２１と各ワイヤ５の一部を被覆し、各ワイヤ５の他の一部が前記実装体８に埋め込まれる。 In the present embodiment, the support 7 has a top edge in contact with the support area 622 of the light transmission layer 6, and a part of the bottom edge is provided on the top surface of the sensing chip 4. A part of the wire 5 is covered, and the other part of each wire 5 is embedded in the mounting body 8.
より詳しくは、前記センシングチップ４の側辺部位４３（例えば、図９中のセンシングチップ４の右側辺部位）に何れの接続パッド４１２１も設けられておらず、前記支持体７は、第１の支持部７１と第２の支持部７２とを備える。なかでも、前記第１の支持部７１は頂縁が前記光透過層６の支持エリア６２２に当接され、その底縁が上記センシングチップ４の天面４１のワイヤボンディングエリア４１２に設けられ、複数の接続パッド４１２１と各ワイヤ５の一部を被覆する。前記第２の支持部７２は頂縁が前記光透過層６の支持エリア６２２に当接され、その底縁が前記載置平面３２１に設けられるとともに上記側辺部位４３に近接し、前記第２の支持部７２は何れのワイヤ５にも接触しない。 More specifically, no connection pad 4121 is provided on the side part 43 of the sensing chip 4 (for example, the right side part of the sensing chip 4 in FIG. 9), and the support 7 A support part 71 and a second support part 72 are provided. Among these, the top edge of the first support portion 71 is in contact with the support area 622 of the light transmission layer 6, and the bottom edge is provided in the wire bonding area 412 of the top surface 41 of the sensing chip 4. The connection pad 4121 and a part of each wire 5 are covered. The top edge of the second support part 72 is in contact with the support area 622 of the light transmission layer 6, the bottom edge thereof is provided on the mounting plane 321, and close to the side part 43, The support portion 72 does not contact any of the wires 5.
なお、前記第２の支持部７２は、本実施例において互いに積み重なる２層式構造で説明するが、本発明はこれに制限されない。例えば、本発明で示していない他の実施例において、前記第２の支持部７２は一体成形されたワンピース構造であってもよい。 In addition, although the said 2nd support part 72 demonstrates in the present Example by the 2 layer type structure stacked | stacked mutually, this invention is not restrict | limited to this. For example, in another embodiment not shown in the present invention, the second support portion 72 may have an integrally formed one-piece structure.
また、前記第１の支持部７１と第２の支持部７２は一体的に接続される構造であってもよく、例えば、第２の支持部７２の下地層構造を成形してから、互いに接続され環状を呈する第１の支持部７１と第２の支持部７２のトップ層構造を成形し、第２の支持部７２のトップ層構造が上記下地層構造に積み重なる。或いは、前記第１の支持部７１と第２の支持部７２は互いに分離される構造であってもよく、本発明はここで制限されていない。 Further, the first support part 71 and the second support part 72 may be integrally connected. For example, after forming the base layer structure of the second support part 72, the first support part 71 and the second support part 72 are connected to each other. The top layer structure of the first support part 71 and the second support part 72 having an annular shape is formed, and the top layer structure of the second support part 72 is stacked on the base layer structure. Alternatively, the first support portion 71 and the second support portion 72 may be separated from each other, and the present invention is not limited here.
なお、本実施例は前記センシングチップ４の側辺部位４３に何れの接続パッド４１２１も設けられていないことにより説明し、前記第２の支持部７２は上記側辺部位４３に対応して設置されるが、本発明はこれに制限されない。例えば、本発明で示していない他の実施例において、前記センシングチップ４は少なくとも二つの側辺部位４３に何れの接続パッド４１２１も設けられていなくてもよい。 This embodiment will be described by not providing any connection pads 4121 in the side portion 43 of the sensing chip 4, and the second support portion 72 is installed corresponding to the side portion 43. However, the present invention is not limited to this. For example, in another embodiment not shown in the present invention, the sensing chip 4 may not be provided with any connection pads 4121 in at least two side portions 43.
［実施例９］
図１０に示すように、それは本発明の実施例９であり、本実施例は上記実施例８とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記支持体７である。以下に本実施例と上記実施例８との相違点を説明する。
[Example 9]
As shown in FIG. 10, it is the ninth embodiment of the present invention, which is almost the same as the eighth embodiment, and the explanation of the same points of the two embodiments is omitted, but the main difference is Is the support 7. The difference between the present embodiment and the above embodiment 8 will be described below.
本実施例において、前記支持体７は上記フレーム３の載置平面３２１に設けられるとともに前記センシングチップ４の外側縁に位置し、各ワイヤ５の一部を被覆し、各ワイヤ５の他の一部が前記実装体８に埋め込まれる。より詳しくは、前記支持体７は、支持層７３と接着層７４とを備える。前記支持層７３は、上記フレーム３の載置平面３２１に設けられ、前記センシングチップ４の外側縁に位置し、何れのワイヤ５にも接触しない。前記接着層７４は支持層７３に設けられ、その頂縁が前記光透過層６の支持エリア６２２に当接され、各ワイヤ５の一部が接着層７４に埋め込まれる。なかでも、前記支持層７３の載置平面３２１に対する高さは前記センシングチップ４の天面４１の載置平面３２１に対する高さとほぼ等しく、各ワイヤ５の一部が接着層７４に埋め込まれるが、本発明はこれに制限されない。 In the present embodiment, the support 7 is provided on the mounting plane 321 of the frame 3 and is positioned on the outer edge of the sensing chip 4 so as to cover a part of each wire 5 and the other one of the wires 5. The part is embedded in the mounting body 8. More specifically, the support 7 includes a support layer 73 and an adhesive layer 74. The support layer 73 is provided on the mounting plane 321 of the frame 3, is located on the outer edge of the sensing chip 4, and does not contact any wires 5. The adhesive layer 74 is provided on the support layer 73, the top edge thereof is in contact with the support area 622 of the light transmission layer 6, and a part of each wire 5 is embedded in the adhesive layer 74. Among them, the height of the support layer 73 with respect to the mounting plane 321 is substantially equal to the height of the top surface 41 of the sensing chip 4 with respect to the mounting plane 321, and a part of each wire 5 is embedded in the adhesive layer 74. The present invention is not limited to this.
なお、前記支持体７の支持層７３及び接着層７４は、本実施例において二つの部材で説明するが、本発明はこれに制限されない。例えば、本発明で示していない他の実施例において、前記支持層７３及び接着層７４は一体成形されたワンピース部材であってもよい。 In addition, although the support layer 73 and the adhesive layer 74 of the said support body 7 are demonstrated with two members in a present Example, this invention is not restrict | limited to this. For example, in another embodiment not shown in the present invention, the support layer 73 and the adhesive layer 74 may be an integrally formed one-piece member.
なお、本実施例の支持体７は支持層７３を介してセンシングチップ４の外側縁に接続されているが、本発明で示していない他の実施例において、前記支持体７とセンシングチップ４の外側縁との間に隙間が残っていてもよい。 In addition, although the support body 7 of a present Example is connected to the outer edge of the sensing chip 4 via the support layer 73, in the other Example which is not shown by this invention, the said support body 7 and the sensing chip 4 of FIG. A gap may remain between the outer edge.
［実施例１０］
図１１に示すように、それは本発明の実施例１０であり、本実施例は上記実施例８とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記実装体８である。以下に本実施例と上記実施例８との相違点を説明する。
[Example 10]
As shown in FIG. 11, this is the tenth embodiment of the present invention, which is almost the same as the eighth embodiment, and the description of the same points of the two embodiments is omitted, but the main differences are the same. Is the mounting body 8. The difference between the present embodiment and the above embodiment 8 will be described below.
本実施例において、前記実装体８は、液状シール剤８２とモールドシール剤８３（ｍｏｌｄｉｎｇ ｃｏｍｐｏｕｎｄ）とを備え、本実施例の液状シール剤８２は上記実施例で説明されたので、ここで重複する説明は省略する。なお、前記モールドシール剤８３は上記液状シール剤８２の天面８２１に形成され、その天面８３１が前記光透過層６の第１の表面６１と平行となるとともにそれよりも低く、略５０μｍから１００μｍのオーバーフロー防止距離Ｄが離れている。 In the present embodiment, the mounting body 8 includes a liquid sealant 82 and a mold sealant 83 (molding compound). Since the liquid sealant 82 of the present embodiment has been described in the above embodiment, it overlaps here. Description is omitted. The mold sealant 83 is formed on the top surface 821 of the liquid sealant 82, and the top surface 831 is parallel to the first surface 61 of the light transmission layer 6 and lower than that, approximately 50 μm. The overflow prevention distance D of 100 μm is separated.
［実施例１１］
図１２に示すように、それは本発明の実施例１１であり、本実施例は上記実施例７とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記実装体８である。以下に本実施例と上記実施例７との相違点を説明する。
[Example 11]
As shown in FIG. 12, this is the eleventh embodiment of the present invention, which is almost the same as the seventh embodiment, and the description of the same points of the two embodiments will be omitted, but the main difference. Is the mounting body 8. The difference between the present embodiment and the above embodiment 7 will be described below.
本実施例において、前記実装体８はモールドシール剤８３である。なかでも、前記モールドシール剤８３（実装体８）が基板１の上面１１に設けられるとともに、前記支持体７の外側縁、フレーム３の外側縁と一部の載置平面３２１、センシングチップ４の外側縁、及び前記光透過層６の固定エリア６２３と一部の外側縁を被覆する。なお、前記モールドシール剤８３（実装体８）の天面８３１は、平面状を呈しており前記光透過層６の第１の表面６１よりも低く、略５０μｍから１００μｍのオーバーフロー防止距離Ｄが離れている。 In this embodiment, the mounting body 8 is a mold sealant 83. Among them, the mold sealant 83 (mounting body 8) is provided on the upper surface 11 of the substrate 1, and the outer edge of the support 7, the outer edge of the frame 3 and a part of the mounting plane 321, and the sensing chip 4. The outer edge and the fixed area 623 and a part of the outer edge of the light transmission layer 6 are covered. The top surface 831 of the mold sealant 83 (mounting body 8) has a flat shape and is lower than the first surface 61 of the light transmission layer 6, and has an overflow prevention distance D of approximately 50 μm to 100 μm. ing.
［実施例１２］
図１３に示すように、それは本発明の実施例１２であり、本実施例は上記実施例２とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は本実施例の積層型センサ実装構造１００が複数の半導体チップ２を備えることである。以下に本実施例と上記実施例２との相違点を説明する。
[Example 12]
As shown in FIG. 13, it is the twelfth embodiment of the present invention, which is almost the same as the second embodiment, and the explanation of the same points of the two embodiments is omitted, but the main difference is Is that the stacked sensor mounting structure 100 of the present embodiment includes a plurality of semiconductor chips 2. The difference between the present embodiment and the second embodiment will be described below.
本実施例において、前記複数の半導体チップ２が互いに積み重なって基板１の上面１１に設けられ、各半導体チップ２は全て前記基板１の上面１１にワイヤボンディングされることで、基板１と電気的な接続を達成するが、本発明はこれに制限されない。 In this embodiment, the plurality of semiconductor chips 2 are stacked on each other and provided on the upper surface 11 of the substrate 1, and all the semiconductor chips 2 are electrically bonded to the upper surface 11 of the substrate 1. Although the connection is achieved, the present invention is not limited to this.
［実施例１３］
図１４に示すように、それは本発明の実施例１３であり、本実施例は上記実施例１２とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は本実施例の積層型センサ実装構造１００が埋め込み式チップＣをさらに備えることである。以下に本実施例と上記実施例１２との相違点を説明する。
[Example 13]
As shown in FIG. 14, this is the thirteenth embodiment of the present invention, which is substantially the same as the above-described embodiment 12, and the description of the same points of the two embodiments is omitted, but the main differences are the same. Is that the stacked sensor mounting structure 100 of this embodiment further includes an embedded chip C. The difference between the present embodiment and the above embodiment 12 will be described below.
本実施例において、前記埋め込み式チップＣが上記基板１に埋め込まれ、本発明で示していない他の実施例において、基板１に埋め込まれる埋め込み式チップＣの数は複数であってもよい。 In this embodiment, the embedded chip C is embedded in the substrate 1, and in other embodiments not shown in the present invention, the number of embedded chips C embedded in the substrate 1 may be plural.
［実施例１４］
図１５及び図１６に示すように、それらは本発明の実施例１４であり、本実施例は上記実施例７とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記半導体チップ２である。以下に本実施例と上記実施例７との相違点を説明する。
[Example 14]
As shown in FIGS. 15 and 16, these are the fourteenth embodiment of the present invention, which is almost the same as the seventh embodiment, and the description of the same points of the two embodiments is omitted. The main difference is the semiconductor chip 2. The difference between the present embodiment and the above embodiment 7 will be described below.
本実施例において、前記半導体チップ２は基板１にワイヤボンディングされていない。より詳しくは、前記半導体チップ２は複数の金属ボール２１で基板１の上面１１に溶接されることで、基板１と電気的な接続を達成する。なお、前記半導体チップ２と上記基板１との間にアンダーフィル剤２２（ｕｎｄｅｒｆｉｌｌ）が選択的に充填されていてもよく、複数の前記金属ボール２１が前記アンダーフィル剤２２に埋め込まれる（例えば、図１６）。 In this embodiment, the semiconductor chip 2 is not wire bonded to the substrate 1. More specifically, the semiconductor chip 2 is electrically connected to the substrate 1 by being welded to the upper surface 11 of the substrate 1 with a plurality of metal balls 21. An underfill agent 22 (underfill) may be selectively filled between the semiconductor chip 2 and the substrate 1, and a plurality of the metal balls 21 are embedded in the underfill agent 22 (for example, FIG. 16).
［実施例１５］
図１７に示すように、それは本発明の実施例１５であり、本実施例は上記実施例１２とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記基板１である。以下に本実施例と上記実施例１２との相違点を説明する。
[Example 15]
As shown in FIG. 17, this is the fifteenth embodiment of the present invention, which is substantially the same as the above-mentioned embodiment 12, and the description of the same points of the two embodiments is omitted, but the main differences are the same. Is the substrate 1. The difference between the present embodiment and the above embodiment 12 will be described below.
本実施例において、前記基板１の上面１１には収容溝１１２が凹設形成されており、前記複数の半導体チップ２は、上記収容溝１１２に位置するとともに、全て前記収容溝１１２の溝底にワイヤボンディングされることで、各半導体チップ２が基板１と電気的な接続を達成する。 In this embodiment, a receiving groove 112 is formed in the upper surface 11 of the substrate 1, and the plurality of semiconductor chips 2 are located in the receiving groove 112 and are all formed in the groove bottom of the receiving groove 112. Each semiconductor chip 2 achieves electrical connection with the substrate 1 by wire bonding.
［実施例１６］
図１８に示すように、それは本発明の実施例１６であり、本実施例は上記実施例１５とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記基板１である。以下に本実施例と上記実施例１５との相違点を説明する。
[Example 16]
As shown in FIG. 18, this is the embodiment 16 of the present invention, which is almost the same as the embodiment 15 described above, and the explanation of the same points of the two embodiments is omitted, but the main difference. Is the substrate 1. The difference between the present embodiment and the above embodiment 15 will be described below.
本実施例において、前記基板１の上面１１は上記フレーム３と収容溝１１２との間にワイヤボンディング領域１１３を残しており、複数の前記半導体チップ２の少なくとも一つの半導体チップ２（例えば、図１８に上方に位置する半導体チップ２）が前記ワイヤボンディング領域１１３にワイヤボンディングされ、他の半導体チップ２（例えば、図１８に下方に位置する半導体チップ２）が前記収容溝１１２の溝底にワイヤボンディングされることで、各半導体チップ２が基板１と電気的な接続を達成する。 In this embodiment, the upper surface 11 of the substrate 1 leaves a wire bonding region 113 between the frame 3 and the receiving groove 112, and at least one semiconductor chip 2 (for example, FIG. 18) of the plurality of semiconductor chips 2. The semiconductor chip 2) located above is wire-bonded to the wire bonding region 113, and another semiconductor chip 2 (for example, the semiconductor chip 2 located below in FIG. 18) is wire-bonded to the groove bottom of the receiving groove 112. As a result, each semiconductor chip 2 achieves electrical connection with the substrate 1.
［実施例１７］
図１９に示すように、それは本発明の実施例１７であり、本実施例は上記実施例１５とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記フレーム３である。以下に本実施例と上記実施例１５との相違点を説明する。
[Example 17]
As shown in FIG. 19, it is Embodiment 17 of the present invention, which is almost the same as Embodiment 15 described above, and the explanation of the same points of the two embodiments is omitted, but the main difference is Is the frame 3. The difference between the present embodiment and the above embodiment 15 will be described below.
本実施例において、前記フレーム３がさらに前記基板１の上面１１に固着される載置板３２に限定され、前記載置板３２の外面が載置平面３２１と定義されている。なかでも、前記載置板３２の周縁は例えば接着剤層（図示せず）で前記基板１の上面１１に接続され、上記収容溝１１２を閉鎖するが、本発明はこれに制限されない。さらに、前記接着剤層は、光硬化型粘着剤、熱硬化型粘着剤、上記光硬化型粘着剤と熱硬化型粘着剤とが混合された混合型粘着剤、又は粘着剤膜であってもよく、本発明はここで制限されていない。 In the present embodiment, the frame 3 is further limited to the mounting plate 32 fixed to the upper surface 11 of the substrate 1, and the outer surface of the mounting plate 32 is defined as a mounting plane 321. In particular, the peripheral edge of the mounting plate 32 is connected to the upper surface 11 of the substrate 1 with, for example, an adhesive layer (not shown) and closes the receiving groove 112, but the present invention is not limited to this. Furthermore, the adhesive layer may be a photocurable pressure-sensitive adhesive, a thermosetting pressure-sensitive adhesive, a mixed pressure-sensitive adhesive in which the photocurable pressure-sensitive adhesive and the thermosetting pressure-sensitive adhesive are mixed, or a pressure-sensitive adhesive film. Well, the invention is not limited here.
［実施例１８］
図２０に示すように、それは本発明の実施例１８であり、本実施例は上記実施例１７とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は本実施例の積層型センサ実装構造１００がシーラント９’をさらに備えることである。以下に本実施例と上記実施例１７との相違点を説明する。
[Example 18]
As shown in FIG. 20, this is an embodiment 18 of the present invention, which is substantially the same as the embodiment 17, and the explanation of the same points of the two embodiments is omitted, but the main difference Is that the stacked sensor mounting structure 100 of the present embodiment further includes a sealant 9 ′. The difference between the present embodiment and the above embodiment 17 will be described below.
本実施例において、前記半導体チップ２が前記シーラント９’に埋め込まれるように、前記収容溝１１２に上記シーラント９’が充填されている。 In this embodiment, the sealant 9 'is filled in the receiving groove 112 so that the semiconductor chip 2 is embedded in the sealant 9'.
［実施例１９］
図２１に示すように、それは本発明の実施例１９であり、本実施例は上記実施例１とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は前記フレーム３である。以下に本実施例と上記実施例１との相違点を説明する。
[Example 19]
As shown in FIG. 21, this is the nineteenth embodiment of the present invention, which is almost the same as the first embodiment, and the explanation of the same points of the two embodiments is omitted, but the main differences are the same. Is the frame 3. The difference between the present embodiment and the first embodiment will be described below.
本実施例において、前記フレーム３の載置板３２に貫通孔３２２が設けられており、前記センシングチップ４が上記貫通孔３２２を遮蔽する。なかでも、本実施例の貫通孔３２２は前記半導体チップ２の真上に位置しないが、それのフレーム３に形成される具体的位置はこれに限定されるものではない。これにより、フレーム３と基板１との間の粘着剤（図示せず）をベークし、前記フレーム３が基板１の上面１１に固定される過程において、上記フレーム３と基板１との間の空気が加熱されて膨張し、前記貫通孔３２２を介して排気され、さらにフレーム３（載置平面３２１）の平坦度を保持することができる。 In this embodiment, a through hole 322 is provided in the mounting plate 32 of the frame 3, and the sensing chip 4 shields the through hole 322. In particular, the through hole 322 of this embodiment is not located directly above the semiconductor chip 2, but the specific position formed in the frame 3 is not limited to this. As a result, the adhesive (not shown) between the frame 3 and the substrate 1 is baked, and the air between the frame 3 and the substrate 1 in the process of fixing the frame 3 to the upper surface 11 of the substrate 1. Is heated and expanded, exhausted through the through-hole 322, and the flatness of the frame 3 (mounting plane 321) can be maintained.
［実施例２０］
図２２に示すように、それは本発明の実施例２０であり、本実施例は上記実施例１９とほぼ同じであり、二つの実施例の同じ点については説明を省略するが、その主な差異は本実施例の積層型センサ実装構造１００が少なくとも三つの半導体チップ２、２’、２’’を備えることである。以下に本実施例と上記実施例１９との相違点を説明する。
[Example 20]
As shown in FIG. 22, this is an embodiment 20 of the present invention, which is almost the same as the embodiment 19, and the explanation of the same points of the two embodiments is omitted, but the main difference Is that the stacked sensor mounting structure 100 of this embodiment includes at least three semiconductor chips 2, 2 ′, 2 ″. The difference between the present embodiment and the embodiment 19 will be described below.
本実施例において、前記三つの半導体チップ２、２’、２’’はそれぞれ異なる固定技術を用い、それぞれ第１の半導体チップ２、第２の半導体チップ２’、及び第３の半導体チップ２’’と名付けられ得ることで、互いに仕分けされ説明しやすくなるが、前記「第１」、「第２」、及び「第３」は他の物理的意味を有しない。 In this embodiment, the three semiconductor chips 2, 2 ′, 2 ″ use different fixing techniques, and the first semiconductor chip 2, the second semiconductor chip 2 ′, and the third semiconductor chip 2 ′, respectively. “1”, “second”, and “third” have no other physical meaning, although they can be classified and explained easily.
前記第１の半導体チップ２は複数の金属ボール２１で基板１の上面１１に溶接されることで、第１の半導体チップ２と基板１との間が電気的な接続を達成する。なお、前記第１の半導体チップ２と上記基板１との間にアンダーフィル剤２２（ｕｎｄｅｒｆｉｌｌ）が充填されており、複数の前記金属ボール２１が前記アンダーフィル剤２２に埋め込まれる。 The first semiconductor chip 2 is welded to the upper surface 11 of the substrate 1 with a plurality of metal balls 21, thereby achieving electrical connection between the first semiconductor chip 2 and the substrate 1. An underfill agent 22 (underfill) is filled between the first semiconductor chip 2 and the substrate 1, and a plurality of the metal balls 21 are embedded in the underfill agent 22.
前記第２の半導体チップ２’が第１の半導体チップ２に積み重なり、前記基板１の上面１１にワイヤボンディングされることで、第２の半導体チップ２’が基板１と電気的な接続を達成する。 The second semiconductor chip 2 ′ is stacked on the first semiconductor chip 2 and wire-bonded to the upper surface 11 of the substrate 1, so that the second semiconductor chip 2 ′ is electrically connected to the substrate 1. .
前記第３の半導体チップ２’’が前記基板１の上面１１に設けられるとともに、上記互いに積み重なる第１の半導体チップ２と第２の半導体チップ２’の一側に位置し、前記第３の半導体チップ２’’が前記基板１の上面１１にワイヤボンディングされることで、第３の半導体チップ２’’が基板１と電気的な接続を達成する。 The third semiconductor chip 2 ″ is provided on the upper surface 11 of the substrate 1 and is located on one side of the first semiconductor chip 2 and the second semiconductor chip 2 ′ that are stacked on each other. The chip 2 ″ is wire-bonded to the upper surface 11 of the substrate 1 so that the third semiconductor chip 2 ″ is electrically connected to the substrate 1.
なお、前記第１の半導体チップ２、第２の半導体チップ２’、及び第３の半導体チップ２’’のタイプは、設計者の要求に従い調整し変更してもよく、例えば、画像信号プロセッサ（ｉｍａｇｅ ｓｉｇｎａｌ ｐｒｏｃｅｓｓｏｒ、ＩＳＰ）、フラッシュメモリ（ｆｌａｓｈ ｍｅｍｏｒｙ）、又はマイクロコントローラ（ｍｉｃｒｏ ｃｏｎｔｒｏｌｌｅｒ）であり、本発明はここで制限されていない。 Note that the types of the first semiconductor chip 2, the second semiconductor chip 2 ′, and the third semiconductor chip 2 ″ may be adjusted and changed according to the requirements of the designer. For example, the image signal processor ( It is an image signal processor (ISP), a flash memory, or a microcontroller, and the present invention is not limited here.
上述したのは本発明の好ましい実施可能な実施例に過ぎず、本発明の保護範囲を限定するためのものではなく、本発明の特許請求の範囲に基づき為された等価の変化と変更は、全て本発明の特許請求の範囲の保護範囲に属するものとする。 The foregoing are merely preferred embodiments of the invention, and are not intended to limit the protection scope of the invention. Equivalent changes and modifications made based on the claims of the invention are: All belong to the protection scope of the claims of the present invention.
１ 基板
１１ 上面
１００ 積層型センサ実装構造
１１１ パッド
１１２ 収容溝
１１３ ワイヤボンディング領域
１２ 下面
１３ 半田ボール
２ 半導体チップ（第１の半導体チップ）
２１ 金属ボール
２２ アンダーフィル剤
２’ 第２の半導体チップ
２’’ 第３の半導体チップ
３ フレーム
３１ 環状台座
３２ 載置板
３２１ 載置平面
３２２ 貫通孔
３３ 切欠き
４ センシングチップ
４１ 天面
４１１ 検知エリア
４１２ ワイヤボンディングエリア
４１２１ 接続パッド
４１３ 載置エリア
４２ 底面
４３ 側辺部位
５ ワイヤ
６ 光透過層
６１ 第１の表面
６２ 第２の表面
６２１ 中心エリア
６２２ 支持エリア
６２３ 固定エリア
６３ 階段部
７ 支持体
７１ 第１の支持部
７２ 第２の支持部
７３ 支持層
７４ 接着層
８ 実装体
８１ 天面
８２ 液状シール剤
８２１ 天面
８３ モールドシール剤
８３１ 天面
９、９’ シーラント
Ｅ 受動電子部品
Ｃ 埋め込み式チップ
Ｄ オーバーフロー防止距離
DESCRIPTION OF SYMBOLS 1 Substrate 11 Upper surface 100 Multilayer sensor mounting structure 111 Pad 112 Accommodating groove 113 Wire bonding region 12 Lower surface 13 Solder ball 2 Semiconductor chip (first semiconductor chip)
21 Metal Ball 22 Underfill Agent 2 ′ Second Semiconductor Chip 2 ″ Third Semiconductor Chip 3 Frame 31 Annular Base 32 Mounting Plate 321 Mounting Plane 322 Through Hole 33 Notch 4 Sensing Chip 41 Top Surface 411 Detection Area 412 Wire bonding area 4121 Connection pad 413 Placement area 42 Bottom surface 43 Side part 5 Wire 6 Light transmission layer 61 First surface 62 Second surface 621 Central area 622 Support area 623 Fixed area 63 Staircase 7 Support body 71 First 1 support portion 72 second support portion 73 support layer 74 adhesive layer 8 mounting body 81 top surface 82 liquid sealant 821 top surface 83 mold sealant 831 top surface 9, 9 ′ sealant E passive electronic component C embedded chip D Overflow prevention distance
Claims (14)
前記基板に取り付けられる少なくとも一つの半導体チップと、
前記基板の前記上面に固定されるとともに複数の前記パッドの内側に位置するフレームであって、少なくとも一つの前記半導体チップが前記フレームと前記基板によって囲まれる空間内に位置し前記フレームに接触せず、少なくとも一つの前記半導体チップ上方に位置する載置平面を備えるフレームと、
サイズが少なくとも一つの前記半導体チップのサイズよりも大きく、対向する天面と底面とを備え、前記天面に複数の接続パッドが設けられており、前記底面が前記載置平面に固定されるセンシングチップと、
一端がそれぞれ複数の前記パッドに接続され、他端がそれぞれ複数の前記接続パッドに接続される複数本のワイヤと、
対向する第１の表面と第２の表面とを有し、前記第２の表面が前記センシングチップに向かっている中心エリアと環状を呈しており前記中心エリアの外側を取り囲む支持エリアとを備える光透過層と、
環状を呈しており、前記センシングチップの前記天面と前記フレームの前記載置平面との少なくとも一つに設けられ、頂縁が前記光透過層の前記支持エリアに当接される支持体と、
前記基板の前記上面に設けられるとともに前記フレームの外側縁、前記光透過層の少なくとも一部の外側縁、及び前記支持体の外側縁を被覆する実装体（ｐａｃｋａｇｅ ｃｏｍｐｏｕｎｄ）であって、各前記ワイヤの少なくとも一部が前記実装体に埋め込まれる実装体とを備え、
前記センシングチップの側辺部位に何れの前記接続パッドも設けられておらず、前記支持体は、
前記センシングチップの前記天面に設けられ、複数の前記接続パッド及び各前記ワイヤの一部を被覆する第１の支持部と、
前記載置平面に設けられるとともに前記側辺部位に近接し、何れの前記ワイヤにも接触しない第２の支持部とを備え、
前記第１の支持部の頂縁と前記第２の支持部の頂縁が全て前記光透過層の前記支持エリアに当接されることを特徴とする、積層型センサ実装構造。 A substrate having an upper surface and a lower surface facing each other, and a plurality of pads formed on the upper surface;
At least one semiconductor chip attached to the substrate;
A frame fixed to the upper surface of the substrate and positioned inside the plurality of pads, wherein at least one of the semiconductor chips is positioned in a space surrounded by the frame and the substrate and does not contact the frame. A frame comprising a mounting plane located above the at least one semiconductor chip;
Sensing in which the size is larger than the size of at least one of the semiconductor chips, the top surface and the bottom surface are opposed to each other, a plurality of connection pads are provided on the top surface, and the bottom surface is fixed to the mounting plane. Chips,
A plurality of wires each having one end connected to the plurality of pads and the other end connected to the plurality of connection pads;
Light having a first surface and a second surface facing each other, wherein the second surface has a center area facing the sensing chip and a support area surrounding the outside of the center area. A transmission layer;
Presenting an annular shape, provided on at least one of the top surface of the sensing chip and the mounting plane of the frame, a support whose top edge is in contact with the support area of the light transmission layer;
A package compound provided on the upper surface of the substrate and covering an outer edge of the frame, an outer edge of at least a part of the light transmission layer, and an outer edge of the support, each wire A mounting body embedded in at least a part of the mounting body ,
None of the connection pads are provided on the side portion of the sensing chip, and the support is
A first support that is provided on the top surface of the sensing chip and covers a plurality of the connection pads and a part of each of the wires;
A second support portion that is provided on the placement plane and is close to the side portion and does not contact any of the wires;
The first top edge of the top edge and the second support portion of the support portion is brought into contact with the supporting area of all the light-transmitting layer, characterized in Rukoto multilayer sensor mounting structure.
前記基板に取り付けられる少なくとも一つの半導体チップと、At least one semiconductor chip attached to the substrate;
前記基板の前記上面に固定されるとともに複数の前記パッドの内側に位置するフレームであって、少なくとも一つの前記半導体チップが前記フレームと前記基板によって囲まれる空間内に位置し前記フレームに接触せず、少なくとも一つの前記半導体チップ上方に位置する載置平面を備えるフレームと、A frame fixed to the upper surface of the substrate and positioned inside the plurality of pads, wherein at least one of the semiconductor chips is positioned in a space surrounded by the frame and the substrate and does not contact the frame. A frame comprising a mounting plane located above the at least one semiconductor chip;
サイズが少なくとも一つの前記半導体チップのサイズよりも大きく、対向する天面と底面とを備え、前記天面に複数の接続パッドが設けられており、前記底面が前記載置平面に固定されるセンシングチップと、Sensing in which the size is larger than the size of at least one of the semiconductor chips, the top surface and the bottom surface are opposed to each other, a plurality of connection pads are provided on the top surface, and the bottom surface is fixed to the mounting plane. Chips,
一端がそれぞれ複数の前記パッドに接続され、他端がそれぞれ複数の前記接続パッドに接続される複数本のワイヤと、A plurality of wires each having one end connected to the plurality of pads and the other end connected to the plurality of connection pads;
対向する第１の表面と第２の表面とを有し、前記第２の表面が前記センシングチップに向かっている中心エリアと環状を呈しており前記中心エリアの外側を取り囲む支持エリアとを備える光透過層と、Light having a first surface and a second surface facing each other, wherein the second surface has a center area facing the sensing chip and a support area surrounding the outside of the center area. A transmission layer;
環状を呈しており、前記センシングチップの前記天面と前記フレームの前記載置平面との少なくとも一つに設けられ、頂縁が前記光透過層の前記支持エリアに当接される支持体と、Presenting an annular shape, provided on at least one of the top surface of the sensing chip and the mounting plane of the frame, a support whose top edge is in contact with the support area of the light transmission layer;
前記基板の前記上面に設けられるとともに前記フレームの外側縁、前記光透過層の少なくとも一部の外側縁、及び前記支持体の外側縁を被覆する実装体（ｐａｃｋａｇｅ ｃｏｍｐｏｕｎｄ）であって、各前記ワイヤの少なくとも一部が前記実装体に埋め込まれる実装体とを備え、A package compound provided on the upper surface of the substrate and covering an outer edge of the frame, an outer edge of at least a part of the light transmission layer, and an outer edge of the support, each wire A mounting body embedded in at least a part of the mounting body,
前記支持体は、前記フレームの前記載置平面に設けられるとともに前記センシングチップの外側縁に位置し、各前記ワイヤの一部を被覆することを特徴とする、積層型センサ実装構造。The stacked sensor mounting structure according to claim 1, wherein the support is provided on the placement plane of the frame and is positioned on an outer edge of the sensing chip and covers a part of each wire.
前記載置平面に設けられ、前記センシングチップの外側縁に位置する支持層と、
前記支持層に設けられ、頂縁が前記光透過層の前記支持エリアに当接される接着層とを備えることを特徴とする、請求項２に記載の積層型センサ実装構造。 The support is
A support layer provided on the mounting plane and located on an outer edge of the sensing chip;
The stacked sensor mounting structure according to claim 2 , further comprising: an adhesive layer provided on the support layer and having a top edge in contact with the support area of the light transmission layer.
前記フレームの前記外側縁、前記光透過層の前記外側縁、及び前記支持体の前記外側縁を被覆し、その天面が斜面状を呈しており、前記天面のエッジが前記光透過層のエッジに接続されている液状シール剤（ｌｉｑｕｉｄ ｃｏｍｐｏｕｎｄ）と、
前記液状シール剤の前記天面に形成され、その天面が前記光透過層の前記第１の表面と平行となるとともにそれよりも低く、略５０μｍから１００μｍのオーバーフロー防止距離が離れているモールドシール剤（ｍｏｌｄｉｎｇ ｃｏｍｐｏｕｎｄ）とを備えることを特徴とする、請求項１又は２に記載の積層型センサ実装構造。 The mounting body is
The outer edge of the frame, the outer edge of the light transmission layer, and the outer edge of the support are covered, and the top surface has a sloped shape, and the edge of the top surface of the light transmission layer A liquid sealant connected to the edge;
Mold seal formed on the top surface of the liquid sealant, the top surface being parallel to the first surface of the light transmission layer and lower than that, and having an overflow prevention distance of about 50 μm to 100 μm. agent (molding Compound), characterized in that it comprises a multilayer sensor mounting structure according to claim 1 or 2.
前記基板に固定される環状台座と、
前記環状台座に接続され、その外面が前記載置平面と定義されている載置板とを備えることを特徴とする、請求項１から８のいずれか１項に記載の積層型センサ実装構造。 The frame is
An annular pedestal fixed to the substrate;
Connected to said annular seat, the multilayer sensor mounting structure according to which the outer surface, characterized in that it comprises a mounting plate, which is defined as before described置平surface, any one of claims 1 to 8.
The upper surface of the substrate leaves a wire bonding region between the frame and the receiving groove, and at least one of the semiconductor chips is wire-bonded to the wire bonding region. The stacked sensor mounting structure according to claim 13 .
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