TWI241663B - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
TWI241663B
TWI241663B TW093109169A TW93109169A TWI241663B TW I241663 B TWI241663 B TW I241663B TW 093109169 A TW093109169 A TW 093109169A TW 93109169 A TW93109169 A TW 93109169A TW I241663 B TWI241663 B TW I241663B
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TW
Taiwan
Prior art keywords
metal
integrated circuit
substrate
layer
fence
Prior art date
Application number
TW093109169A
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Chinese (zh)
Other versions
TW200504891A (en
Inventor
Alberto O Adan
Original Assignee
Sharp Kk
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Publication date
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Publication of TW200504891A publication Critical patent/TW200504891A/en
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Publication of TWI241663B publication Critical patent/TWI241663B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61G—TRANSPORT, PERSONAL CONVEYANCES, OR ACCOMMODATION SPECIALLY ADAPTED FOR PATIENTS OR DISABLED PERSONS; OPERATING TABLES OR CHAIRS; CHAIRS FOR DENTISTRY; FUNERAL DEVICES
    • A61G7/00—Beds specially adapted for nursing; Devices for lifting patients or disabled persons
    • A61G7/0005—Means for bathing bedridden persons
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61G—TRANSPORT, PERSONAL CONVEYANCES, OR ACCOMMODATION SPECIALLY ADAPTED FOR PATIENTS OR DISABLED PERSONS; OPERATING TABLES OR CHAIRS; CHAIRS FOR DENTISTRY; FUNERAL DEVICES
    • A61G7/00—Beds specially adapted for nursing; Devices for lifting patients or disabled persons
    • A61G7/02—Beds specially adapted for nursing; Devices for lifting patients or disabled persons with toilet conveniences, or specially adapted for use with toilets
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61G—TRANSPORT, PERSONAL CONVEYANCES, OR ACCOMMODATION SPECIALLY ADAPTED FOR PATIENTS OR DISABLED PERSONS; OPERATING TABLES OR CHAIRS; CHAIRS FOR DENTISTRY; FUNERAL DEVICES
    • A61G7/00—Beds specially adapted for nursing; Devices for lifting patients or disabled persons
    • A61G7/05—Parts, details or accessories of beds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Public Health (AREA)
  • Veterinary Medicine (AREA)
  • General Health & Medical Sciences (AREA)
  • Animal Behavior & Ethology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Nursing (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

A lamination of metal wire layers forms an electromagnetic isolation structure. The metal wire layers are connected with each other by vias, so that a metal fence having a laminated structure is formed. The metal fence is provided so as to surround an element (e.g. a spiral inductor) that generates an electromagnetic field in an integrated circuit. The metal wire satisfies d <= lambda/8, WF >= 5delta, and L <= lambda/20, where delta is a skin depth of an electromagnetic wave, c is a velocity of light, f is an operating frequency of the integrated circuit, d is a lateral-direction size of a metal-fence region, WF is a surrounding-line width of the metal fence, L is an interval between the vias, and lambda=c/f is a wavelength of a signal. With this arrangement, it is possible to decrease electromagnetic coupling noises and coupling noises caused via the substrate.

Description

1241663 九、發明說明： 【發明所屬之技術領域】 本發明係關於積體電路者 區域中之人 子〜疋關於必須考慮RF頻率 匕忒T之電磁性耦合之積體電路者。 【先前技術】 二=:)係將包含數位、類比、高頻等複數個訊號 μ路集成化於一個晶片中者。現 _』 區塊之相互作用’特別係通過梦基板輕合於:比 電路之數位開關雜訊會降低裝置特性。對於減低如此之數 位開關雜訊介以基板之麵合，於CM0S混载裝置設計之中使 用賴井之方法為幕所周知。但是，於同一晶 般為數微V)之感度會下降 ㈣路之情形時，會_到㈣路區塊間（介以基板之電性 麵合與基板上方之磁性耗合）之干擾。㈣合之程度係與所 使用之頻率一同增加。更且，於具有螺旋電感器般大面積 之RF被動元件中’石夕基板與被動元件間及與鄰接之裝置易 產W合。例如，若L0W Noise Amplifier(LNA，低雜訊放 大器）之輸入與以丨.5 GHZ2RF頻率動作之vc〇進行耦合， 則用於藉由VC0之較大訊號（典型為〜lv)檢測天線訊號（― 為抑制如螺旋電感器與螺旋電感器間之耦合般的RF裝置 彼此之耦合的影響，提出有下述之若干技術： (1) 加大干擾裝置間的空間之技術。 (2) 於螺旋電感器下方配置圖案化之接地遮罩層的技術 (ff〇n-Chip Spiral Inductors with Patterned Ground Shields 92300.doc 1241663 for Si-Based RF IC，sn、IEEE JOURNAL OF SOLID- STATE CIRCUITS，νο1·33, Νο·5, May 1998, pp.743-752)(稱為非專 利文獻1)。 (3) Deep Trench Guard(深渠溝保護）技術（&quot;Deep Trench Guard Technology to Suppress Coupling between Inductors in Silicon RF ICsn、2001IEEE)(稱為非專利文獻 2)。1241663 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to the person in the area of the integrated circuit ~ to the integrated circuit which must consider the electromagnetic coupling of RF frequency T. [Previous technology] Two = :) is a circuit that integrates multiple signals μ including digital, analog, and high frequency in one chip. Now the interaction of the blocks ’is particularly close to the dream substrate: the digital switch noise of the circuit will reduce the device characteristics. It is well known to reduce the noise of such digital switches through the surface of the substrate and use Lai Jing in the design of the CM0S hybrid device. However, in the case where the sensitivity of the same crystal is several micro-V) will decrease in the case of Kushiro, interference will occur between the Kushiro blocks (the electrical plane of the substrate and the magnetic dissipation above the substrate). The degree of coupling increases with the frequency used. Furthermore, among RF passive components having a large area like a spiral inductor, the 'Shi Xi substrate' and the passive components and adjacent devices are easy to produce. For example, if the input of L0W Noise Amplifier (LNA, low-noise amplifier) is coupled with vc0 which operates at a frequency of 1.5 GHz, it is used to detect the antenna signal by the larger signal of VC0 (typically ~ lv) ( ― In order to suppress the influence of coupling of RF devices such as the coupling between spiral inductors and spiral inductors, the following technologies have been proposed: (1) Technology to increase the space between interference devices. (2) To spiral Technology for placing a patterned ground shield layer under the inductor (ff〇n-Chip Spiral Inductors with Patterned Ground Shields 92300.doc 1241663 for Si-Based RF IC, sn, IEEE JOURNAL OF SOLID- STATE CIRCUITS, (No. 5, May 1998, pp.743-752) (referred to as Non-Patent Document 1). (3) Deep Trench Guard (Deep Trench Guard Technology to Suppress Coupling between Inductors in Silicon RF ICsn, 2001IEEE) (referred to as Non-Patent Document 2).

(4) 藉由於至少3面包圍訊號線之Faraday cage(法拉第籠） 的金屬佈線之遮罩技術（美國專利第6307252號說明書（公開 曰期為2001年10月23日）)(稱為專利文獻1)。 (5) 包圍金屬佈線之金屬籠遮罩技術（日本專利特開平 10-256250號公報（公開日為1998年9月25日）)（稱為專利文 獻2)。(4) Masking technology using metal wiring due to a Faraday cage surrounding at least three sides of the signal line (U.S. Patent No. 6,307,252 (publication date: October 23, 2001)) (referred to as a patent document 1). (5) A metal cage mask technology (Japanese Patent Laid-Open No. 10-256250 (published on September 25, 1998)) surrounding a metal wiring (referred to as Patent Document 2).

再者，其目的在於藉由金屬遮罩構造減少與電路區塊的 金屬連接線的電容結合，該等遮罩構造係與GND連接。該 習知例之構造（EMC EXPO 1996)本質上是與用於PCB之技 術（將電路間隔離，且使EMI減少之技術）（nFUTURE EMC TRENDS IN PC BOARD DESIGN1，，1986 年 6 月 16 日〜19 日，EMC EXPO 1996，網址 &lt;URL:http://www.blackmagic· com/ses/bruceg/EMC/futurePCB.html&gt;)(稱為非專利文獻 3) 相類似。 但是，於上述方法中存有如下問題。 干擾之裝置間的較大空間會造成晶片尺寸以及成本之增 加0 於螺旋電感器之下方配置圖案化之GND遮罩會使螺旋電 92300.doc 1241663 感器之Q係數降低。更且，該技術雖於RF頻帶範圍内有效 果（減少介以基板之耗合），但是，對於抑制電磁性耗合（基 板上部之磁性躺合）並無效果。 又，非專利文獻2之技術與通常的CMOS製程無互換性， 結果成為價格昂貴之製程。 又，專利文獻1之技術是對於金屬佈線抑制雜訊者。為 此揭示於專利文獻1或專利文獻2之技術雖可遮蔽金屬 線，但無法抑制來自於矽基板或者經由矽基板而來之拾波 雜訊與耦合雜訊。 更且，該類之任一技術皆未處理諸如與放大耦合之活性 電晶體之相互作用。例如，圖12顯示包含與螺旋電感器鄰 接之電晶體的測試圖案。當施加訊號至螺旋電感器時，較 為理想的是不產生任何耦合，於電晶體之汲極所測定之訊 號應為0。 但是，自圖13可知，輸出入間之結合度（S21)與頻率之關 係可明顯顯不有耦合之情形。由此可知，即使於電晶體為 ^FF(Id喝之情形下，仍會因經由基板側之旁通路徑之轉 合’而於高頻區域增加輸出入結合度。 的另一方面’ 1晶體為⑽之情形了，訊號會藉由螺旋電感 為與電晶體之閘極線之電磁性耦合而被傳送。 於混合訊號1C中，Deep N井技術一般用於抑制通過石夕基 板之數位雜訊搞合。如此《Deep N井技術可適用於圖⑵斤 τ之螺旋電感器與電晶體構造，輸出入間結合度u 1之值如 '所不，具有大約減少5 db左右之效果，但對於諸如好 92300.doc 1241663 LNA之要求高之應用裝置，仍然遠遠不足。 【發明内容】 本發明之目的在於提供一種與標準IC製矛呈具有互換性， 並可降低電磁性或介以基板之輕合雜訊之積體電路。 為貫現上述目的’本發明之積體電路具有以下特徵：疊 ^之金屬佈線層形成有電磁隔離構造；上述金屬佈線層係 藉由金屬佈㈣間之複數個通道互相連接，藉由上述各金 屬佈線層藉由通道而連接的方式形成疊層構造之金屬拇 攔；上述金屬柵攔係、以包圍對象元件之方式配置，且若設 電磁波之Skin depth(表層深度）為5、設e為光速、設積體電 路之動作冑率為f、$金屬栅攔區域之橫向尺寸為d、設金 屬栅攔之包圍線寬度為WF、設通道間距為L、設訊號之波 長λν/f之時，dm WF^5§，Lg/2()。 藉由上述之構ie，規疋電磁波之（表層深度） δ、金屬柵欄區域之橫向尺寸d、金屬柵欄之包圍線寬wf、 通道間距L，及訊號之波長λ間之關係。 因此，可降低電磁性或介以基板之耦合雜訊。 又，與本發明相關之積體電路，其特徵除具有上述構成 以外，係於金屬柵攔之正下方設有包括具有與基板為同一 導電型之第一擴散層的護圈，護圈係連接於固定電位，並 與金屬柵欄電性隔離。 根據上述構成，於金屬柵攔之正下方設有包括具有與基 板為同一導電型之第一擴散層的護圈，護圈係連接於固定 電位，並與金屬柵欄電性隔離。因此，除因上述構成而產 92300.doc 1241663 之耦合雜 生之放果外，可更有效地減少電磁性或介以基板 訊。 &amp; 又’與本發日月相關之積體電路，其特徵除上述構成外， 係於上述對象元件之下方含有與基板接合之井。 人X康上述構成’使井於上述對象元件之下方與基板接 小…除因上述構成而產生之效果外，可更有效地減 少電磁性或介以基板之耦合雜訊。 二，與本發明相關之積體電路，其特徵除上述構成外， '、、上述對象70件之下方含有與基板為同-導電型之低電 ::層雜上述低電阻層係連接於固定電位，且 栅欄電 性隔離。 又，與本發明相關之積體電路，其特徵除上述構成外， ^迷低電阻層之面積係與藉由金屬栅攔而包圍之面積相 等。 、 因此’除因上述構成而漆吐 ♦ 生之效果外，可更有效地減少 电磁性或介以基板之耦合雜訊。 上二：本發明相關之積體電路，其特徵除上述構成外， 電阻層係含有自動對準金屬碎化物擴散層。 根據上述構成，上述低雷 物擴散層，因此，自動對準金屬梦化 此㊉上述構成之效果外，可更有效地減少 電磁性或介以基板之耦合雜訊。 上U本發明相關之積體電路，其特徵除上述構成外， ㈣層係含有自動對準金屬魏物化之多晶石夕層。 構成，上述低電阻層係含有自動對準金屬石夕化 92300.doc 1241663 物化之多晶石夕層，因此，除因上述構成而產生之效果外， 可更有效地減少電磁性或介以基板之耦合雜訊。 又，與本發明相關之積體電路，除上述構成外，於含有 上述金屬柵欄構造之複數個元件中，其特徵在於其間係為 基板。 根據上述構成，於具有上述金屬柵櫊構造之複數個元件 中，其間係為基板。即，於該處不設置擴散層。因此，除 因上述構成而產生之效果外，可省去設置擴散層之必要， 而可更有效地減少電磁性或介以基板之耦合雜訊。 又，與本發明相關之積體電路，除上述構成外，於具有 上述金屬柵攔構造之元件中，其特徵在於其與其他無金屬 柵欄構造之元件之間係為基板。 根據上述構成，於具有上述金屬柵攔構造之元件中，其 與其他無金屬柵攔之構造的元件之間係為基板。即，該場 所不設置擴散層。因此，除因上述構成而產生之效果，可 省去設置擴散層之必要，而可更有效地減少電磁性或介以 基板之耗合雜訊。 本發明之進一步之其他目的、特徵以及優點可藉由以下 揭示充分理解。又，本發明之利益可就參照附圖之以下說 明而清楚理解。 【實施方式】 關於本發明實施之一形態，根據圖1至圖10說明如下。 本發明係關於提供一種積體電路中之電路區塊的電磁隔 離，特別是用於減少RF頻帶區域中之電磁性耦合的更有效 92300.doc -10- 1241663 之電磁隔離構造者。又，該構造係對於標準CMOS、BiCMOS 或者雙極製程之有效技術。以下所述之構成例皆為可防止 高頻區域中之電磁性耦合以及基板串擾者。於此處，電路 區塊係作為於積體電路中產生電磁場之元件（對象元件）的 高頻裝置，例如為螺旋電感器等之被動零件。 與本實施之形態相關之構成係藉由使用接地之金屬柵攔 抑制電路區塊間、與電路區塊相互連接之佈線間之電磁性 耦合者。金屬柵欄全部為導體，可藉由金屬佈線而連接於 Vdd或GND等固定（一定）電位。金屬柵攔係疊層有金屬佈線 層者，藉由穿孔而連接。又，金屬柵攔係完全或部分地包 圍電路區塊。遮罩層即例如連接於GND電位之P +、N +、 N井擴散層係抑制高頻下經由基板之耦合。更且，為抑制電 晶體之後閘極耦合，Deep N井可與金屬柵欄組合使用。 另外’下述之構成例皆可以眾所周知之一般性的8卜1(^製 程製造。故省去製造步驟之說明。即，本發明不需要任何 附加性製程或製程之變形。又，本發明之構造係在通常之 1C製程中於形成金屬佈線層或擴散層時，精心設計其圖案 並正確設置而成。 以下詳細說明電磁性隔離構造。再者’雖於以下之說明 中以4層金屬製程為例加以說明，但當然亦可適用於任意之 金屬佈線層數。 圖1及圖2分別表示於本申請案之積體電路21中，包圍螺 方疋電感之電磁性金屬栅攔20。又，圖3詳細表示本發明申 請案之一的金屬柵攔構造。於此，於金屬栅欄之正下方， 92300.doc 11 1241663 即於金屬柵櫊之丁* μ , 卢，-有勺人ώ 、攸：向來看與金屬栅攔為相同位置 處、又有包含與石夕製基板！具有 置 3ί第一擴檄Μ、 〒电生之擴政層的護圈 、、_而且’金屬栅欄係以疊層所有金屬佈線層 …丨丨之⑦式使用，與該護圈3同時作用。再者 中2表不元件隔龜- ° 離£域70件隔離區域2係使用以〇2之以製 程的一般性元件隔離。 又’金屬栅攔20於金屬佈線層疊層，藉由穿孔卜8、κ 而於垂直方向相互連接，全部或部分地包圍電路區塊。 於圖2之例中，金屬柵攔係包圍螺旋電感器12。 又’金屬栅攔11與作為電路區塊之螺旋感應器12間之縫 隙曜示於圖υ的值，應選擇不會改變金屬栅攔所包圍之 電路區塊（於圖2之情形為螺旋電感器）之電氣特性之值，這 點尤為重要。即，上述之縫隙SF必須因應實際應用而決定， 較為典型的是SF&gt;25 μιη。又，寬度WF應選擇可充分減少金 屬柵欄之低電阻化與電磁場之影響者。又，用於抑制電磁 性耦合之金屬柵攔的有效性亦依存於疊層構造中的金屬栅 欄之寬度以及穿孔之距離。 原則上’表層殊度（電磁場深入之程度）設為$。即，3係 電磁波之Skin depth(表層深度），即，產生電磁性耗合之自 積體電路表面算起的最大深度。此時， 公式 δ = {ρ/(πμ:〇}1/2 (此處，ρ為金屬柵欄之電阻率，μ為導磁率，f為動作頻 率·· 1〜5 GHz)，若電路内最快之訊號的波長為： λ= c/f， 92300.doc -12- 1241663 則只需滿足以下條件： 金屬栅攔之寬度WF- 5δ， 通道之間隔$ λ/20 即可幾乎消除電磁性耦合之影響。此處c表示光速。 再者，作為典型性值，使用A1Cu之材料，厚度為〇·6〜ΐ5 卜瓜之情形時，採用WF&gt;5pm。除A1Cu以外，亦可使用例如Furthermore, the purpose is to reduce the capacitance combination with the metal connection lines of the circuit block by the metal shield structures, which are connected to GND. The structure of this conventional example (EMC EXPO 1996) is essentially the same as the technology used for PCBs (technology that isolates circuits and reduces EMI) (nFUTURE EMC TRENDS IN PC BOARD DESIGN1, June 16, 1986 ~ On the 19th, EMC EXPO 1996, the URL &lt; URL: http://www.blackmagic.com/ses/bruceg/EMC/futurePCB.html&gt;) (referred to as Non-Patent Document 3) was similar. However, the above method has the following problems. The larger space between the interfering devices will increase the chip size and cost. Placing a patterned GND shield under the spiral inductor will reduce the Q factor of the spiral sensor. 92300.doc 1241663 In addition, although this technology is effective in the RF frequency range (reducing the consumption through the substrate), it has no effect on suppressing electromagnetic consumption (magnetic laying on the upper part of the substrate). In addition, the technology of Non-Patent Document 2 is not interchangeable with a general CMOS process, and as a result, it is an expensive process. In addition, the technique of Patent Document 1 suppresses noise for metal wiring. For this reason, although the technology disclosed in Patent Document 1 or Patent Document 2 can shield metal wires, it cannot suppress pick-up noise and coupling noise from the silicon substrate or from the silicon substrate. Moreover, none of these technologies deal with interactions such as active transistors coupled with amplification. For example, Fig. 12 shows a test pattern including a transistor adjacent to a spiral inductor. When applying a signal to a spiral inductor, it is ideal not to generate any coupling. The signal measured at the drain of the transistor should be zero. However, it can be seen from Fig. 13 that the relationship between the degree of coupling (S21) between the input and the output and the frequency can be obviously not coupled. It can be seen that, even in the case where the transistor is ^ FF (Id), the degree of input-output coupling is increased in the high-frequency region due to the switching of the bypass path through the substrate side. On the other hand, '1 crystal As a result of this situation, the signal will be transmitted by the spiral inductor for electromagnetic coupling with the gate line of the transistor. In the mixed signal 1C, the Deep N-well technology is generally used to suppress the digital noise passing through the Shixi substrate. In this way, "Deep N well technology can be applied to the spiral inductor and transistor structure of Figure ⑵ τ, the value of the combination of input and output u 1 as 'no,' has the effect of reducing about 5 db, but for 92300.doc 1241663 The demanding application device of LNA is still far from enough. [Summary of the invention] The purpose of the present invention is to provide a spear that is interchangeable with standard IC spears, and can reduce the electromagnetic properties or lighten the substrate. The integrated circuit of noise. In order to achieve the above-mentioned object, the integrated circuit of the present invention has the following characteristics: the metal wiring layer is stacked with an electromagnetic isolation structure; the above metal wiring layer is formed by a plurality of metal wiring layers. The channels are connected to each other, and a metal thumb bar of a laminated structure is formed by the above-mentioned metal wiring layers connected by the channels. The above metal grid is arranged so as to surround the target element, and if the skin depth of the electromagnetic wave is set (surface layer) Depth) is 5, let e be the speed of light, set the action rate of the integrated circuit to f, the lateral dimension of the metal barrier area to be d, the width of the enclosing line of the metal barrier to be WF, the channel spacing to be L, When the wavelength of the signal is λν / f, dm WF ^ 5§, Lg / 2 (). By the above-mentioned structure ie, regulate the electromagnetic wave (surface depth) δ, the lateral dimension d of the metal fence area, and the surrounding of the metal fence The relationship between the line width wf, the channel spacing L, and the wavelength λ of the signal. Therefore, it is possible to reduce the electromagnetic properties or the coupling noise through the substrate. In addition, the integrated circuit related to the present invention is characterized in that it has the above structure A guard ring including a first diffusion layer having the same conductivity type as the substrate is provided directly under the metal fence, and the guard ring is connected to a fixed potential and is electrically isolated from the metal fence. According to the above structure, the metal Fence A guard ring having a first diffusion layer of the same conductivity type as the substrate is provided on the side. The guard ring is connected to a fixed potential and is electrically isolated from the metal fence. Therefore, except for the coupling produced by the above structure, 92300.doc 1241663 In addition to miscellaneous fruits, it can more effectively reduce electromagnetic properties or pass through the substrate. &Amp; Also, the integrated circuit related to the sun and the moon of this issue, in addition to the above structure, is characterized by being contained below the above-mentioned target component The well connected to the substrate. The above-mentioned structure of the human X Kang 'makes the well smaller than the target component to be connected to the substrate ... In addition to the effects caused by the above structure, it can more effectively reduce electromagnetic or coupling noise through the substrate Second, the integrated circuit related to the present invention is characterized in that in addition to the above-mentioned structure, the low-electricity of the same conductive type as the substrate is included below the 70 objects mentioned above :: The above-mentioned low-resistance layer is connected to The potential is fixed and the fence is electrically isolated. In addition, the integrated circuit according to the present invention is characterized in that, in addition to the above structure, the area of the low-resistance layer is equivalent to the area surrounded by a metal barrier. Therefore, in addition to the effect of paint spitting due to the above structure, it can more effectively reduce electromagnetic or coupling noise through the substrate. Upper two: The integrated circuit according to the present invention is characterized in that in addition to the above-mentioned structure, the resistance layer includes an auto-aligned metal fragment diffusion layer. According to the above structure, the above-mentioned low-lightning diffusion layer can automatically align the metal dream. In addition to the effects of the above structure, it is possible to more effectively reduce electromagnetic noise or coupling noise through the substrate. The integrated circuit related to the present invention is characterized in that in addition to the above-mentioned structure, the plutonium layer contains a polycrystalline stone layer that is automatically aligned with the material of the metal. Structure, the above-mentioned low-resistance layer contains a polycrystalline stone material layer that is automatically aligned with metal stone material 92300.doc 1241663. Therefore, in addition to the effects produced by the above structure, it can reduce electromagnetic properties or intervene through the substrate more effectively. Coupling noise. The integrated circuit according to the present invention is characterized in that, in addition to the above-mentioned configuration, among a plurality of elements including the above-mentioned metal fence structure, a substrate is provided therebetween. According to the above configuration, among the plurality of elements having the above-mentioned metal gate structure, a substrate is provided therebetween. That is, no diffusion layer is provided there. Therefore, in addition to the effects produced by the above configuration, the necessity of providing a diffusion layer can be omitted, and the electromagnetic noise or coupling noise through the substrate can be reduced more effectively. In addition, the integrated circuit related to the present invention, in addition to the above-mentioned configuration, among the elements having the above-mentioned metal barrier structure, it is characterized in that it is a substrate with other elements having no metal-barrier structure. According to the above configuration, among the elements having the above-mentioned metal barrier structure, a substrate is provided between the element having the above-mentioned metal barrier structure and other elements having no metal barrier structure. That is, no diffusion layer is provided at this site. Therefore, in addition to the effects produced by the above-mentioned configuration, the necessity of providing a diffusion layer can be eliminated, and the electromagnetic properties or the noise due to the substrate can be more effectively reduced. Further objects, features and advantages of the present invention can be fully understood from the following disclosure. Further, the advantages of the present invention can be clearly understood from the following description with reference to the drawings. [Embodiment] An embodiment of the present invention will be described below with reference to Figs. 1 to 10. The present invention relates to an electromagnetic isolation constructor for providing circuit blocks in integrated circuits, and more particularly for reducing electromagnetic coupling in the RF frequency band region. 92300.doc -10- 1241663 In addition, this structure is an effective technology for standard CMOS, BiCMOS, or bipolar processes. The configuration examples described below are those that can prevent electromagnetic coupling and crosstalk of the substrate in the high frequency region. Here, the circuit block is a high-frequency device that is an element (target element) that generates an electromagnetic field in a integrated circuit, such as a passive part such as a spiral inductor. The configuration related to the embodiment of this embodiment is a method of suppressing electromagnetic coupling between circuit blocks and wiring between interconnected circuit blocks by using a grounded metal barrier. Metal fences are all conductors and can be connected to a fixed (constant) potential such as Vdd or GND through metal wiring. Metal barriers are stacked with metal wiring layers and are connected by vias. Furthermore, the metal barriers completely or partially surround the circuit blocks. The mask layer, for example, P +, N +, and N-well diffusion layers connected to the GND potential, suppresses coupling through the substrate at high frequencies. Furthermore, to suppress gate coupling after the transistor, Deep N wells can be used in combination with metal fences. In addition, the following constitutional examples can be manufactured by the well-known general process (manufacturing process). Therefore, the description of the manufacturing steps is omitted. That is, the present invention does not require any additional processes or deformations of the processes. Furthermore, the present invention The structure is carefully designed and correctly arranged when forming a metal wiring layer or a diffusion layer in a normal 1C process. The electromagnetic isolation structure is described in detail below. Furthermore, although a 4-layer metal process is used in the following description As an example for illustration, of course, it can also be applied to any number of metal wiring layers. Figs. 1 and 2 respectively show an electromagnetic metal barrier 20 surrounding the spiral inductor in the integrated circuit 21 of the present application. Fig. 3 shows the metal barrier structure in detail in one of the applications of the present invention. Here, right below the metal fence, 92300.doc 11 1241663 is the metal gate ditch * μ, Lu,-spoonful Yau: Looking at the same position as the metal fence, there is also a base plate made of Ishiba! It has a retainer with a 3rd first expansion 〒M, an electric expansion layer, and a metal fence Laminate all metal cloth The layer is used in the same way as the guard ring 3. In addition, the middle 2 means that the element is separated from the turtle-° off the zone 70 pieces of isolation area 2 is isolated by general components with a process of 0 to 2. The metal barrier 20 is stacked on the metal wiring layer, and is connected to each other in the vertical direction through the perforations 8 and κ, which completely or partially surround the circuit block. In the example of FIG. 2, the metal barrier surrounds the spiral inductor. 12. The value of the gap between the metal barrier 11 and the spiral inductor 12 as the circuit block is shown in Figure υ, and the circuit block surrounded by the metal barrier should be selected (in the case of Figure 2 it is The value of the electrical characteristics of the spiral inductor) is particularly important. That is, the above-mentioned gap SF must be determined according to the actual application, and the more typical is SF &gt; 25 μιη. In addition, the width WF should be selected to reduce the metal fence sufficiently. Resistors and the influence of electromagnetic fields. In addition, the effectiveness of metal barriers used to suppress electromagnetic coupling also depends on the width of the metal fence in the laminated structure and the distance of the perforation. In principle, the surface layer (the depth of the electromagnetic field Degree Set it to $. That is, the skin depth of the 3 series electromagnetic waves (surface depth), that is, the maximum depth from the surface of the integrated circuit that generates electromagnetic depletion. At this time, the formula δ = {ρ / (πμ: 〇} 1/2 (here, ρ is the resistivity of the metal fence, μ is the magnetic permeability, and f is the operating frequency ... 1 to 5 GHz). If the wavelength of the fastest signal in the circuit is: λ = c / f, 92300 .doc -12- 1241663 only need to meet the following conditions: the width of the metal barrier WF-5δ, the channel spacing $ λ / 20 can almost eliminate the influence of electromagnetic coupling. Here c represents the speed of light. Moreover, as a typical For the performance value, when using A1Cu material with a thickness of 0.6 to ΐ5, use WF> 5pm. In addition to A1Cu, for example,

AlSi、A卜 Au、Cu等。 本申請案之金屬隔離柵攔之效果如圖4所示。適用於與圖 、相同之測5式構造（即，具有藉由金屬柵攔包圍之螺旋電 感器之構造)。其結果，與無金屬隔離柵欄之先前圖案相比 較’可達到減少約20 dB之輸出入間結合度。s參數係以電 磁波之傳播為基礎者，其中⑵在本例中表示隔離 (isolation)。S21越低則隔離越好，基板串擾之影響越小。 金屬栅攔整體之高度，可設為與產生電磁場之元件同声 以上之金屬佈線層。又，層數可根據設計而決定，又，一 層之厚度、通道之高度、通道之直徑等可根據製程而決定。 、於上述之圖1之構成中’疊層之金屬佈線層之金屬栅攔可 適當變更。又，用於減少與鄰接電路區塊之電磁性搞合的 栅欄效果，依存於疊層之金屬佈線層之數量。 基於電路區塊為高頻裝置，且其特性會因與基板之寄生 電容而劣化等理由，若被包圍之電路區塊、即產生電磁場 之元件使用最上層之全屬故&amp; &amp; y 曰^屬佈線層而形成之情形時，作為 屬柵攔，與其設置包含撼私a 也 匕3擴散層之護圈3及底層金屬佈線 (最下層之金屬佈線層），不 曰J不如没置最上層之金屬佈線層來得 92300.doc 1241663 有效。即，作為用於金屬栅欄之金屬佈線層，必須為與產 生電磁場之元件同層以上之金屬佈線層。圖5表示不使用包 含擴散層之護圈3或底層金屬佈線層之金屬隔離拇搁的= 〇 圖6,係概括說明於上述般之於最上層之金屬佈線層設有 兩個螺旋電感器之情形時，兩個螺旋電感器間之輸入輸出 間結合度S21(dB)之試驗結果者。此處，兩個螺旋電感器間 隔1〇 gm，其中之-的螺旋電感器係藉由以不同之金屬佈線 層（第-金屬佈線層〜第四金屬佈線層）製成之金屬 包圍。 再者’自表面至遠處依次為第—金屬佈線層、第二金屬 料層、第三金屬佈線層，以及第四金屬佈線層。距基板 最近之金屬佈線層為第一金屬佈線層，「〇」與「◎」兩者皆 表示形成有金屬佈線層，空攔處則表示未形成有金屬佈線 層。自第四金屬佈線層側起設為〇，自第一金屬佈線層側 起設為「◎」。 為進-步改善電磁隔離之效果，特別是於高頻之情形 中士圖7所示若於藉由金屬柵欄包圍之電路區塊之下 方，與N井3 0(第二擴散層）組合，則更具效果。 N井3 0之面積與藉由金屬栅攔2()包圍之面積（即電路區塊 之面積）同等（例如，相等）。 再者，圖7係於電路區塊之下方設置料、基板為_之 情形’但亦可與此相反，於電路區塊下方設置p井，而將基 板設為Nsub。 92300.doc •14- 1241663 更且，作為基本構造之其他變形例，電磁隔離亦可與低 電阻層40組合。該情形時，低電阻層4〇與基板區域之導電 3L相同如圖8所示連接於固定電位。固定電位係或 GND，藉由金屬佈線連接。再者，該低電阻層仞係藉由高 導電性之自動對準金屬矽化物擴散層或已予自動對準金屬 :化物化之多晶石夕層而形成。又，該構造亦可如螺旋電感 益般，使用於基板内未搭載有被包圍之電路區塊的情形。 又，若將應加以保護（所包圍之）之電路區域之尺寸（一邊 之長度）設為d，將該電路區域之面積設為，則 d=Area1/2。 又，電磁隔離柵襴之關係依存於動作頻率（即，波長入= )再者，上述d式於應保護之（被包圍之）電路區域例如為 正方形時成立，而除此以外當應保護之（被包圍之）電路區域 例如為圓形之情形時亦可為同—計算式，不 正方形或為圓形，d之值都差不乡 ^ ^域為圓形之情形 ”至屬柵攔亦形成為圓形，其尺寸4表示直徑。 如右又/8，則電磁放射無法從金屬拇搁 不需要有如習知例（專利文獻取底部或頂部之金屬罩則 又，對於使育氧化膜作為介電層之1C，於 c〜1.5x1(^cm/秒、f=5GHz、^3cm 、 之時’電路區域之尺寸為 或頂部之金屬遮罩層，僅“：、路區塊無需無底部 電磁性搞合。θ 1精“磁柵欄而包圍，即可抑制 更且’於電路區塊之間的高頻區域之輕合，主要將基板 92300.doc -15- 1241663 作為通路。為了減少基板㉝合，上述之金屬隔離栅搁可與 建入矽區域之電路構成要素（比如螺旋電感器、電容器）組 合。其區域中如圖9所示，即使僅配置^^井51以及卩井“作為 經過一般中等摻雜的井（tabs)，仍可獲得充分之抑制效果: 即，如圖9所示，電路區塊25間雖未予以摻雜，但藉由將基 板1設為Psub，使基板電阻增大，則摻雜之程度即使僅為通 系之中等左右，亦可充分抑制基板雜訊。 其結果，電路區塊25間之矽區域成為具有高電阻率之基 板，耦合基板之阻抗增大，從而減少高頻區域之電路間之 事禺合。 如此，於具有金屬柵攔之複數個元件（電路區塊25)中， 其間係可構成如基板1。又，如圖10所示，於具有金屬柵攔 構造之元件中，與其他不具有金屬柵攔構造之元件之間可 構成如基板1。 專利文獻2之;樁顯示於橫向（金屬配線層之疊層中）包 圍電路或元件之金屬佈線層，且至少於電路或元件之頂部 或下方藉由金屬佈線層而具有2次元之表面。更且，專利文 獻2中’金屬之疊層係連接至基板之擴散層。 另一方面，本發明之金屬堆疊構造不必連接至基板之擴 散層。藉此，可以使設計單純化。又，本發明之金屬柵攔 係以橫向尺寸（1為〇14/8之方式包圍電路或元件，故而不必 使用頂部金屬遮罩層。 如上所述’本發明係有效地抑制RF電路區塊間之磁性、 電谷性以及基板耦合者。因而，金屬之電磁隔離技術不需 92300.doc -16- 1241663 任何特殊製程。其結果具有與標準性之㈣程之互換性。 已確 &lt; 為有效之電磁隔離。即，臨界性之電路區塊 P使間隔小，仍可達到電磁隔離。其結果可進一步縮小 晶片尺寸。 再者，於發明之詳細說明内容中之具體性實施態樣或實 施例僅係清楚解釋本發明之技術性内容者，並非僅限定於 該具體例而狹義解釋之，可於本發明之精神及其後所揭示 之申請專利範圍内，進行各種變更而實施之。 【圖式簡單說明】 、圖1係表示與本發明相關之積體電路的金屬柵攔之一構 成例的平面圖。 圖2係表示圖1的構成之包含A-A，箭頭朝向部分的剖面之 立體圖。 圖3係表示圖1的構成之立體圖。 圖4係表不輸出入間結合度S2丨與頻率之關係圖表。 圖5係表示與本發明相關之積體電路之金屬柵攔的其他 構成例之立體圖。 圖6係表示輸出入間結合度S21之圖。 圖7係表示與本發明相關之積體電路之金屬柵攔的次一 其他構成例之立體圖。 圖8係表示與本發明相關之積體電路之金屬柵攔的另一 其他構成例之立體圖。 圖9係表示與本發明相關之積體電路之金屬柵攔的又一 其他構成例之立體圖。 92300.doc -17- !241663 圖1 〇係表示與本發明相關之積體電路之金屬柵攔的再一 其他構成例之立體圖。 圖Π係表示於同一晶月内混載有類比/數位裝置之情形 的互相干擾之圖。 圖12係表示測試圖案之平面圖。 圖13係表示輸出入間結合度821之頻率依存之圖表。 圖14係表示設有DeepN井時S21的效果之圖表。 【主要元件符號說明】 1 基板 2 元件分離區域 3 護圈（第一擴散層） 5、7、9、11 金屬佈線層 穿孔 12 20 21 25 30 40 51 52 螺旋電感器（對象元件） 金屬柵欄 積體電路 電路區塊 N井（第二擴散層） 低電阻層 N井 P井 92300.doc -18·AlSi, Abu, Au, Cu, etc. The effect of the metal isolation barrier in this application is shown in FIG. 4. Applicable to the same type 5 structure as that shown in the figure (that is, a structure with a spiral inductor surrounded by a metal fence). As a result, compared with the previous pattern of the metal-free barrier fence, a reduction of the input-to-input coupling ratio of about 20 dB can be achieved. The s-parameter is based on the propagation of electromagnetic waves, where ⑵ in this case means isolation. The lower the S21, the better the isolation, and the smaller the influence of substrate crosstalk. The height of the metal barrier as a whole can be set to a metal wiring layer that is at least the same level as the component that generates the electromagnetic field. The number of layers can be determined according to the design, and the thickness of one layer, the height of the channel, and the diameter of the channel can be determined according to the manufacturing process. In the above-mentioned constitution of FIG. 1, the metal gate of the laminated metal wiring layer can be appropriately changed. In addition, the effect of the fence for reducing the electromagnetic coupling between adjacent circuit blocks depends on the number of metal wiring layers stacked. Because the circuit block is a high-frequency device, and its characteristics will be deteriorated due to the parasitic capacitance with the substrate, etc., if the enclosed circuit block, that is, the component that generates the electromagnetic field, uses the top layer, it ’s the whole reason &amp; &amp; y ^ When it is formed by a wiring layer, as a barrier, instead of setting the retaining ring 3 and the bottom metal wiring (lowest metal wiring layer) including a diffusion layer 3 and a diffusion layer, it is better not to set J The upper metal wiring layer is 92300.doc 1241663 effective. That is, as the metal wiring layer used for the metal fence, it is necessary to be a metal wiring layer of the same layer or more as the element generating the electromagnetic field. Figure 5 shows the use of a metal isolation barrier without a guard ring 3 or a bottom metal wiring layer including a diffusion layer. Figure 6 is a summary of the two spiral inductors provided on the uppermost metal wiring layer as described above. In this case, the test result of the combination degree S21 (dB) between the input and output of the two spiral inductors. Here, the two spiral inductors are separated by 10 gm. Among them, the spiral inductor is surrounded by metal made of different metal wiring layers (first metal wiring layer to fourth metal wiring layer). Furthermore, the first metal wiring layer, the second metal material layer, the third metal wiring layer, and the fourth metal wiring layer are in this order from the surface to the distant place. The metal wiring layer closest to the substrate is the first metal wiring layer. Both "0" and "◎" indicate that the metal wiring layer is formed, and the blank area indicates that the metal wiring layer is not formed. It is set to 0 from the fourth metal wiring layer side, and "第一" from the first metal wiring layer side. In order to further improve the effect of electromagnetic isolation, especially in the case of high frequencies, as shown in FIG. 7, if it is combined with the N well 30 (second diffusion layer) below the circuit block surrounded by a metal fence, More effective. The area of the N well 30 is the same as the area surrounded by the metal fence 2 () (ie, the area of the circuit block) (for example, equal). Furthermore, Fig. 7 shows a case where a material is provided below the circuit block and the substrate is _ ', but the opposite can also be done by setting a p-well below the circuit block and setting the substrate to Nsub. 92300.doc • 14-1241663 Furthermore, as another modification of the basic structure, electromagnetic isolation may be combined with the low-resistance layer 40. In this case, the low-resistance layer 40 is connected to a fixed potential as shown in FIG. 8 as the conductive 3L in the substrate region. Fixed potential or GND, connected by metal wiring. Furthermore, the low-resistance layer is formed by a highly-conductive self-aligned metal silicide diffusion layer or a metal: chemically-crystallized polysilicon layer. In addition, this structure can also be used in the case where the enclosed circuit block is not mounted on the substrate like a spiral inductor. If the size (length of one side) of the circuit area to be protected (enclosed) is set to d and the area of the circuit area is set to, d = Area1 / 2. In addition, the relationship between the electromagnetic isolation barrier 襕 depends on the operating frequency (ie, wavelength in =). Furthermore, the above formula d holds when the circuit area to be protected (enclosed) is, for example, a square, and other than that, it should be protected. The (enclosed) circuit area can also be the same when it is circular, for example—the calculation formula is not square or circular, and the value of d is not as good as ^ ^ the case where the field is circular. It is formed into a circle, and its size is 4 diameter. If the right is / 8, electromagnetic radiation cannot be removed from the metal thumb. It does not need to be a conventional example (patent literature takes the metal cover at the bottom or the top. 1C of the dielectric layer, at c ~ 1.5x1 (^ cm / s, f = 5GHz, ^ 3cm, when the size of the circuit area is or the top metal mask layer, only the ":" and the road blocks do not need to have no bottom Electromagnetic compatibility. Θ 1 fine "magnetic fence and surrounded, you can suppress the light and high frequency region between circuit blocks, mainly using the substrate 92300.doc -15-1241663 as a pathway. In order to reduce the substrate Coupled, the above metal isolation barrier can be integrated with the circuit structure built into the silicon area The combination of elements (such as spiral inductors and capacitors). As shown in Fig. 9 in this area, even if only ^^ well 51 and manholes are configured as "wells with moderately doped (tabs), sufficient suppression effects can still be obtained. : That is, as shown in FIG. 9, although the circuit blocks 25 are not doped, the substrate resistance is increased by setting the substrate 1 to Psub, so that the degree of doping is only in the middle of the system. It is also possible to sufficiently suppress substrate noise. As a result, the silicon region between the circuit blocks 25 becomes a substrate with a high resistivity, and the impedance of the coupling substrate is increased, thereby reducing the interference between the circuits in the high-frequency region. Among the plurality of elements having a metal barrier (circuit block 25), a substrate 1 can be configured therebetween. Also, as shown in FIG. 10, among the elements having a metal barrier structure, other elements without a metal barrier structure can be formed. The components can be constituted as substrate 1. Patent Document 2; the stub is displayed in the lateral direction (in the stack of metal wiring layers) surrounding the metal wiring layer of the circuit or component, and at least on or under the top of the circuit or component by metal Wiring layer There is a two-dimensional surface. Furthermore, the 'metal stack in Patent Document 2 is connected to the diffusion layer of the substrate. On the other hand, the metal stack structure of the present invention does not need to be connected to the diffusion layer of the substrate. This allows the design to be made Simplified. In addition, the metal barrier of the present invention surrounds a circuit or component in a lateral dimension (1 is 014/8), so there is no need to use a top metal mask layer. As described above, the present invention effectively suppresses RF circuits The magnetic, electrical valley, and substrate coupling between blocks. Therefore, the electromagnetic isolation technology of metal does not require any special process of 92300.doc -16-1241663. The result is interchangeable with the standard process. It has been confirmed &lt; For effective electromagnetic isolation. That is, the critical circuit block P makes the interval small and still achieve electromagnetic isolation. As a result, the wafer size can be further reduced. Furthermore, the specific implementation forms or examples in the detailed description of the invention are only those that clearly explain the technical content of the present invention, and are not limited to the specific examples but explained in a narrow sense. They can be interpreted in the spirit and scope of the present invention. Within the scope of the patent application disclosed later, various changes were implemented. [Brief description of the drawings] Fig. 1 is a plan view showing an example of a structure of a metal barrier of an integrated circuit related to the present invention. Fig. 2 is a perspective view showing a cross-section of the structure of Fig. 1 including A-A and a portion facing an arrow. FIG. 3 is a perspective view showing the structure of FIG. 1. FIG. 4 is a graph showing the relationship between the degree of integration S2 丨 and the frequency between input and output. Fig. 5 is a perspective view showing another configuration example of a metal barrier of an integrated circuit according to the present invention. FIG. 6 is a diagram showing the degree of integration S21 between the output and the input. Fig. 7 is a perspective view showing another example of the constitution of the metal barrier of the integrated circuit according to the present invention. Fig. 8 is a perspective view showing another configuration example of the metal barrier of the integrated circuit according to the present invention. Fig. 9 is a perspective view showing still another configuration example of the metal barrier of the integrated circuit according to the present invention. 92300.doc -17-! 241663 Fig. 10 is a perspective view showing still another example of the configuration of the metal barrier of the integrated circuit related to the present invention. Figure Π is a diagram showing mutual interference in a case where analog / digital devices are mixed in the same crystal moon. Fig. 12 is a plan view showing a test pattern. FIG. 13 is a graph showing the frequency dependence of the input-output coupling degree 821. FIG. 14 is a graph showing the effect of S21 when a DeepN well is provided. [Description of main component symbols] 1 Substrate 2 Element separation area 3 Guard ring (first diffusion layer) 5, 7, 9, 11 Metal wiring layer perforation 12 20 21 25 30 40 51 52 Spiral inductor (target component) Metal fence product Body circuit circuit block N well (second diffusion layer) Low resistance layer N well P well 92300.doc -18 ·

Claims (1)

1241663 十、申請專利範圍： h 一種積體電路，其包含·· 對象元件’以及以包圍上述對象元件之方式而配置之 金屬柵攔； 上述金屬栅攔包含： $層而形成有電磁隔離構造之金屬佈線層，以及 互相連接上述金屬佈線層彼此之複數個穿孔； 當設電磁波之Skin depth(表層深度）為δ、設c為光速、 没積體電路之動作頻率為f、設金屬柵櫊區域之橫向尺寸 為d、設金屬栅攔之包圍線寬為WF、設穿孔間隔為：、設 訊號竦長λ= c/f時，則 dm WF- 5δ ; Lg λ/20。 2·如請求.項1之積體電路，其中於上述金屬栅攔之正下方， 包含與基板具有相同導電型之第一擴散層所構成之護 圈；上述護圈係連接於固定電位，且上述護圈係與上述 金屬柵欄電性隔離。 3. 如請求項丨之積體電路，其中於上述對象元件之下方，具 有與基板接合之井。 4. 如請求項1之積體電路，其中於上述對象元件之下方，具 有與基板相同導電型之低電阻層，上述低電阻層係連接 於固定電位，且與上述金屬栅攔電性隔離。 5·如請求項4之積體電路，其中上述低雷阳爲^ ^ k低冤阻層之面積係與藉 92300.doc 1241663 由上述金屬桃搁而包圍之面積相等。 6.如請求項5之積體電路，其中上述低電阻層係包括自動對 準金屬矽化物擴散層。 7·如晴求項5之積體電路，其中上述低電阻層係包括經自動 對準金屬石夕化物化之多晶石夕層。 8. 如請求項工之積體電路，其中具有上述金屬拇棚構造之複 數個元件之間係為基板。 9. 如請求項1之積體電路，其中具有上述金屬柵欄構造之元 件與其他不具有金屬柵攔構造之元件之間係為基板。 10·如請求項丨之積體電路，其中上述對象元件係於上述積體 電路内產生電磁場之元件。 11·如請求項10之積體電路，其中上述對象元件係為高頻裝 置。 12_如請求項丨丨之積體電路，其中上述對象元件係為螺旋電 感器。 13·如請求項1之積體電路，其中上述金屬栅欄係接地。 14.如請求項丨之積體電路，其中上述金屬柵欄與上述對象元 件之間之縫隙SF係SF&gt;25 μιη。 15·如請求項丨之積體電路，其中上述金屬柵攔為AiCu，上述 金屬栅攔之厚度為0.6〜1·5 μπι，上述WF為WF&gt;5 μιη。 16·如請求項丨之積體電路，其中上述金屬柵攔之整體高度係 與上述對象元件為同層以上。 17.如請求項丨之積體電路，其中上述對象元件之頂部及底部 係露出而不為上述金屬柵攔所覆蓋。 92300.doc1241663 X. Scope of patent application: h An integrated circuit including: an object component 'and a metal fence configured to surround the object component; the metal fence includes: Metal wiring layer, and a plurality of perforations connecting the metal wiring layers to each other; when the Skin depth (surface depth) of the electromagnetic wave is δ, the speed of light is c, the operating frequency of the integrated circuit is f, and the area of the metal grid is set When the horizontal dimension is d, the surrounding line width of the metal fence is WF, the perforation interval is set, and when the signal length λ = c / f, then dm WF-5δ; Lg λ / 20. 2. If requested, the integrated circuit of item 1, which includes a guard ring composed of a first diffusion layer having the same conductivity type as the substrate directly below the metal barrier; the guard ring is connected to a fixed potential, and The retainer is electrically isolated from the metal fence. 3. The integrated circuit of claim 丨, which has a well connected to the substrate below the above-mentioned target component. 4. The integrated circuit of claim 1, wherein a low-resistance layer of the same conductivity type as the substrate is provided below the above-mentioned target element, and the low-resistance layer is connected to a fixed potential and is electrically isolated from the metal gate. 5. The integrated circuit as claimed in claim 4, wherein the area of the above-mentioned low thunder-yang layer is ^ ^ k and the area of the low-resistance layer is equal to the area surrounded by the metal peaches by 92300.doc 1241663. 6. The integrated circuit of claim 5, wherein the low-resistance layer includes an automatic alignment metal silicide diffusion layer. 7. The integrated circuit as described in item 5 above, wherein the above-mentioned low-resistance layer comprises a polycrystalline silicon layer that has been chemically aligned with the metal stone. 8. If the integrated circuit of the project is requested, among the plurality of components having the above-mentioned metal thumb structure is a substrate. 9. As in the integrated circuit of claim 1, the substrate having the above-mentioned metal fence structure and other components not having the metal fence structure are substrates. 10. The integrated circuit as claimed in claim 1, wherein said target component is a component that generates an electromagnetic field in said integrated circuit. 11. The integrated circuit according to claim 10, wherein the above-mentioned target element is a high-frequency device. 12_ The integrated circuit as claimed in the above item, wherein the above-mentioned target element is a spiral inductor. 13. The integrated circuit of claim 1, wherein the metal fence is grounded. 14. The integrated circuit as claimed in claim 1, wherein the gap SF between the metal fence and the target element is SF &gt; 25 μm. 15. The integrated circuit as claimed in claim 1, wherein the metal barrier is AiCu, the thickness of the metal barrier is 0.6 to 1.5 μm, and the WF is WF> 5 μm. 16. The integrated circuit as claimed in claim 1, wherein the overall height of the metal barrier is the same layer or more as the above-mentioned target element. 17. The integrated circuit as claimed in claim 1, wherein the top and bottom of the target component are exposed and not covered by the metal barrier. 92300.doc
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