JPH10256250A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform effective shielding by forming the (n+1)<-> th wiring layer which covers a specified functional block in the (n+1)<-> th layer above this specified functional block. SOLUTION: An N-type diffused region 2-6 for stopper connected with an n-well 203 is made into a circular form in advance, and a circuit to be shielded is built in beforehand, including a P-well 202 within. First, contacts 221a for connection between the first-layer metallic wiring and a diffused region are arranged densely in a circular form likewise on the N-type diffused layer 206 formed into a circular shape. Thereon, wring is arranged in circular form likewise along the contact arranged, by a first wiring 321a. This processing is performed in a circular form to a contact 223a for connection between a third- layer metallic wiring 233a and a second-layer metallic wiring 232a. Lastly, the third-layer metallic wiring 233a is made in the shape for filling up this functional block over the entire surface, whereupon the contacts can be piled up in the shape of an upside-down cup from the same subplate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-scale integrated circuit device using multi-layer wiring, and more particularly, to an analog and digital circuit block for handling high frequencies as a noise source, and a wiring group for connecting specific functional blocks and distributing signals. In contrast, the present invention relates to an integrated circuit device that can shield an external circuit with a multilayer metal wiring.

[0002]

2. Description of the Related Art In an integrated circuit device employing multi-layered metal wiring, as shown in FIG. 4, the effect of the coupling capacitance between wirings between wirings is taken into account the effect of the width of wiring. Was only. Until the era of two-layer wiring, especially in the process of automatic wiring processing geometrically,
The problem was solved by making it as straight as possible, and in terms of circuit, a chip in which completely different types of circuits exist in one chip was not developed. For example,
An analog high-speed circuit, a high-speed arithmetic circuit, a DRAM, and the like were not mixed in a normal-speed circuit.

Therefore, even in the era of three-layer wiring, it is not necessary to separate or isolate a particular functional block in a chip or a wiring group interconnecting the particular functional block. .

[0004]

However, in recent years, in a large-scale integrated circuit device on a system-on-silicon scale, which actively employs multilayer metal wiring, a circuit scale which has conventionally been developed as a separate chip LSI has been developed. By taking a plurality of devices in the form of a circuit function block called a megacell in a chip and arranging and wiring them mutually, a great leap and improvement in LSI performance and cost has been made.

In order to improve the degree of integration, a deep sub-micron process is being adopted. As for the coupling capacitance between the wirings, the ratio between the wiring width and the wiring thickness is getting closer, and the conventional vertical capacitance is required. It has become necessary to consider not only the coupling capacitance between the wirings in the directions but also the influence of the side surface and the coupling capacitance.

From the above, a) For the wiring processing of three or more layers, the effect of the mutual coupling capacitance between the wirings can be sufficiently reduced only by the method of making the wiring layers orthogonal as in the conventional two-layer wiring. Can not.

B) When a high-speed analog circuit or a digital circuit block which becomes a noise generating source is incorporated in the same chip, a general circuit which normally operates normally has a large influence including a malfunction. Comes out.

C) In the deep sub-micron process, since the degree of integration in the chip is extremely high, no extra area can be occupied merely by shielding the circuit.

D) It is necessary to shield the coupling capacitance between the wirings due to the wiring side surfaces.

With respect to the problem described above, it is inevitable to rely on the progress of the circuit simulation technology in consideration of the coupling capacitance between wirings.

The present invention solves such a problem, and an object of the present invention is to isolate a specific functional block and a wiring group connecting the specific functional blocks from the wiring of other LSIs. Another object of the present invention is to provide a system-on-silicon scale semiconductor integrated circuit device which can be mixed in an LSI chip.

[0012]

According to the present invention, there is provided a semiconductor integrated circuit device comprising: a) an n-layer wiring layer in an LSI chip;
In the case where a specific functional block is configured, b) a diffusion layer for a stopper, which is formed in the same substrate Pwell or Nwell, is provided in an annular shape around the specific functional block region, and c). A first contact connecting the first wiring layer and the diffusion layer is annularly arranged on the diffusion layer formed so as to surround the functional block so as to surround the function block, b. A) the first contacts arranged in an annular shape are connected to each other in an annular shape by a first wiring layer; c) the first contacts arranged in the annular shape similarly to the diffusion layer.
A second contact connecting the second wiring layer and the first wiring layer is annularly arranged on the first wiring layer so as to surround the functional block. Similarly, the n-th wiring layer and the n-th contact connecting the (n + 1) -th wiring layer to the n-th wiring layer are arranged in a ring shape. It is characterized in that it is formed by forming an (n + 1) th wiring layer covering the specific functional block in the layer.

Further, the semiconductor integrated circuit device of the present invention has the following features: a) In the case where a wiring group for connecting specific function blocks is formed in an LSI chip by wiring layers from the nth layer to the mth layer, b) Below the wiring group connecting the specific functional blocks, a plate-like region formed by the (n-1) -th wiring layer, which covers most of the wiring group in a plane, is formed. C) a first contact for connecting the n-th wiring layer and the (n-1) th wiring layer is annularly arranged on the plate-like region so as to surround the plate-like region; d) further connecting the n-th contact arranged in an annular shape with each other in an annular manner by an n-th wiring layer; e) on the n-th wiring layer arranged in the annular shape ,
A second contact connecting the (n + 1) th wiring layer and the nth wiring layer is arranged in a ring shape. D) Similarly, the (n + m−1) th wiring layer and the n +
The m-th contact connecting the m-th wiring layer and the (n + m-1) -th wiring layer is arranged in a ring shape. e) The n + m-th layer above the wiring group connecting the specific function blocks And an (n + m) th wiring layer covering this, and f) the contact and the wiring are grounded to the same potential.

Further, in the semiconductor integrated circuit device according to the present invention, in the semiconductor integrated circuit device, the first to n-th contacts are stacked at the same place in a plane (s).
(tack via).

Further, the semiconductor integrated circuit device according to the present invention is characterized in that, in the semiconductor integrated circuit device, a power supply line is supplied from a contact and a wiring layer at the same potential to another functional block in the LSI.

The semiconductor integrated circuit device according to the present invention is characterized in that, in the semiconductor integrated circuit device, wirings and contacts are mounted on a grid in a plane.

[0017]

According to the present invention, a plurality of interlayer contacts and a ring-shaped wiring are arranged in a wall shape in cross section and in a ring shape in plan view. The specific circuit block having n layers is covered with a plate-like lid by the (n + 1) th wiring layer. n
For a specific wiring group consisting of m layers from the first layer, n-1
A plate-like lid is formed on the upper and lower sides by the wiring layer of the layer and the (n + m) th layer. The above-mentioned wirings and contacts all have the same substrate potential. Therefore, compared to the conventional shielding by a flat wiring layer, it takes up less space in a plane. It is also possible to shield the coupling capacitance on the wiring side surface, which is characteristic of the deep submicron process.

According to the above configuration of the present invention, a contact (Via) for a multilayer wiring is vertically connected to a specific functional block and a wiring group connecting the specific functional blocks. An extremely effective shielding can be performed by being stacked in an annular shape from the substrate, and by forming an upper wiring layer on the functional block so as to cover the functional block.

Further, regarding the stacking of the contacts, by actively utilizing the multi-stacking of the contacts,
The mesh formed by the wirings and contacts in FIG. 6 can be made thinner, and the shielding effect can be improved.

In addition, compared with the shielding by a mere flat wiring layer, it does not take up space in a plane or in a three-dimensional manner.

[0021] It is possible to sufficiently shield the coupling capacitance on the side surface of the wiring, which is characteristic of the deep submicron process in which the ratio between the width and the thickness of the wiring is closer.

By performing this shielding, the coupling capacitance generated in the vertical and horizontal directions shown in the sectional view of FIG.
As shown in (1), there is only the coupling capacitance between the wirings inside the functional block.

Further, also for a wiring group connecting specific functional blocks, the coupling capacitance with wiring other than the wiring group can be completely reduced.

From the above, it is possible to greatly improve the influence on a circuit around a specific functional block or a wiring group which is a source of noise inside the LSI.

[0025]

FIG. 1 is a schematic plan view of an entire chip of a large-scale LSI including a high-frequency circuit block.
For the chip 01, the input / output cells 105 are arranged in a ring around the chip, and the basic cells 102 are arranged in a matrix inside the input / output cells. RAM, ROM and MPU as megacells with a certain set of functions
Are arranged, and a high-frequency circuit block area 107, which is also a noise generation source, is arranged.

On the other hand, around the chip, there are arranged input / output function cells having a logical function. The input / output cells and the internal function block area, the basic cell matrix area, and the high-frequency circuit block area are denoted by reference numeral 104. To secure a dedicated wiring area.

By connecting these basic cell / matrix regions and various functional block regions to each other by a multilayer wiring technique, a system-on-silicon LSI is realized.

In FIG. 2, FIG. 3, FIG. 6, and FIG. 7, reference numeral 201 denotes an N-type substrate region, on which a P-well 202 is provided.
And 203 are formed as N-wells.

Reference numeral 204 in the P-well 202 denotes an N-type diffusion region, which forms an N-channel MOS transistor together with a polysilicon region 208 passing through the center.

Reference numeral 205 in the N-well 203 denotes a P-type diffusion region which forms a P-channel MOS transistor together with a polysilicon region 208 passing through the center.

Reference numeral 206 denotes an N-type diffusion region for a stopper of a P-channel transistor, and reference numeral 207 denotes a P-type diffusion region for a stopper of an N-channel transistor.
And a part of the P-type substrate region 202.

Reference numeral 209 denotes a field oxide film.

Reference numerals 221a and 221b denote contacts for connection between the first-layer metal wiring and the diffusion region, 222a and 222b denote contacts for connection between the second-layer metal wiring and the first-layer metal wiring,
223a and 223b are connection contacts between the third-layer metal wiring and the second-layer metal wiring, and 224 and 224a are connection contacts between the fourth-layer metal wiring and the third-layer metal wiring.
31, 231a and 231b are first layer metal wirings, 232,
232a and 232b are the second layer metal wiring, 23
Reference numerals 3 and 233a denote third-layer metal wires, and 234 and 234a denote fourth-layer metal wires.

In these sectional views, reference numeral 240 indicates an interlayer insulating film between the first-layer metal wiring and the diffusion region or the polysilicon region, and reference numeral 241 indicates an interlayer insulating film between the second-layer metal wiring and the first-layer metal wiring. Reference numeral 242 denotes an interlayer insulating film between the third-layer metal wiring and the second-layer metal wiring, 243 denotes an interlayer insulating film between the fourth-layer metal wiring and the third-layer metal wiring, and 244 denotes a chip surface and the fourth-layer metal wiring. Is an interlayer insulating film.

FIG. 2 is a sectional view of a chip showing the state of a conventional multilayer metal wiring.

FIG. 4 is a cross-sectional view showing the type of coupling capacitance between wirings in a conventional multilayer metal wiring, and is also a model of FIG.

FIG. 3 is a chip sectional view of the shielded high-frequency circuit block according to the embodiment of the present invention as viewed from the vertical direction in FIG.

FIG. 5 is a cross-sectional view showing the type of coupling capacitance between wirings when the shield processing according to the present invention is performed, and is also a model of FIG.

Comparing the types of coupling capacitance between the wirings, as shown in FIGS. 3 and 5, when a specific circuit block is shielded, only the mutual coupling capacitance is considered as the coupling capacitance. It is no longer necessary to consider the coupling capacitance caused by the adjacent second-layer metal wiring and its side surface, and the coupling capacitance with the third-layer metal wiring, which existed in FIG.

FIG. 6 is a cross-sectional view of the shielded high-frequency circuit block according to the embodiment of the present invention as viewed from the horizontal direction in FIG. 7, and the contacts between the respective layers are shown in a so-called stack VIA state, that is, FIG. FIG. 7 shows a vertically stacked multistage stacking of the contacts for connection between the first layer metal wiring of 221a and the diffusion region of 221a.

This stack VIA is often prohibited by design rules. However, in order to eliminate the coupling capacitance between the wiring side surfaces, contacts can be arranged densely and the functional blocks are shielded. Seems to be more effective.

FIG. 7 is a plan view of a shielded high-frequency circuit block according to an embodiment of the present invention.

Here, an N-type diffusion region for a stopper 206 connected to the N-well 203 is formed in a ring shape, and a P-well 202 is included in the inside to form a circuit to be shielded. Is built in. First, the first of 221a is placed on the N-type diffusion region formed in an annular shape.
Similarly, contacts for connection between the layer metal wiring and the diffusion region are densely arranged in an annular shape. Similarly, the first layer metal wiring 231a is similarly annularly wired along the arranged contacts.

In this process, the contact 223a is annularly arranged up to the contact for connection between the third-layer metal wiring and the second-layer metal wiring.

At the end, a third metal wiring layer 233a is formed so as to completely fill this functional block.

By the above-described processing, a very effective shielding can be performed by stacking the contacts from the same substrate in such a manner that the bowl is turned down.

FIG. 8 is a cross-sectional view of a wiring group for connecting between specific shielded functional blocks according to the embodiment of the present invention.

In this figure, three third-layer metal wirings 233b are formed around 223a in the same manner as in FIG.
The connection contacts between the third-layer metal wiring and the second-layer metal wiring, and the connection contacts between the fourth-layer metal wiring and the third-layer metal wiring 224a are similarly arranged in a ring shape and stacked to be shielded. ing.

As compared with the case of FIG. 3, the lowermost layer is the N-type diffusion region diffusion layer of 204, but is replaced by the second-layer metal wiring of 232a.

According to the above-described embodiment, in the system large-scale LSI chip adopting the deep sub-micron process, by adopting the shield of the present method, the coupling capacitance from the high-frequency function block by analog and digital circuits can be obtained. In addition, it is possible to prevent the malfunction of the circuit due to crosstalk, and it is very economical in terms of location. It can be technically realized.

[0051]

As described above, according to the present invention, a contact (Via) for a multilayer wiring is vertically provided from the same substrate to a high-frequency circuit function block serving as a noise source. By stacking them in such a manner that they are lying down, extremely effective shielding can be achieved.

In addition, compared with the shielding by a mere flat wiring layer, a space is not required in two dimensions or three dimensions.

It is possible to sufficiently shield the coupling capacitance on the side surface of the wiring, which is characteristic of the deep submicron process in which the ratio between the width and the thickness of the wiring is closer.

Further, a sufficient shielding effect can be similarly obtained with respect to a wiring group connecting specific functional blocks, so that a high-frequency signal or a high-frequency clock is bundled to have almost no influence on signals on other wirings. Instead, it can be distributed all over the chip.

Also, when automatically performing the layout and wiring processing in the LSI chip, specific function blocks and a wiring group connecting the specific function blocks can be shielded in advance, so that other functions can be performed. It is not necessary to pay attention to the arrangement and wiring of the blocks and their interconnections.

From the above, L on the system-on-silicon scale employing the deep submicron process is used.
In the development of SI chips, the effect of noise from high-frequency noise sources due to analog and digital circuits through coupling capacitors is drastically reduced, and circuit malfunctions due to crosstalk can be prevented. There is an effect that the circuit can be increased in scale and speed as a whole.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of an entire chip of a large-scale LSI including a high-frequency circuit block.

FIG. 2 is a cross-sectional view of a chip showing a state of a conventional multilayer metal wiring.

FIG. 3 is a chip cross-sectional view of the shielded high-frequency circuit block according to the embodiment of the present invention as viewed from the vertical direction in FIG. 7;

FIG. 4 is a cross-sectional view showing types of coupling capacitance between wirings in a conventional multilayer metal wiring.

FIG. 5 is a cross-sectional view illustrating types of coupling capacitance between wirings when a shielding process according to the present invention is performed.

FIG. 6 is a cross-sectional view of the shielded high-frequency circuit block according to the embodiment of the present invention as viewed in the horizontal direction in FIG. 7;

FIG. 7 is a plan view of a shielded high-frequency circuit block according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view of a wiring group for connecting between specific shielded functional blocks according to the embodiment of the present invention.

[Explanation of symbols]

101. . . Chip outline 102. . . Unit basic cell 103. . . Basic cell matrix 104. . . Area dedicated to wiring 105. . . Input / output cell 106. . . Function block 107. . . High frequency circuit function block 201. . . N-type substrate region 202. . . P-well 203. . . N-well 204. . . N-type diffusion region 205. . . P-type diffusion region 206. . . N-type diffusion region for stopper 207. . . P-type diffusion region for stopper 208. . . Polysilicon region 209. . . Field oxide films 221a, 221b. . Contact 222a, 222b. For connection between the first layer metal wiring and the diffusion region. . Contact 223a, 223b. For connection between the second-layer metal wiring and the first-layer metal wiring. . Contact 224, 224a. For connection between the third-layer metal wiring and the second-layer metal wiring. . . Contacts 231, 231 a, 231 b. For connection between the fourth-layer metal wiring and the third-layer metal wiring. . First layer metal wiring 232, 232a, 232b. . Second layer metal wiring 233, 233a, 233b. . Third layer metal wiring 234, 234a. . . . . . . Fourth layer metal wiring 240. . . 241. Interlayer insulating film between first layer metal wiring and diffusion region or polysilicon region . . 242. Interlayer insulating film between second-layer metal wiring and first-layer metal wiring . . 243. Interlayer insulating film between third-layer metal wiring and second-layer metal wiring . . 244. Interlayer insulating film between fourth-layer metal wiring and third-layer metal wiring . . 250. Interlayer insulating film between chip surface and fourth layer metal wiring . . Substrate

Claims (5)

[Claims] 1. a) When a specific function block is constituted by n wiring layers in an LSI chip, b) On the outer periphery of the specific function block region, the same substrate Pwell or A diffusion layer for a stopper formed in Nwell is provided in a ring shape. C) On a diffusion layer formed so as to surround the function block, a first layer is formed so as to surround the function block. A first contact connecting the wiring layer and the diffusion layer is arranged in an annular shape; and b) the first contacts arranged in an annular shape are connected to each other in an annular shape by a first wiring layer. C) similar to the diffusion layer, the first annularly arranged first
A second contact connecting the second wiring layer and the first wiring layer is annularly arranged on the first wiring layer so as to surround the functional block. Similarly, the n-th wiring layer and the n-th contact connecting the (n + 1) -th wiring layer to the n-th wiring layer are arranged in a ring shape. A semiconductor integrated circuit device, wherein an (n + 1) th wiring layer covering the specific function block is formed in a layer, and is configured. 2. a) When a wiring group connecting specific functional blocks is formed by an nth to mth wiring layers in an LSI chip, b) the specific functional block A plate-like region formed by the (n-1) th wiring layer, which covers most of the wiring group in a plane, is provided below the wiring group connecting between the wiring groups; A first contact connecting the n-th wiring layer and the (n-1) -th wiring layer is annularly arranged on the region so as to surround the region. D) Further, the first contact is annularly arranged. The n-th contact thus formed is connected to each other in an annular manner by an n-th wiring layer. E) On the n-th wiring layer arranged in the annular shape,
A second contact connecting the (n + 1) th wiring layer and the nth wiring layer is arranged in a ring shape. D) Similarly, the (n + m−1) th wiring layer and the n +
The m-th contact connecting the m-th wiring layer and the (n + m-1) -th wiring layer is arranged in a ring shape. e) The n + m-th layer above the wiring group connecting the specific function blocks And an (n + m) th wiring layer covering the contact layer, and f) the contact and the wiring are grounded to the same potential. 3. The semiconductor integrated circuit device according to claim 1, wherein the first to n-th contacts are stacked in the same place in a plane (stack v).
A semiconductor integrated circuit device having the structure of ia). 4. The semiconductor integrated circuit device according to claim 1, wherein a power supply line is supplied from a contact and a wiring layer at the same potential to another functional block in the LSI. Circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein the wiring and the contact are on a grid in a plane.