JP2003133421A - Semiconductor integrated circuit device and method of its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a highly reliable wiring structure that stabilizes a ground potential level and is hard to get influenced by noise, and a method of manufacturing this device. SOLUTION: An integrated circuit manufactured by applying a metal multilayer wiring technique is shown. For example, a desired well zone and element are formed on a p-type semiconductor substrate 10, and metal wiring layers M1 to M4 having aluminum, for example, as a main component are formed to constitute the integrated circuit 11. The top layer is provided with a wiring layer M5 based on a metal member (Cu, for example) having diamagnetism properties, and it is connected with the high-concentration zone 12 of the substrate through a via hole VIA. The reference potential on the integrated circuit, e.g. the ground potential VSS is given to the wiring layer M5. A part of the wiring layer M4 constituting a ground pad 13 guided out as an external connection part and the wiring layer M5 are connected through the via hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal wiring structure in a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device which requires a high speed operation with a low voltage power supply and a design method thereof.

[0002] [Detailed Description of the Invention]

2. Description of the Related Art Semiconductor integrated circuit devices such as LSI chips are required to operate at higher speed due to lower power supply voltage, smaller size and thinner thickness. There are not a few products that are built in various electronic devices, especially small portable electronic devices, and have a digital IC and an analog IC mounted together.

These semiconductor integrated circuit devices include a metal multilayer wiring structure. Secure the lines of power supply voltage VDD and VSS (ground potential) to some extent with the metal on the lower layer side,
Most of the upper-layer metal is CAD (Computer for placement and wiring)
It is often used as a resource. The metal on the lower layer side is generally formed thinner in the subsequent stacking process.

Regarding the power supply voltage (VDD), there is a method of allocating the metal wiring on the upper layer side in particular, but little consideration is given to securing the ground potential (VSS). In many cases, metal as a VSS line formed near the outermost periphery is connected to the substrate via a via.

[0005]

High speed IC with low power supply voltage
When designing, the fluctuation of the power supply voltage is fatal. CMOS that can set the input voltage judgment level to VDD × 1/2
Even if it is a technique, the determination level will be closer to the ground side when the device dimensions of the P-channel MOSFET and the N-channel MOSFET are the same. Therefore, noise caused by the floating of the ground potential VSS (internal bounce) also contributes to malfunction and reduction of noise margin.

[0006] Further, noise caused by natural phenomena, noise from other electronic devices, adjacent IC chips, noise generated by itself, and the like, which are unfavorably affected, electromagnetic interference (that is, electromagnetic interference), so-called EMI. (Electr
Countermeasures against omagnetic interference should also be considered.

The present invention has been made in consideration of the above circumstances, and has a semiconductor integrated circuit having a highly reliable wiring structure which stabilizes the ground potential level of the semiconductor integrated circuit itself and is hardly affected by external noise. A circuit device and a method for manufacturing the same are provided.

[0008]

A semiconductor integrated circuit device according to the present invention relates to an integrated circuit to which a metal multi-layer wiring technique is applied, in which an uppermost wiring layer is composed of at least a metal member having a diamagnetic property, and A reference potential of the integrated circuit is applied to the metal member.

According to the above-described semiconductor integrated circuit device of the present invention, the metal member adapted to be applied with the reference potential of the integrated circuit is provided in the uppermost layer. Since the installation area can be increased and a stable reference potential can be obtained, it is a measure against noise. Moreover, it can be a countermeasure against EMI by being composed of a metal member having diamagnetism.

The metal member has a mesh pattern. According to this pattern, it is expected that noise of a specific frequency can be effectively suppressed by devising the mesh size.

Alternatively, the metal member has a striped pattern. According to this pattern, the effect is lower than that of the high-density mesh, but it has the effect of suppressing noise as described above.

Further, the above-mentioned metal member is characterized in that it is fixed with a form in which a base metal material is covered. Depending on the base on which the metal member is formed, a base metal material that improves the barrier property and the adhesiveness may be required.

Further, the metal member is electrically connected to a predetermined pad as an external connection portion, and a reference potential is applied to the substrate of the integrated circuit. The electrical connection to the predetermined pad may be a configuration performed at an appropriate portion in the multilayer wiring or a direct connection configuration to the predetermined pad.

The metal member as described above is characterized by containing Cu. Cu has been established as a buried wiring material and has a diamagnetic property. This makes a great contribution to the electromagnetic shield effect.

If the integrated circuit is divided into blocks, the metal members as described above are individually divided into regions according to the blocks, and the reference potential is applied depending on the integrated circuit block. It is characterized by further comprising a configuration in which a region in a state other than the above is also provided. Noise countermeasures can be strengthened for each integrated circuit block.

The integrated circuit as described above may be a hybrid IC in which an analog integrated circuit and a digital integrated circuit are mounted together. The pattern of the metal member is individually provided according to each integrated circuit block, and the pattern of the metal member further includes an electrically floating region on the analog integrated circuit. . There is a part that emphasizes the effect of the clock noise shield and the effect of the electromagnetic shield, and the noise countermeasure can be strengthened for each block of the integrated circuit.

In the method for manufacturing a semiconductor integrated circuit device according to the present invention, an element is formed on a semiconductor substrate, an integrated circuit is constituted by a multilayer wiring via an interlayer insulating film, and each required pad for external connection is derived. Accordingly, a wiring connection portion for applying a reference potential to the semiconductor substrate is formed up to the uppermost layer separately from the pad, and is formed on the interlayer insulating film above a predetermined region of the integrated circuit. It is characterized in that a pattern of a metal member having a diamagnetic property is formed including on the wiring connection portion.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the diamagnetic metal member connected to the wiring connecting portion to which the reference potential is applied to the substrate is provided only in the uppermost layer of the multilayer wiring. Will be available. A large area can be obtained and a stable reference potential can be obtained, which is a measure against noise. Moreover, by partially applying the diamagnetic metal member, the EMI countermeasure can be inexpensively performed.

The pattern of the metal member is characterized by including a step of dividing the pattern of the metal member into individual blocks according to the blocks of the integrated circuit and simultaneously forming a region in a state other than a state where a reference potential is applied. At the uppermost layer of the multilayer wiring, noise countermeasures can be strengthened for each integrated circuit block.

The metal member is characterized in that it is patterned by fixing by a sputtering method and utilizing a photolithography technique. Alternatively, the metal member is characterized in that it is coated with a base metal material and then fixed on it. Depending on the base on which the metal member is formed, a base metal material that improves the barrier property and the adhesiveness may be required. Since it is close to the final step, the manufacturing method can be selected appropriately.

Further, the method is characterized by further comprising a step of forming a protective film on the uppermost layer including the metal member. That is, a protective film that opens the pad portion is formed. A configuration in which the metal member is provided between the protective films is conceivable.

The metal member as described above is characterized by containing Cu. Cu has been established as a buried wiring material and has a diamagnetic property. This makes a great contribution to the electromagnetic shield effect.

[0023]

FIG. 1 is a sectional view showing the structure of a main part of a semiconductor integrated circuit device according to a first embodiment of the present invention. An integrated circuit to which metal multi-layer wiring technology is applied is shown. For example, desired well regions and elements are formed on the P-type semiconductor substrate 10, metal wiring layers M1 to M4 containing aluminum as a main component are formed, and the integrated circuit 11 is configured.

In this embodiment, the wiring layer M5 made of a metal member (for example, Cu) having a diamagnetic property is provided in the uppermost layer, and the high concentration region 12 and the via V of the substrate are provided.
It is connected via IA. The vias connected to the M5 wiring layer are not provided in one but in a plurality of predetermined places.

The wiring layer M5 is a reference potential in the integrated circuit,
For example, the ground potential VSS is applied. Here, a part of the wiring layer M4 that constitutes the ground pad 13 that is derived as an external connection portion and the wiring layer M5 are connected via a via. In addition, in designing the integrated circuit, the ground pad 13
M for internal wiring that needs to be electrically connected to
It goes without saying that any one of the wiring layers 1 to M4 is used.

According to the semiconductor integrated circuit device of the first embodiment, the wiring layer M5 adapted to be supplied with the reference potential (ground potential VSS) of the integrated circuit to be formed can be used as the uppermost layer to have a large area. . As a result, a stable reference potential can be obtained, which is a measure against noise. Moreover,
EMI by being composed of a diamagnetic metal member
It can also be a countermeasure.

FIG. 2 is a top view showing the structure of FIG. 1 as an IC chip. The wiring layer M5 has, for example, a mesh pattern containing Cu as a main component, and is configured to cover the integrated circuit inside the IC chip. As described above, it is connected to the ground pad 13 using the internal wiring layer. Although not otherwise specified, other power supply pads and signal pads are also arranged.

3 and 4 are modifications of the configuration of FIG. 2, respectively. In addition, various finer patterns are possible. By devising the stripe pitch and mesh size, it can be expected that noise at a specific frequency can be effectively suppressed. Further, there are various possible ways of forming the ground pad 13 or a ground line using an internal wiring layer, and it may be connected to the uppermost layer M5.

FIGS. 5A to 5C are cross-sectional views showing an example of a method of manufacturing a main part according to the configuration of FIG. 1 in the order of steps. An integrated circuit is configured up to the wiring layer M4 by applying the metal multilayer wiring technology. For example, the pad for each external connection including the wiring layer M4 is formed by patterning. After that, the upper surface including the pad is covered with the insulating film 16 as the first protective film (FIG. 5A).

Next, using photolithography, a portion of a predetermined M4 wiring layer that is to be connected to the substrate region and should be led out including the stacked via (VIA) is opened (opening HL). After that, the base material 14 and the Cu material 15 are sputtered on the insulating film 15 and the openings HL (FIG. 5).
(B)).

Next, by using photolithography technology, C
After the u material 15 (including the base material 14) is formed in a predetermined pattern (see FIGS. 2 to 4), the insulating films 17 and 18 are coated as second and third protective films. Thereby, the insulating films 16-18
Is a passivation film PF. After that, each pad portion is opened in the passivation film PF by using a photolithography technique (FIG. 5C).

It is assumed that the insulating film 16 is a silicon oxide film, the base material 14 is a barrier metal having good adhesion to the silicon oxide film, the insulating film 17 is a silicon nitride film, and the insulating film 18 is a silicon oxide film. That is, the passivation film PF here is a silicon oxide film / silicon nitride film /
It is a laminated structure of silicon oxide films. This is an example,
Other possibilities are possible.

According to the method of the above embodiment, the diamagnetic Cu material 15 connected to the wiring connection portion to which the reference potential is applied to the substrate 10 is provided in the uppermost layer (M5) of the multilayer wiring. Become. A large area can be obtained and a stable reference potential can be obtained, which is a measure against noise. Moreover, by partially applying the Cu material having diamagnetism, the EMI countermeasure can be inexpensively performed.

FIG. 6 is a plan view showing a main surface of a chip region, which is a main part configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention. This is an example of a configuration in which an analog integrated circuit 21 and a digital integrated circuit 22 are mounted together by applying a metal multilayer wiring technology.

On the area of the digital integrated circuit 22,
Similar to the first embodiment, the uppermost wiring layer is provided with the uppermost metal Mtop-22 made of a metal member (for example, Cu) having a diamagnetic property, and is provided with a high concentration region of the substrate and a via. It is connected. The pattern is, for example, a stripe pattern as shown in FIG. 3, and each pattern is designed to be electrically connected to a predetermined region of the substrate by using an internal wiring layer.
It is connected to the.

On the area of the analog integrated circuit 21, a metal member (for example, Cu) also having a diamagnetic property is provided as the uppermost metal Mtop-21, but it is in an electrically floating state. The pattern is, for example, a mesh pattern as shown in FIG. Also,
A guard band GB having a ground potential (connected to the ground pad 23) is provided on the substrate so as to surround the area of the analog integrated circuit 21. As described above, by including the floating mesh pattern, the region can be appropriately configured as a region in which the shield effect of clock noise and the effect of electromagnetic shield are emphasized.

According to the configuration of the above embodiment, when the integrated circuit is divided into blocks, the metal member having the diamagnetic property, which is individually divided into regions according to the blocks, can be patterned in the uppermost layer. Depending on the integrated circuit block, it is possible to realize a configuration in which a region in a state other than the state where the reference potential is applied is also provided. As a result, noise countermeasures can be strengthened for each integrated circuit block.

FIGS. 7A to 7C are plan views showing a method of manufacturing a main part having the structure of FIG. 6 in the order of steps.
As shown in FIG. 7A, an n-layer (n is a predetermined natural number) metal multilayer wiring technique is applied to form an integrated circuit wafer. It is possible to achieve a structure in which the analog integrated circuit 21, the digital integrated circuit 22, and the pads PAD for each external connection are formed by patterning including the multilayer wiring (n-1) layers. It also includes installation of a guard band GB of ground potential so as to surround the area of the analog integrated circuit 21.

Further, at a predetermined location in the area of the digital integrated circuit 22, an (n-1) layer electrically connected to a predetermined area of the substrate by using an internal multilayer wiring layer and connected to the ground pad 23. Electrodes 24 are provided.

Next, as shown in FIG. 7B, the pad P
The upper surface including the AD is covered with the insulating film 26 as the first protective film. The portion of the electrode 24 to be derived is opened by using the photolithography technique. Then, the insulating film 26
A base material (not shown) and C on the upper and exposed electrodes 24.
The u material 35 is formed by sputtering.

Next, as shown in FIG. 7C, after the Cu material 35 (including the base material) is formed into a predetermined pattern (see FIG. 6) by using the photolithography technique, the second and third protective films are formed. As a result, the insulating films 27 and 28 are covered. Insulating film 26-2
8 is a passivation film PF. Then, each pad PAD portion is opened in the passivation film PF by using a photolithography technique. Figure 6 after dicing
An IC chip shown in is obtained.

It is assumed that the insulating film 26 is a silicon oxide film, the base material is a barrier metal having good adhesion to the silicon oxide film, the insulating film 27 is a silicon nitride film, and the insulating film 28 is a silicon oxide film. That is, the passivation film PF here has a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film. This is an example, and others are possible.

According to the method of the above-mentioned embodiment, the Cu material having the diamagnetic property can be widely taken by the uppermost layer (n layer) of the multi-layered wiring, and the noise countermeasure can be applied to each integrated circuit block individually.
An EMI countermeasure configuration can be realized. That is, it is used as a noise countermeasure to obtain a stable reference potential to the board,
Further, it can be provided in an electrically floating region in a region where EMI countermeasures are important. In addition, although not shown, by providing a metal member having diamagnetism by using the uppermost layer of the multi-layer wiring, it is possible to realize a configuration for appropriately enhancing the potential according to the integrated circuit block. In addition, it is possible to realize a noise countermeasure and an EMI countermeasure configuration. Furthermore, by providing as many vias (VIA) as possible to electrically connect the Cu material of the uppermost layer and the integrated circuit board, the heat of the integrated circuit can be generated not only from the back surface of the substrate but also from the metal uppermost layer (Cu material). It has a structure that allows it to escape, which contributes to stable operation and faster operation.

[0044]

As described above, according to the semiconductor integrated circuit device of the present invention, the metal member which is provided with the reference potential of the integrated circuit to be formed is provided in the uppermost layer. Since the installation area can be increased and a stable reference potential can be obtained, it is a measure against noise. Moreover, it can be a countermeasure against EMI by being composed of a metal member having diamagnetism. Further, a region or the like which is in a state other than the reference potential can be individually configured. Further, since the heat of the integrated circuit can be made to escape from the metal uppermost layer (Cu material), the secondary effect that contributes to the stabilization of the operation and the speeding up of the operation can be obtained. As a result, it is possible to provide a semiconductor integrated circuit device having a highly reliable wiring structure that stabilizes the ground potential level and is not easily affected by noise, and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a top view showing the configuration of FIG. 1 as an IC chip.

FIG. 3 is a first modification example of the configuration of FIG.

FIG. 4 is a second modification example of the configuration of FIG.

5A to 5C are cross-sectional views showing, in the order of steps, a method of manufacturing a main part according to the configuration of FIG.

FIG. 6 is a plan view showing a main surface of a chip region, which is a main-part configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention.

7A to 7C are plan views showing a method of manufacturing a main part according to the configuration of FIG. 6 in the order of steps.

[Explanation of symbols]

10 ... Semiconductor substrate 11 ... Integrated circuit 12 ... High concentration area 13, 23 ... Ground pad 14 ... Base material 15, 35 ... Cu material 16, 17, 18, 26, 27, 28 ... Insulating film 21 ... Analog integrated circuit 22 ... Digital integrated circuit 24 ... Electrode M1 to M5 ... Wiring layer Mtop-21,22 ... Top metal GB ... Guard band

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F033 HH08 HH11 JJ01 JJ08 JJ11                       KK01 KK08 MM05 MM13 MM22                       NN06 NN07 PP15 QQ09 QQ10                       QQ37 RR04 RR06 TT02 VV03                       VV05 XX14                 5F038 BE09 BH10 BH19 CD02 CD18                       DF12 EZ08 EZ20

Claims (14)

[Claims] 1. An integrated circuit to which a metal multi-layer wiring technique is applied, wherein an uppermost wiring layer is made of a metal member having at least a diamagnetic property, and a reference potential of the integrated circuit is applied to the metal member. A characteristic semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the metal member has a mesh pattern. 3. The semiconductor integrated circuit device according to claim 1, wherein the metal member has a stripe pattern. 4. The metal member is fixed with a form of covering a base metal material.
3. The semiconductor integrated circuit device according to any one of 3 to 3. 5. The metal member is electrically connected to a predetermined pad as an external connection portion to apply a reference potential to the substrate of the integrated circuit. Semiconductor integrated circuit device. 6. The semiconductor integrated circuit device according to claim 1, wherein the metal member contains Cu. 7. The metal member is individually divided into regions according to the blocks of the integrated circuit, and further comprises a region in a state other than the state where the reference potential is applied. 7. The semiconductor integrated circuit device according to any one of 6 to 6. 8. The integrated circuit is a hybrid IC in which an analog integrated circuit and a digital integrated circuit are mixedly mounted, and the patterns of the metal members are individually provided according to blocks of the respective integrated circuits. 7. The semiconductor integrated circuit device according to claim 1, further comprising an electrically floating region on the analog integrated circuit in the pattern. 9. When an element is formed on a semiconductor substrate and an integrated circuit is constituted by multi-layer wiring via an interlayer insulating film and each pad for external connection required is derived,
A wiring connection portion for applying a reference potential to the semiconductor substrate is formed up to the uppermost layer separately from the pad, and the wiring connection portion is formed on the interlayer insulating film above a predetermined region of the integrated circuit. A method of manufacturing a semiconductor integrated circuit device, comprising forming a pattern of a metal member having a diamagnetic property. 10. The pattern of the metal member is divided according to the blocks of the integrated circuit, and a step of simultaneously forming a region in a state other than the application of the reference potential is also provided. Item 10. A method for manufacturing a semiconductor integrated circuit device according to item 9. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the metal member is patterned by fixing using a sputtering method and utilizing a photolithography technique. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the metal member is coated with a base metal material and then fixed on the base metal material. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 9, further comprising the step of forming a protective film on the uppermost layer including the metal member. 14. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the metal member contains Cu.