TWI237379B - Chip package structure and circuit substrate thereof - Google Patents

Abstract

A chip package structure mainly includes a substrate, a patterned solder mask layer and a chip. The substrate has a plurality of first contacts on a first surface of the substrate, and the first surface includes a chip bonding area surrounded by these first contacts. In addition, the patterned solder mask layer covers onto the first surface of the substrate and exposes these first contacts and the chip bonding area. The chip is disposed on the chip bonding area and electrically connected to these first contacts. Moreover, the substrate has a power plane and/or a ground plane over a portion of the surface of the patterned solder mask layer and electrically connected to at least one of these first contacts.

Description

1237379 V. Description of the invention (1)-Species: 2: It relates to a chip packaging structure, and in particular to a packaging structure and its circuit substrate. Phases: "The rapid development of the" sub-technology "of the high-tech electronics industry is innovating and ::; humanization: better-functioning electronic products continue to be packaged with conductors. Design. At present, in the semi-constructed element i:!, Mf ;, ubstrate) are often used to remove the two types of substrates: "laminated and laminated" and "g UP". Among them, the circuit The substrate is mainly composed of two or two patterned circuit layers and multiple patterned dielectric layers. As the circuit substrate has the advantages of fine wiring, compact assembly and good performance, it makes the circuit substrate Has become a chip size package (Ch ip

The mainstream of Scale Package (CSP) and flip chip package.

Generally, a patterned circuit layer of a circuit substrate is defined by, for example, copper foil iayer through lithographic etching, and a dielectric layer is disposed between two adjacent patterned circuit layers for Isolate two adjacent patterned circuit layers. The overlapping patterned circuit layers are electrically connected to each other through a Planting Through Hole (PTH) or a conductive via. The material of the patterned dielectric layer is, for example, glass epoxy resin (FR-4, FR-5), bismaleimide-triazine (BTT), or ring

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e: y resin) and so on. Here's the picture of the outermost layer of the circuit substrate: "The road layer and the dielectric layer are further provided with a solder mask liii, and the glow mask layer only exposes a large number of contacts, as a circuit The substrate is connected to other electronic components such as wafers and passive components. Figure 1 shows a schematic cross-section of a conventional circuit board. Please refer to Figure 1 for a four-layer circuit board as an example. The conventional circuit board iq () mainly Number of Lunar New Years: Road layer: 10 M20, 13., 140 and most of the patterned dielectric layers 22, 24, 126 are stacked on top of each other, and each of the patterned dielectric layers 122, 124, 126 is between two Adjacent circuit layers are between u0, 12o, i3o, and 14o. Generally, in the circuit design, the innermost circuit layer, 2o, and 1o are used as the power plane of the circuit board (power plane). ) Or ground plane, as the power input terminal or ground terminal required for signal transmission. In addition, the outermost circuit layers 11 and 14 can be etched by lithography to become the signal conductor of the circuit board 100. When the signal is transmitted between the outermost patterned circuit layers 110, 140, The electron flow can pass through the patterned dielectric layers 122, 124, 126 and one of the power planes and ground planes on the upper and lower sides of the conductive via 132 'to achieve signal transmission, and the signal can be transmitted to the power plane during transmission. Or the ground plane is used as a plane where the reference voltage is located to avoid signal distortion. In the conventional technology, 'although the circuit substrate 00 has four circuit layers 110, 120, 130, 140, only the outermost two circuit layers 11 〇, can be used as signal transmission (layout) space, the innermost two of the circuit layer 1 2 0, 1 3 0 most of the area as a power plane and a ground plane 1237379

V. Description of the invention (3) The layout space. That is, when the number of layers of the circuit board of the circuit board is four, six, or more than eight, but the number of layers actually transmitted as a signal is relatively less than or equal to two, four, or six The remaining number of layers provides the plane on which the reference voltage for signal transmission is located, so the number of layers of the circuit substrate cannot be effectively reduced, and the cost of the circuit substrate 100 can not be reduced. In addition, the conventional signal transmission must pass through the plane where the reference voltage is located, which also easily leads to the instability of the signal transmission. ^ SUMMARY OF THE INVENTION Therefore, the object of the present invention is to provide a circuit substrate, the number of layers of the circuit substrate can be reduced to reduce the production of the substrate. A circuit substrate. The circuit layer on the inner layer of the board can be used as a layout area for signal transmission. Another object of the present invention is a plane above the outermost circuit layer of the board. It is to provide a circuit substrate, in which the base surface of the circuit can be used as the reference voltage of the signal conductor. The above-mentioned objective A 1 of the present invention mainly includes a plurality of patterned lines. The present invention proposes a patterned solder mask layer of a circuit substrate and an electrical complaint. That is, at least-patterned dielectric layer, and few-conductive vias, which are electrically between two, and the patterned dielectric layer has an outer, and the patterned solder mask layer covers between the patterned circuit layers of the Jit portion. And the power / ground contact configuration, the outermost part of the patterned circuit layer is on the surface of the patterned solder mask layer, j 1237379 V. Description of the invention (4) At least one of the patterned circuit layers is electrically connected By. According to a preferred embodiment of the present invention, the aforementioned power / ground contact includes, for example, at least one power plane and at least one ground plane, and the power plane and the ground plane may be located on the same surface of the patterned solder mask layer or On different surfaces. In addition, the power plane and the ground plane are, for example, a copper layer formed by electroplating or sputtering, and the surface of the copper layer may be covered with an anti-oxidation layer. To achieve the above object of the present invention, the present invention further provides a circuit substrate, which mainly includes a first patterned circuit layer with a plurality of first signal contacts, and a second patterned circuit layer with a plurality of second signals. contact. In addition, the circuit substrate also has a patterned dielectric layer disposed between the first and second patterned circuit layers, and the patterned dielectric layer has at least one conductive via, which is electrically connected to the first and the first. Between two signal contacts; and a patterned solder mask layer covering the first and second patterned circuit layers respectively, exposing the first and second signal contacts, and a power / ground contact It is disposed on a part of the surface of the patterned solder mask layer, and is electrically connected to at least one of the first or second signal contacts. According to a preferred embodiment of the present invention, the aforementioned power / ground contact includes, for example, at least one power plane and at least one ground plane, and the power plane can be electrically connected to at least one first signal contact, and the ground plane is electrically Connect at least one second signal contact. In addition, the circuit substrate may further include an oxygen-proof U-layer, which covers the surfaces of the first signal contact, the second signal contact, and the power / ground contact, and the anti-oxidation layer is selected from, for example, nickel, gold, and One of nickel-gold alloys. In order to achieve the above object of the present invention, the present invention provides a chip package junction

13192twf.ptd Page 9 1237379 V. Description of the Invention (5), ‘mainly includes-the circuit substrate, and the j 'circuit substrate has a plurality of first d :: and-wafers. No. — on the surface. In addition, Figure Macro γ is on the -surface 'of the circuit substrate and exposes the-^ of the two substrates and is electrically connected to the-contacts: the core substrate-a lightning source / ground contact, which is arranged in the patterned The covering soil has a function of electrically connecting at least one of the first contacts. Of it. On the surface of the trowel, according to the preferred embodiment of the present invention, the points include, for example, the periphery of the power / ground contact of an electric plane: a is located on the chip bonding area and the first reference planes. . In addition, it is used to provide the required voltage surface of the chip and the circuit substrate :: Yu Yue: Pull: The source / ground contact also includes, for example, a ground plane to provide a crystal; the peripheral surface of the first signal contact, /, Ground voltage reference plane required by the circuit board. : The transmission base Λ has a structure of △ multilayer signal transmission, and the signal cover / ground reference plane is located on the outermost welding plate; most of the layers of Γ and its cost. Because of &, the ^ face of the line base plus signal wire = as the space for the signal wire layout, so that the above and other features, features, and advantages of easy ηπ can be more clearly explained as follows. Take a preferred embodiment, and In accordance with the drawings, 详 V 2V, which is a detailed circuit board, shows a circuit base of the first embodiment of the present invention, w θ. The circuit substrate 2 00 mainly includes a plurality of patterned lines 13l92twf.ptd Page 10 1237379 V. Description of the invention (6) The circuit layers 210, 220, 230, 240, and a plurality of patterned dielectric layers 222 224, 226, -1 The patterned solder mask layer 25 and a power / contact 260 are provided. In this embodiment, the circuit substrate 200 is, for example, a plastic substrate, and the dielectric material is, for example, glass epoxy resin (FR_4, FR_g f ^ grease, or epoxy resin. In addition, the circuit substrate 2QQ may also be For other types of substrates, such as ceramic substrates, glass substrates, organic / inorganic substrates with soft dielectric constants, etc., each patterned dielectric layer is 222, 224, 226 lower between adjacent two patterns. Between the circuit layer 21Q, 22〇, 230, 240, and the patterned dielectric layer 22 2, 224, 226. Most of the conductive vias 232, 234 (only the second one is shown). The patterned circuit layer is between 210, 240 or 220, 230. It is worth noting that in this embodiment, the innermost circuit 220, 230 is no longer used as the power plane or ground of the circuit substrate 2000. Plane, so in circuit design, the innermost and outermost circuit layers 21, 220, 230, and 240 can be used as signal conductors of the circuit board 200 to increase the area of signal conductors. In addition, the board The power plane and ground plane of the industrial 200 are not on the line base. Within 200: 2 Therefore, the transmission stability during flood transmission will not pass through the reference voltage. Shenyang ~ plus Λ Please also refer to Figure 2, the first surface 202 and the first surface of the circuit board 2 0 0 The second surface 2 0 4 has a plurality of first signal contacts 2 and 2 and a signal contact 242 'the first—and the second signal contacts ⑴, such as the third one—a layer 21V 240 (for example, copper Foil layer) is defined by lithographic etching, and the first and second signal contacts 212, 242 can be

1237379 V. Description of the invention (7) The conductive vias 242 inside the board 200 are electrically connected to each other to transmit the electronic name. In addition, the patterned solder mask layer 250 can also cover the outermost patterned circuit layers 210 and 240 to protect the circuit, and the patterned solder mask layer 25 is to expose the first and second signal contacts 212. , 242, as the connection points of the circuit board 200 externally connected to the chip (as shown in Figure 5), passive components (not shown) or large printed circuit boards (not shown). Φ As shown in FIG. 2, after the patterned solder mask layer 250 is formed in this embodiment, a power / ground contact 2 60 (or power / ground layer) is formed on a part of the surface of the patterned fresh mask layer 250. And the power / ground contact 26 is a power plane and a ground plane formed by, for example, electricity mining and / or money plating. The material can be an oxidation-resistant conductive material, such as aluminum, gold, or beans. Alloy metal. In addition, the power / ground contact 2 60 can also be a conductive or thermally conductive copper layer or copper alloy as a power plane or a ground plane, and then covered with an anti-oxidation layer (not shown) on the surface of the copper layer. To avoid oxidation of the copper layer. The material of the anti-oxidation layer may be selected from nickel, gold or nickel-gold alloy. FIG. 3 is a schematic top view of a circuit substrate according to the present invention. The drawing shows a schematic cross-sectional view of another circuit substrate of the present invention. FIG. 5 is a schematic cross-sectional view of a chip packaging structure according to the present invention. It is also worth noting that the above-mentioned power plane and ground plane may be located on the same surface of the circuit substrate or on different surfaces. As shown in FIG. 3, when the power plane 310 and the ground plane 320 are located on the same surface 300, the power plane 310 and the ground plane 320 may be located on both sides of the circuit substrate 300 or around the substrate 300, respectively. Route the first signal contact 3 1 2 on the peripheral surface and

1237379 V. Description of the invention (8) The plane 3 1 0 and the ground plane 3 2 0 are electrically connected to at least one first signal contact 3 1 4 and 3 1 6 respectively, and the array of first signal contacts 3 1 2 The area surrounded by 3, 4 and 3 1 6 is, for example, a wafer bonding area 3 1 8 or a configuration area of other electronic components. The wafer (not shown) is, for example, a flip-chip bonding type or a wire bonding type. It is electrically connected to the first signal contact 3 1 2, 3 1 4, 3 1 6. Furthermore, as shown in FIG. 4, when the power plane 4 1 0 and the ground plane 4 2 0 are located on the surfaces of the solder mask layer 4 50 above the first and second surfaces 402 and 404 of the circuit substrate, respectively, the power plane 4 1 0 and ground plane 4 2 0 can be located on the circuit board

The upper and lower sides of 4 0 0 are electrically connected to at least one first signal contact 41 2 and at least one second signal contact 4 1 4 respectively. Referring to FIG. 5, when the chip 330 is disposed on the first surface 3 2 of the circuit substrate 300, the power plane 3 1 0 and the ground plane 3 2 0 are preferably located on the periphery of the surface on which the chip 3 3 0 is disposed. In particular, the chip packaging structure of wire bonding, using the large-area power plane 3 丨 0 and the ground plane 3 2 Q of the present invention, can produce a metal shielding effect to avoid the occurrence of the interference between adjacent wires 332 that transmit signals. The phenomenon of inductive coupling. In addition, a plurality of solder balls (340), pins (pins), or other conductive bumps can be arranged on the second surface 3 04 of the circuit substrate 300 to serve as a circuit.

Medium for signal transmission between board 300 and external electronic devices (such as large printed circuit boards). b [Second Embodiment] Fig. 6 is a schematic diagram of a second embodiment of the present invention. Please refer to FIG. 6 ′ The three-layer circuit = 50 0 is mainly composed of a plurality of rearward deep roadbeds, similar to the circuit layers 510, 52, and 54 and a plurality of drawings.

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5. Description of the invention (9) The dielectric layers 522 and 524 are stacked on each other, and each patterned dielectric layer 522 and 524 is located between two adjacent circuit layers 510, 520 and 540. In the circuit design of this embodiment, the innermost circuit layer 5 2 0 is used as a power plane of the circuit board 500, and is used as a power input terminal required for signal transmission of Nissan. In addition, the outermost circuit layers 5 丨 〇, 5 4〇 can be finely etched to become signal conductors of the circuit substrate 5000, and the two can be dreamed = electrically connected by the conductive via 532 or the conductive hole, To reach the signal =

Said. & J Please also refer to FIG. 6. The first surface 502 and the second surface 504 of the circuit substrate 500 have a plurality of first signal contacts 512 and a plurality of second signal contacts 542, respectively. These first and second signals The contacts 512 and 542 are, for example, t-lines, and the layers 51Q and 54 () (for example, the plutonium layer) are generalized in the manner of lithography. In addition, the first and second surfaces 502, 504 of the substrate 500 can cover a patterned solder mask layer 550, and the patterned solder mask layer 5500 "exposes the first and second signal contacts. 512, 542. It is worth noting that after the Xue cover layer 550 is patterned by Λ Chengan, a power / ground contact 5 6 0 is formed in Tuxing J. The left contact 560 is, for example, the cover layer 550. Part of the surface is a ground formed by the power source / connecting plane, its material and / or splattering method. In this embodiment, “the same as described in the embodiment” will not be repeated here. ! Λ on the ground plane (such as the reference number 56 () is located on a power plane Γ sub-surface), and the inside of the circuit board 5 0 0 is only equipped with the number of layers from the Xi, 52 ^ G, so the circuit board The number of three layers in the circuit layer is reduced ^ The number of layers is reduced to three, and the number of layers in the dielectric layer is also known from the sentence / layer-so the number of layers in the circuit substrate 5 0 0 is reduced and the cost is also reduced.

1237379 V. Description of the invention (10) Relative decrease. In addition, the signal transmission will not pass through the plane where the ground voltage is located, thereby increasing the stability during signal transmission. On the other hand, the above-mentioned power plane and ground plane are interchangeable, that is, the innermost circuit layer 520 can be used as a connection plane of the circuit substrate 500 as a ground terminal required for signal transmission. In addition, the power / ground contact 5 6 0 is a flat surface formed by, for example, plating and / or sputtering, and the remaining parts are the same as those configured in FIG. 6. Therefore, when transmitting signals, a power plane (such as the number 52) or a ground plane (such as the number 560) can be used as the reference plane to avoid signal loss caused by the first and second implementations. For example, it can be known that the present invention and its circuit substrate are characterized by wires; :: the space for wiring is arranged to increase the area of the signal conductor: ΐ =; Γ =;隹 ί ί The circuit layer can be used as the voltage or grounding parameter required for the signal transmission of the signal wire; = The road = the same part of the surface, such as "^ ^ ^ t., Ν„ ,, # 同 同-surface On or on different surfaces to form a crystal on the chip: power source :: = ground, although the present invention has been described in a preferred embodiment, ^: 冓. Ζ limits the present invention, anyone familiar with this technique will not be used. The arsenic and the range can be modified and retouched without departing from the essence of the present invention. Therefore, the protection of the present invention 13l92twf.Ptd page 15 1237379 V. Description of the invention (11) The ones defined in the scope of patent application shall prevail.

Hill 13192twf.ptd Page 16 1237379

FIG. 3 is a top view of a circuit substrate of the present invention. FIG. 4 is a cross-sectional view of another circuit substrate of the present invention. FIG. 5 is a cross-sectional view of a chip packaging structure according to the present invention; FIG. 6 is a diagram showing a second embodiment of the present invention. intention. The diagram of the cross-section of the board is not explained. 1 0 ·· Circuit substrate 14 〇: Circuit layer patterned dielectric layer 110, 120, 130 122, 124, 126 1 3 2: Conductive via hole 2 0 0: Circuit substrate 202, 204: first surface 210, 220, 230, 240: patterned circuit layer 2 1 2, 242: first signal contact, second signal contact 222, 224, 226: patterned dielectric layers 232, 234 : Conductive through hole 2 5 0: Patterned solder mask layer 26 0: Power / ground contact 3 0 0: Circuit board 3 0 2, 3 04: First surface, second surface

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1237379 Brief description of the diagram 3 1 0: power plane 3 1 2, 3 1 4, 3 1 6: first signal contact 318 chip bonding area 320 ground plane 330 chip 332 wire 340 solder ball 400 circuit board 402, 404 ·· First surface, second surface 4 1 0: power supply plane 4 1 2, 4 1 4: first signal contact, second signal contact 420 ground plane 450 solder mask layer 500 circuit substrate 502, 504 · · first surface 2nd surface 5 1 0, 5 2 0, 5 4 0: circuit layer 5 1 2, 5 4 2: first signal contact, second signal contact 522, 524: patterned dielectric layer 532 conductive via 550 patterned solder mask layer 560 power / ground contact

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Claims (1)

1237379 l A circuit substrate, comprising: a plurality of patterned circuit layers; at least one patterned dielectric layer, which is placed between the adjacent patterned circuit layers, and the patterned dielectric layer has at least one conductive path A hole electrically connected between some of the patterned circuit layers; a patterned solder mask layer covering the outermost layer of the patterned circuit layers; a power / ground contact disposed on the patterned A part of the surface of the solder mask layer is electrically connected to at least one of the pattern and circuit layers. 2. The circuit board according to item / item of the scope of application for a patent, wherein the power / ground contact includes at least a power source and at least one ground plane, and the power plane and the ground plane are respectively located in the patterned welding cover. Layers are on different areas of the same surface. 3. The circuit board according to item 1 of the scope of patent application, wherein the power / ground contact includes at least one power plane and at least one ground plane, and the power plane and the ground plane are located on the patterned solder mask layer, respectively. No 4 · If the second or third patent scope of the patent application, the power plane and the ground plane are _ covered with an anti-oxidation layer. The circuit substrate according to the above item, wherein the steel layer and the surface of the copper layer are also covered with 5 · —a type of circuit substrate, including: a signal contact; two signal contacts; two patterned circuit layers and a first patterned circuit Layer having a plurality of first and second patterned circuit layers and a plurality of patterned dielectric layers disposed on the first and the first 13l92twf.ptd Page 19 VI. Between the scope of patent application, and the patterning is connected to the _ | |, there is at least one guide thunder ϋ ^ ^-graphic information; '· through hole' between the contacts The electrical connection layer is exposed with a cover = a first and a second patterned line, a power / ground contact, and a brother; a signal contact with the brother; on the surface, and electrically connect these First Hai-Part of the patterned solder mask layer Table 6. If at least one of the two signal contacts of the second patent application scope. The source / ground contact includes at least one of the circuit substrates, wherein the power and the power plane are electrically connected to 〃, ', the plane, and at least one ground plane, grounded with a number US: —' and the source / two V Package Special: to Fan Er 5 = circuit substrate, which ... and the power plane disk to the ground plane / two sides / and at least-ground plane 'signal contact; to the thousand planes to electrically connect the first- Or the second ?. The circuit substrate as described in item 5 of the scope of patent application, further including an anti-oxidation layer covering the first signal contacts, the second signal contacts, and the power / ground contact. On the surface. 9. The circuit board according to item 8 of the patent claim, wherein the anti-oxidation layer is selected from one of nickel, gold and nickel-gold alloy. 1 0 · A chip packaging structure including: a circuit substrate having a first surface, the first surface having a plurality of first contacts; a patterned solder mask layer covering the first of the circuit substrate Surface, and the first contacts are exposed; and III m I 13192twf.ptd Λ ^-1237379 ------ VI. A patent is required to be connected: the chip is arranged on the circuit substrate and connected with the No. 1 connection: The pattern has a power / ground contact, and is arranged at least at least “on the surface” and electrically connected to these No. 1 connection, among which 1J ·, :: 1 所述 described in item 10 of the patent scope The chip power package / ground contact in the chip package structure includes at least one power plane: the second structure's-the peripheral surface of the contact. "The chips described in Section 10 of the Section 1 Electricity 2. Erli range. In the packaging structure, the power supply / ground contact also includes at least one ground plane, its position, and a peripheral surface of the first contact. In these 13. The chip package described in item 1 of the patent application scope, the circuit substrate also has a plurality of second contacts, which are located on a second surface of the circuit substrate, and the second substrates The contacts are electrically connected to the first contacts. 1 4 · The chip package structure described in item 13 of the scope of patent application, wherein the circuit substrate further has at least one conductive through hole electrically connected to at least one of the power / ground contact and the second contacts. between. 1 5 · The chip packaging structure as described in item No. 0 of the patent application scope, wherein the δ-Hai wafer is arranged on the first surface in a flip-chip bonding mode. 1 6. The wafer cracking structure according to item 1 of the patent application scope, wherein the wafer is arranged on the first surface in a wire bonding mode. Its 17 · As in the chip package structure described in item 10 of the patent application scope, the first surface also has a wafer bonding area ', and the first contacts are located at 13l92twf.ptd No. 21 tribute 1237379 6. Application The scope of the patent is the periphery of the wafer land. 1 8. The chip packaging structure according to item 10 of the scope of patent application, wherein the first surface further has a wafer bonding area, and the first contacts are located in the wafer bonding area. 1 9. A chip packaging structure comprising: a circuit substrate having a first surface and a corresponding second surface, the first surface having a plurality of first contacts; a patterned solder mask layer covering the The first surface of the circuit substrate, and the first contacts are exposed; at least one power / ground layer is disposed on a part of the surface of the patterned solder mask layer, and is electrically connected to at least one of the first contacts A chip disposed on the circuit substrate and electrically connected to the first contacts; and a packaging gel encapsulating the chip and part of the first surface of the circuit substrate / wherein the power source / ground layer The system is exposed outside the encapsulant. 20. The chip packaging structure according to item 19 of the scope of the patent application, wherein the chip has at least one power / ground pad, and the power / ground pad is electrically connected to the power / ground layer. 2 1. The chip package structure described in item 20 of the scope of patent application, wherein the chip is electrically connected to the power / ground layer through the first contact. 2 2. The chip package structure according to item 19 of the scope of patent application, wherein the power / ground layer is partially covered by the packaging gel. 2 3. The chip package structure described in item 19 of the scope of patent application, which 13192twf.ptd Page 22 1237379 6. In the scope of patent application, the power / ground layer includes at least one power layer and at least one ground layer, and the power layer and the ground layer are located at different positions on the first surface. 2 4. The chip package structure according to item 19 of the scope of patent application, wherein the power / ground layer extends to the edge of the circuit substrate. 2 5. The chip package structure described in item 19 of the scope of patent application, further comprising a plurality of solder balls, which are arranged on the second surface of the circuit substrate and are electrically connected to the first contacts. 13192twf.ptd Page 23