JP2002076278A - Semiconductor device having antenna member - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has body of an antenna, suitable for a mobile apparatus integrated with a semiconductor IC. SOLUTION: On a semiconductor IC substrate 1, formed with a plurality of circuit elements, the antenna member 11 which is constituted of a metal interconnection is provided, and the faces and upper face of the antenna element are coated with a dielectric material 12 having a relative permittivity of 10 or larger.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an integrated antenna.

[0002]

2. Description of the Related Art As a communication component mounted on a portable device or the like, there is a semiconductor chip in which an antenna and a semiconductor integrated circuit (LSI) are incorporated. Usually, the antenna and the LSI are separately assembled on a substrate, and a ratio of a mounting area is increased. Is about one to one.
The antenna in this case is used for both transmission and reception.

[0003] There is no communication LSI having an antenna integrated therein, and it is assumed that the antenna is integrated in the LSI, and a plurality of antennas are arranged in the LSI in order to identify a source of electromagnetic noise generated inside the LSI. (Japanese Patent Laid-Open No. 11-103018). The antenna in this case has been used only for receiving electromagnetic wave noise. There is no concept of using it for communication.

[0004]

In portable equipment, an antenna occupies about half of the mounting area, which is an obstacle to miniaturization of portable equipment.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which an antenna and a semiconductor integrated circuit suitable for use in a portable device are integrated, taking into consideration the above-mentioned conventional problems.

[0006]

According to the present invention, an antenna member made of metal wiring is provided on a semiconductor integrated circuit board on which a plurality of circuit elements are formed, and a side surface and an upper surface of the antenna element are separated by a relative dielectric constant. It is characterized by being coated with a dielectric material having a rate of 10 or more.

[0007] According to the above-described configuration, the antenna is formed as an LSI.
, The mounting area can be reduced, and the size of the portable device can be reduced.

Further, a grounded metal wiring layer may be formed between the antenna member and a semiconductor integrated circuit formed thereunder.

According to the above configuration, the electromagnetic wave output from the antenna member is absorbed by the metal wiring layer provided between the antenna member and the LSI, and the influence of the LSI on the transistor can be eliminated.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a sectional view showing a semiconductor device having an antenna member according to the present invention.

As shown in FIG. 1, a plurality of semiconductor circuit elements are formed in a p-type silicon substrate 1, and an integrated circuit constituting a communication circuit and the like is formed. FIG. 1 shows a MOS transistor part forming a part of an integrated circuit. In this embodiment, the p-type silicon substrate 1
After digging a shallow trench (200 nm to 500 nm), an oxide film is buried and STI (Shallow Trench)
h Isolation) is formed to separate the p-type silicon substrate 1 into an active region and a field region.

In the portion shown in FIG. 1, an n-ch transistor is taken as an example. A gate oxide film 3 is provided on a substrate 1 and a gate electrode 4 made of polysilicon is provided thereon.
Is provided. Side walls 5 are formed on both sides of the gate electrode 4 by a silicon insulating film.

In the substrate 1, a diffusion layer 6 serving as a source / drain is formed. A silicon oxide film 7 is provided as an interlayer insulating film on the substrate 1 including on the gate electrode 4, and a contact hole 8 for metal wiring is provided in the silicon oxide film 7. The diffusion layer 6 and the first metal electrode 9 are connected via the contact hole 8. On this first metal electrode 9, a silicon oxide film 10 is provided as an upper interlayer insulating film. Silicon oxide film 11 in circuit portion to be connected to antenna member
A via hole is formed in the substrate. A metal wiring 12 serving as an antenna member is formed on the silicon oxide film 11 in a desired pattern.

The side and top surfaces of the metal wiring 12 are covered with an insulating film having a relative dielectric constant of 10 or more. As described above, when the uppermost metal wiring 12 is used as an antenna member, the antenna can be reduced in size when covered with a member having a high relative dielectric constant. That is, by surrounding the periphery of the antenna with an insulating film having a relative permittivity ε, the effective wavelength λg becomes λ0 / ε.
^{Since it is 1/2} , the effective wavelength λg of the space where the antenna exists can be made shorter than the free space wavelength λ0.

In this way, the antenna can be integrated in the LSI, the mounting area can be reduced, and the size of the portable device can be reduced.

Next, an example of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. First, FIG.
As shown in the figure, after a p-type silicon substrate 1 is prepared and a shallow groove (200 nm to 500 nm) is dug in this substrate 1,
An oxide film is embedded and STI (Shallow Trend
An element isolation 2 called “ch isolation” is formed (see FIG. 2B). Thus, the p-type silicon substrate 1 is separated into an active region and a field region.

Next, an impurity (for example, boron for an n-ch transistor) for adjusting a transistor threshold is ion-implanted (20 keV, 5E12c) into the active region.
m ⁻² ), a gate oxide film 3 is formed on the substrate 1 by about 5 nm.
The gate polysilicon 4 is deposited thereon, and is formed to a desired size by a photolithography etching process. Then, the sidewalls 5 are formed by the silicon insulating film (see FIG. 2C).

Subsequently, impurities are ion-implanted to form a diffusion layer 6 serving as a source / drain of the transistor. As an injection condition of the n-ch transistor, for example,
Arsenic is implanted under the conditions of 30 keV and 2E15 cm ^-2 (see FIG. 2D).

After depositing a silicon oxide film 7 as an interlayer insulating film, a contact hole 8 for a metal wiring is formed by a photolithographic etching step (see FIG. 2E).
After depositing the metal layer for a metal electrode, the first metal electrode 9 is formed by a photolithographic etching process (see FIG. 2F).

Next, a silicon oxide film 10 serving as an upper interlayer insulating film is deposited (see FIG. 3G). After that, a via hole is formed in the silicon oxide film 10 by a photolithography etching process, a metal layer is deposited, and the metal wiring 11 is formed to a desired size by the photolithography etching process. This metal wiring 1
1 is used as an antenna (see FIG. 3 (h)).

Subsequently, the dielectric material 12 having a relative dielectric constant of 10 or more is used.
Is deposited on the metal wiring 11, and the side and top surfaces of the metal wiring are covered with a dielectric (see FIG. 3 (i)). This dielectric 12
Is, for example, a PZT-based material or an SBT-based material or P
An LZT-based material, a BST-based material, or a BTO-based material is deposited by MOCVD, sputtering, or a sol-gel method (or an epitaxial method). In addition to the above materials, a PVF2 ferroelectric material which is an organic substance may be deposited.
Thus, the semiconductor device according to the present invention is formed.

Usually, an LSI has two or more metal wiring layers, but in this embodiment, two layers are used for simplicity. Although an example using a typical photolithography etching process for forming a metal wiring to a desired size has been described, a damascene process or a dual damascene process may be used as a metal wiring forming method.

When an antenna is made using metal wiring on an LSI, the electromagnetic wave output from the antenna is LS
This may adversely affect the transistors in I. Therefore, in a second embodiment of the present invention shown in FIG.
The effect of such electromagnetic waves has been eliminated. In addition,
Components having the same configuration as the first embodiment are denoted by the same reference numerals,
Here, the description is omitted to avoid duplication of the description.

As shown in FIG. 4, in the second embodiment, the lower part of the metal wiring 11 used as an antenna
A grounded metal plate 13 is provided between the transistor constituting the SI and the like. That is, a grounded metal plate 13 is provided on the upper silicon oxide film 10, and a silicon oxide film 14 is provided thereon as an insulating film. And
The metal wiring 1 serving as an antenna is formed on the silicon oxide film 14.
1 and a dielectric 12 is provided.

With this configuration, the antenna 11
The electromagnetic wave output from the device is absorbed by the metal plate 13 provided between the device and the LSI, so that the effect of the LSI on the transistor can be eliminated.

Next, an example of manufacturing the semiconductor device shown in FIG. 4 will be described with reference to FIGS. First, similarly to the first embodiment, as shown in FIG. 5A, a p-type silicon substrate 1 is prepared, and a shallow groove (200 nm to 5 nm) is formed in the substrate 1.
Then, an oxide film is buried to form an element isolation 2 (see FIG. 5B).

Subsequently, an impurity (for example, boron for an n-ch transistor) for adjusting a transistor threshold is ion-implanted (20 keV, 5E12 cm) into the active region.
After the implantation in ^-2 ), a gate oxide film 3 is formed to a thickness of about 5 nm on the substrate 1, and a gate polysilicon 4 is further deposited thereon, and is formed to a desired size by a photolithography etching process. Then, the sidewalls 5 are formed by the silicon insulating film (see FIG. 5C).

Thereafter, impurities are ion-implanted to form a diffusion layer 6 serving as a source / drain of the transistor. As an injection condition of the n-ch transistor, for example,
Arsenic is implanted under the conditions of 30 keV and 2E15 cm ^-2 (see FIG. 5D).

Next, a silicon oxide film 7 is used as an interlayer insulating film.
Is deposited, a contact hole 8 for metal wiring is formed by a photolithographic etching step (see FIG. 5E). After depositing a metal layer for a metal electrode, a first metal electrode 9 is formed by a photolithography etching process, and then a silicon oxide film 10 serving as an upper interlayer insulating film is deposited (see FIG. 6F).

Thereafter, a via hole is opened in the silicon oxide film 10 by a photolithographic etching process, and a metal plate 13 is formed.
Is deposited and formed into desired dimensions by photolithographic etching. Then, a silicon oxide film 14 is deposited on the metal plate 13 (see FIG. 6G).

A via hole is opened in the silicon oxide film 14 by a photolithographic etching process, a metal layer is deposited, and the metal wiring 11 is formed to a desired size by the photolithographic etching process. This metal wiring 11 is used as an antenna. next,
A dielectric 12 having a relative dielectric constant of 10 or more is deposited on the metal wiring 11, and the side and upper surfaces of the metal wiring are covered with the dielectric (see FIG. 6 (i)).

In the third embodiment of the present invention shown in FIG. 7, the antenna has a multilayer structure. In addition,
The same components as those of the second embodiment are denoted by the same reference numerals,
Here, the description is omitted to avoid duplication of the description.

In the third embodiment shown in FIG. 7, two layers of metal wiring serving as an antenna, that is, metal wirings 11 and 11 are used.
a, and each is covered with dielectrics 12 and 12a to form a helical antenna.

[0034]

As described above, according to the present invention, the antenna can be integrated in the LSI, the mounting area can be reduced, and the size of the portable device can be reduced.

Further, by forming a grounded metal wiring layer between the antenna member and the semiconductor integrated circuit formed thereunder, the electromagnetic wave output from the antenna member can be integrated into an LSI.
Is absorbed by the metal wiring layer provided between the transistors, and the effect of the LSI on the transistor can be eliminated.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device having an antenna member according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing a semiconductor device provided with an antenna member according to a second embodiment of the present invention.

FIG. 5 is a sectional view illustrating a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a semiconductor device including an antenna member according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation part 3 Gate insulating film 4 Gate electrode 6 Diffusion layer 7 Silicon oxide film (interlayer insulating film) 8 Contact hole 9 Wiring metal 10 Silicon oxide film (interlayer insulating film) 11 Metal wiring (antenna) 12 Dielectric body

Continued on front page F term (reference) 5F033 HH07 JJ07 KK01 MM01 MM02 NN01 QQ08 QQ37 RR01 RR04 RR21 SS00 SS08 SS11 VV00 VV03 5F038 AV06 AZ02 BH10 CD18 EZ13 EZ15 EZ20 5J046 AA07 AB13 QA02

Claims (2)

[Claims] An antenna member made of metal wiring is disposed on a semiconductor integrated circuit substrate on which a plurality of circuit elements are formed, and a side surface and an upper surface of the antenna element have a relative dielectric constant of 1.
A semiconductor device having an antenna member covered with zero or more dielectrics. 2. The semiconductor device having an antenna member according to claim 1, wherein a grounded metal wiring layer is formed between said antenna member and a semiconductor integrated circuit formed thereunder.