KR100709782B1 - High frequency semiconductor passive device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a high frequency semiconductor passive device and a method for manufacturing the same, which can improve the characteristics of the device by preventing the coupling between the inductor and the Q value decrease.

To this end, the high frequency semiconductor passive device of the present invention comprises a first insulating film formed on a semiconductor substrate having a predetermined substructure, a ground pattern formed on the first insulating film, and a second insulating film filling the first insulating film on which the ground pattern is formed. And a plurality of vias connected to one side of the ground pattern through the second insulating film, a plurality of metal wires for inductors formed on the second insulating film and having one side connected to the vias, and the metal wirings. And a signal shield formed on the second insulating film so as to be connected to one side of each of the inductor metal wires, and a ground shield formed horizontally across the two ends connected to the ground pad.

Ground Shield, Inductor, Metal Wiring, Coupling

Description

High Frequency Semiconductor Passive Device and Manufacturing Method Thereof {HIGH FREQUENCY SEMICONDUCTOR PASSIVE DEVICE AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a high-frequency semiconductor passive element according to the prior art.

2 is a cross-sectional view taken along the line AA ′ of FIG. 1.

3 is a layout view of a high-frequency semiconductor passive element using a pattern ground shield method according to the prior art.

4 is a cross-sectional view taken along line BB ′ of FIG. 3.

5 is a layout view of a high-frequency semiconductor passive element according to the present invention.

6 is a cross-sectional view taken along the line CC ′ of FIG. 5.

7A to 7C are sequential process cross-sectional views of a method for manufacturing a high frequency semiconductor passive device according to the present invention.

Figure 8 is a graph of the frequency-dependent coupling test results of the high frequency semiconductor passive device and the conventional high frequency semiconductor passive device of the present invention.

<Description of the symbols for the main parts of the drawings>

50 semiconductor substrate 51 first insulating film

52: ground pattern 53: second insulating film

54: Via 55: Metal Wiring

56 ground shield 57: signal line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency semiconductor passive device and a method of manufacturing the same, and more particularly, to a high frequency semiconductor device and a method of manufacturing the same, which can improve the characteristics of the device by preventing an increase in coupling between the inductor and a decrease in the Q value.

RFICs, which are in high demand mainly in wireless transceivers and portable information terminals, are manufactured by collectively or integrally manufacturing active elements such as transistors and passive elements such as lines, resistors, capacitors, and inductors on a semiconductor substrate. It is an integrated circuit.

In such RFICs, passive devices, especially inductors or capacitors, occupy a larger area than active devices, resulting in increased manufacturing costs due to the large consumption of expensive semiconductor substrates.

Therefore, in order to reduce the chip area and reduce the manufacturing cost of the RFIC, it is a problem to reduce the area occupied by the passive element.

Among the passive elements, the inductor is an indispensable element for impedance matching in the RF circuit. In particular, the inductor is a quality factor of the LC circuit used in a voltage controlled oscillator (VOC); Higher Q) may reduce phase noise.

However, due to leakage occurring between the inductor and the semiconductor substrate, it is difficult to implement an inductor having a high Q value in a complementary metal oxide semiconductor (CMOS) process.

As the inductor, a planar spiral coil is frequently used. The Q value of the spiral coil varies depending on the number of turns, the width of the metal wiring, the thickness of the metal wiring, the spacing, radius, and shape between the metal wirings. Conditions must be set.

In detail, the number of turns can be increased to increase the first inductance, which leads to an increase in the parasitic capacitance due to the increase in resistance due to the increased inductor area, resulting in a decrease in the Q value and the coupling effect with the substrate. Therefore, it is necessary to set an appropriate condition for the number of windings, since it causes a decrease in the use range while lowering the resonance frequency.

Second, in order to ensure low series resistance, the width of the metal wiring should be as wide and thick as possible. If the width of the metal wiring becomes too wide, parasitic capacitance may increase due to the increase of the inductor area, and the substrate loss may be increased. Because of this, proper conditions must be set.

Third, a hollow inductor should be implemented such that the thickness of the metal wiring is five times or more than the width of the metal wiring in order to reduce the negative mutual coupling.

Fourth, the spacing between metal lines should be minimized to minimize the inductor area and maximize mutual inductance.

Fifth, in order to minimize parasitic capacitance to the substrate, the multilayer metal wiring should be spherical on the top layer.

Sixth, it is advantageous to have a circular structure rather than a square structure, and to leave the center of the inductor empty, but leave about one third of the diameter of the inductor empty.

1 is a layout view of a high frequency semiconductor passive device according to the prior art, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1.

1 and 2, a first SiO ₂ insulating layer 11 is formed on a silicon substrate 10 on which predetermined lower structures are formed, and a ground pattern 12 is formed on the first SiO ₂ insulating layer 11. Is formed.

An upper portion of the first SiO ₂ insulating layer 11 on which the ground pattern 12 is formed is buried in the second SiO ₂ insulating layer 13, and the ground pattern 12 penetrates through the second SiO ₂ insulating layer 13. Is connected to the via 14.

In addition, the ground pattern 12 is electrically connected to one side of the inductor 15 spirally formed on the second SiO ₂ insulating layer 13 through the via 14, and has a central portion of the spiral inductor 15. Is empty without inductor wiring.

In addition, a signal line 16 connected to one end of the inductor 15 is formed on the second SiO ₂ insulating layer 13.

In such a conventional high frequency semiconductor passive device, as shown in FIG. 2, the currents of the inductor's magnetic field toward the silicon substrate are generated between adjacent inductors, thereby increasing EM coupling and increasing resistance, thereby increasing Q of the inductor. The problem of lowering the value occurs.

In addition, as a result of simulating the coupling effect between the inductors of the high-frequency semiconductor device according to the prior art using the HFSS of Ansoft, the conventional spiral inductor is a magnetic field of the silicon substrate 10 and the SiO ₂ insulating film (11, 13) Field) is transferred, causing the H-Field to cross to the other side through the substrate between adjacent inductors 15.

In order to prevent the Q value of the inductor due to the beat current in the conventional high frequency semiconductor device, a pattern ground shield method is conventionally used.

3 is a layout view of a high frequency semiconductor device using a pattern ground shield method according to the related art, and FIG. 4 is a cross-sectional view taken along line BB ′ of FIG. 3.

3 and 4, a radial polysilicon pattern 31 is formed on a silicon substrate 30 on which predetermined substructures are formed, and a first SiO ₂ insulating film filling the polysilicon pattern 31 is formed. A first ground pattern 34 of 32 is formed, and the first ground pattern 34 is electrically connected to the lower polysilicon pattern 31 through a contact 33.

Then, the ground pattern 34 is filled through the second SiO ₂ insulating film 35, the second ground pattern 36, the upper part of the second SiO ₂ insulating film 35 to fill the round pattern 34 is Is formed.

In addition, the second ground pattern 36, the second SiO ₂ insulating film 35, the upper formed is embedded in claim 3 SiO ₂ insulating film 37, wherein the inductor of a spiral upper portion of the 3 SiO ₂ insulating film 37 ( 39 and the signal line 40 metal wirings are formed.

The second ground pattern 36 is electrically connected to one side of the spiral inductor 39 formed thereon through the via 38 penetrating through the third SiO ₂ insulating layer 37.

As described above, a radial polysilicon pattern is formed below the inductor, and a ground pattern is connected to the polysilicon pattern to prevent a decrease in Q value by preventing an increase in resistance component due to a beat current component directed to the silicon substrate. .

However, in the case of applying the pattern ground shield method as described above, the Q value characteristic of the inductor was affected, but there was still a problem that the H-Field was turned to the other side through the substrate between adjacent inductors.

This, in turn, increases the coupling between adjacent inductors, causing a problem of decreasing the frequency use range while lowering the resonance frequency.

An object of the present invention for solving the problems according to the prior art is to form a ground shield between adjacent inductors to isolate from each other, it is possible to reduce the signal coupling between the inductors and prevent the reduction of the Q value of the inductors compared to the conventional method The present invention provides a high frequency semiconductor passive device and a method of manufacturing the same.

The high frequency semiconductor passive device of the present invention for solving the above technical problem comprises a first insulating film formed on a semiconductor substrate having a predetermined substructure, a ground pattern formed on the first insulating film, and a first insulating film having the ground pattern formed thereon. A second insulating film filling a second insulating film, a plurality of vias penetrating the second insulating film and connected to one side of the ground pattern, and a plurality of inductor metals formed on the second insulating film and having one side connected to the via, respectively. A signal line formed on the second insulating film so that a ground shield is formed to cross a wire, a horizontal line between the metal wires, and both ends thereof are connected to a ground pad, and a side of the metal wire for each inductor. It is configured to include.

In the high frequency semiconductor passive device of the present invention, the metal wiring is formed in a multilayer structure, and the ground shield may be formed horizontally on at least one or more layers of the metal wiring in the multilayer structure.

In addition, the high frequency semiconductor passive device manufacturing method of the present invention for solving the technical problem comprises the steps of forming a first insulating film on a semiconductor substrate having a predetermined substructure; Forming a ground pattern on the first insulating film; Forming a second insulating film on the entire upper surface of the first insulating film on which the ground pattern is formed; Forming a via hole through the second insulating layer to expose the upper surface of the ground pattern; Filling the via holes to form vias; A metal layer is formed on the second insulating layer including the via, and a patterning process is performed on the metal layer, so that a plurality of metal wires crossing one side of the via top surface and a ground shield intersecting between the respective metal wires. And forming a signal line connected to one side of each metal wiring.

In the method for manufacturing a high frequency semiconductor passive element of the present invention, the metal wiring is formed in a multilayer structure, and forms a contact for connecting each layer of the multilayer metal wiring, and the ground shield is at least one of the metal wiring of the multilayer structure. It can be formed horizontally in any one or more layers.

As described above, according to the present invention, the ground shield is formed between the metal wires for the inductor to prevent the H-field from crossing between the inductors to the opposite side, thereby increasing the coupling between the inductors, thereby improving the electrical characteristics of the device. You can.

The invention will become more apparent through the preferred embodiments described below with reference to the accompanying drawings. Hereinafter will be described in detail to enable those skilled in the art to easily understand and reproduce through embodiments of the present invention. In addition, the thickness or size of each layer in the drawings may be exaggerated for convenience and clarity of description. In the drawings, like numerals refer to like elements.

5 is a layout view of the high-frequency semiconductor passive device according to the present invention, Figure 6 is a cross-sectional view taken along the line CC 'of FIG.

5 and 6, a first insulating film 51 formed on a semiconductor substrate 50 having a predetermined substructure is formed.

Although not shown in the drawings, the predetermined substructure may be a CMOS structure in which active devices such as a well, an isolation layer, a gate, and a source / drain are formed.

The semiconductor substrate 50 may be a silicon substrate, and the first insulating layer 51 may be made of SiO ₂ .

A ground pattern 52 is formed on the first insulating layer 51, and a second insulating layer 53 is formed on the first insulating layer 51 on which the first ground pattern 52 is formed.

The second insulating layer 53 may be made of a SiO ₂ material like the first insulating layer 51.

A plurality of vias 54 are formed in the second insulating layer 53 and penetrate the second insulating layer 53 to be connected to the ground pattern 52.

In addition, a plurality of inductor metal wires 55, one side of which is connected to the via 54 and electrically connected to the ground pattern 52, on the second insulating layer 53, and the respective metal wires. Signal lines 56 connected to one side are formed.

In this case, although the metal wire 55 is formed in a single layer structure in the embodiment of the present invention, it may be formed in a multi-layer structure, the metal wire 55 of each layer may be a spiral structure.

In addition, the center of the spiral metal wire is to allow the metal wire for the inductor is stopped so that the center is empty, it is advantageous to leave about 1/3 of the entire diameter of the metal wire empty.

In addition, a ground shield 57 is formed between the metal wires 55 horizontally therebetween and both ends thereof are connected to the ground pad G, respectively.

In the embodiment of the present invention, the inductor metal wiring 55 is formed as a single layer on the uppermost layer, and the ground shield 57 is formed to be flush with the metal wiring 55 at the same height. The metal wiring 55 may be formed in a multilayer structure, and the ground shield 57 may be formed horizontally on at least one or more layers of the multilayer metal wiring 55.

As described above, in the high-frequency semiconductor passive device of the present invention, the ground shield is horizontally interposed between the inductors, and the insulation current between the inductors is prevented, thereby preventing the occurrence of a beat current directed to the silicon substrate. This prevents the field from falling over.

As a result, not only the EM coupling between the inductors can be prevented, but also the Q value can be prevented from being increased due to the increase in resistance due to the beat current.

Hereinafter, a high frequency semiconductor passive device manufacturing method of the present invention will be described with reference to the drawings.

First, as shown in FIG. 7A, a first insulating layer 51 is formed on a semiconductor substrate 50 having a predetermined substructure, a metal layer is deposited thereon, and a patterning process using a predetermined photo and etching process is performed. Proceeding to form a ground pattern 52 on the first insulating film (51).

In this case, the predetermined substructure may be a CMOS structure in which active elements such as a well, an isolation layer, a gate, and a source / drain are formed, although not shown in the same manner as described in the structure of the high-frequency semiconductor passive element of the present invention.

In addition, the semiconductor substrate 50 may be a silicon substrate, and SiO ₂ may be used as the first insulating layer 51.

Subsequently, as illustrated in FIG. 7B, the second insulating layer 53 is deposited on the entire upper surface of the first insulating layer 51 on which the ground pattern 52 is formed, and the second insulating layer 53 is formed by performing a photo and etching process. Through-holes 54a are formed to expose upper surfaces of the ground patterns 52.

In this case, as the second insulating film 53, a SiO ₂ material may be used as in the first insulating film 51.

Then, as shown in FIG. 7C, the via hole 54a is filled to form the via 54, and a metal layer is formed on the second insulating layer 53 including the via 54. The patterning process for the plurality of metal wires 55 crossing one side of the upper surface of the via 54 and the ground shield 56 and the signal line crossing between the respective metal wires 55 are performed. Form 57.

Each of the metal wires 55 is an inductor, and one side of each of the metal wires 55 crosses the vias 54 so that the metal wires 55 are electrically connected to the lower ground pattern 52 through the vias 54.

In the exemplary embodiment of the present invention, the inductor metal wiring 55 is formed as a single layer on the uppermost layer, and the ground shield 56 is formed at the same height as the uppermost metal wiring 55, but various embodiments are shown. Through the metal wiring can be formed in a multi-layer structure.

In addition, a contact connecting each layer of the multi-layer metal wiring may be formed, and the ground shield 56 may be formed horizontally on at least one or more layers of the multi-layer metal wiring. There is no need to limit the formation.

8 is a graph illustrating a coupling test result for each frequency of the high frequency semiconductor passive device of the present invention and the conventional high frequency semiconductor passive device.

In Figure 8 (a) is a high frequency semiconductor passive device of the present invention, (b) is a conventional general high frequency semiconductor passive device, (c) is a high frequency semiconductor passive device using a pattern ground shield method.

Here, the fabricated test patterns were measured by the Agilent 8510C. Each test pattern was made of 80 μm between each inductor, the inductor pattern was made of single poly and 5 metal, and the highest thickness of 1.5 μm in 0.25 μm standard CMOS. Lay out with metal.

In the high frequency semiconductor passive device of the present invention, the distance between the inductor and the ground shield is set to 25 μm.

As a result of simulation of the test patterns fabricated as described above, as shown in FIG. 8, the high-frequency semiconductor passive device (a) of the present invention, which has a ground shield in a region of 5 kHz or less, does not have a ground shield isolation; Compared with the high frequency semiconductor passive element (c) with the pattern ground shield, the coupling characteristics were about 15 dB better.

As such, the present invention can minimize electromagnetic coupling by isolating the inductors through the ground shield.

Accordingly, the problem of reducing the use range while reducing the resonance frequency in accordance with the increase in the coupling can be solved.

As described above, according to the present invention, the ground shield is formed between adjacent inductors and is isolated from each other, so that the signal coupling between the inductors can be reduced as well as the Q value even if the spacing between each inductor is narrow compared to the conventional method. There is an advantage that can improve the characteristics of the device by preventing the reduction.

Although the present invention has been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that many different and obvious modifications are possible without departing from the scope of the invention from this description. Therefore, the scope of the invention should be construed by the claims described to include many such variations.

Claims (4)

A first insulating film 51 formed on the semiconductor substrate 50 having a predetermined substructure, A ground pattern 52 formed on the first insulating layer 51; A second insulating film 53 which fills the first insulating film 51 on which the ground pattern 52 is formed; A plurality of vias 54 penetrating through the second insulating layer 53 and connected to one side of the ground pattern 52; A plurality of inductor metal interconnections 55 formed on the second insulating layer 53 and connected to one side of the via 54; A ground shield 56 formed horizontally across the metal wires 55 and having both ends connected to the ground pads 55; and And a signal line (57) formed on the second insulating film (53) so as to be connected to one side of each of the inductor metal wires (55). The method of claim 1, The metal wire 55 is formed in a multilayer structure, The ground shield (56) is a high-frequency semiconductor passive device, characterized in that formed in at least one layer of at least one layer of the metal wiring (55) of the multi-layer structure. Forming a first insulating film on a semiconductor substrate having a predetermined substructure; Forming a ground pattern on the first insulating film; Forming a second insulating film on the entire upper surface of the first insulating film on which the ground pattern is formed; Forming a via hole through the second insulating layer to expose an upper surface of the ground pattern; Filling the via holes to form vias; A metal layer is formed on the second insulating layer including the via, and a patterning process is performed on the metal layer, so that a plurality of metal wires crossing one side of the via top surface and a ground shield intersecting between the respective metal wires. And forming a signal line connected to one side of each metal wire; Method for producing a high frequency semiconductor passive device comprising a. The method of claim 3, wherein The metal wiring is formed in a multilayer structure, Forming a contact connecting each layer of the multilayer metal wiring, And the ground shield is formed horizontally on at least one or more layers of the metal wiring of the multilayer structure.

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