JP2006261297A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a dielectric element freely placeable without causing the magnetic flux of the element to affect the device or the like on a semiconductor substrate, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device 1 having the dielectric element 3 formed on the semiconductor substrate 2 is equipped with a shield 15 grounded to the substrate 2 via a grounding electrode 5 in a position overlapping in the thickness direction on the dielectric element 3 across insulation resin layers 10 and 12. Thus, the shield 15 blocks the magnetic flux of the dielectric element 3 to prevent the flux of the element 3 from affecting the device or the like on the semiconductor substrate 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which an induction element is provided on a base material via an insulating resin layer.

In recent years, in a semiconductor device such as a high-frequency semiconductor element, a spiral inductive element (spiral inductor) is formed on a semiconductor substrate such as a silicon wafer via an insulating resin layer in order to achieve impedance matching and the like. It has been broken. However, in such a semiconductor device, due to parasitic capacitance between the semiconductor substrate and the wiring portion formed thereon via the insulating resin layer, eddy current generated by the magnetic flux of the induction element passing through the semiconductor substrate, etc., Some of the electromagnetic energy generated by this inductive element may be lost. In this case, there arises a problem that the Q value and the self-resonant frequency of the inductive element are lowered. For this reason, in the semiconductor device, the above-described loss of electromagnetic energy is suppressed by providing a thick insulating resin layer between the semiconductor substrate and the inductive element and widening the distance between the semiconductor substrate and the wiring portion. (For example, refer to Patent Document 1).
JP 2003-86690 A

  By the way, in the semiconductor device described above, since the magnetic flux of the inductive element passing through the semiconductor substrate may affect the device on the semiconductor substrate and cause a malfunction, for example, induction is performed directly above a device such as an oscillation circuit. Elements cannot be placed. For this reason, the conventional semiconductor device has a problem that the inductive elements cannot be freely arranged (redistributed), and the degree of freedom in design is greatly reduced due to such a restriction.

  Therefore, the present invention has been proposed in view of such a conventional situation, and the object thereof is to freely arrange the induction element without the magnetic flux of the induction element affecting the device or the like on the semiconductor substrate. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

A semiconductor device according to claim 1 of the present invention is provided with a base material provided with an electrode portion, an insulating resin layer provided on the base material, and connected to the electrode portion through a hole formed in the insulating resin layer. And an inductive element provided on the wiring part via an insulating resin layer and connected to the wiring part through a hole formed in the insulating resin layer. And a shield portion is provided at least in a region overlapping with the induction element in the thickness direction.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the inductive element has a coil part formed in a spiral shape, and the shield part is at least an area inside the innermost peripheral part of the coil part. And in a region overlapping in the thickness direction.
According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the shield portion is further provided in a region overlapping with a region inside the outermost peripheral portion of the coil portion in the thickness direction.
According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the shield portion is further provided in a region overlapping with a region outside the outermost peripheral portion of the coil portion in the thickness direction.
A semiconductor device according to a fifth aspect of the present invention is characterized in that, in the first aspect, when the distance between the shield portion and the inductive element is D, 10 μm ≦ D ≦ 40 μm.
According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a base material provided with an electrode portion; and an electrode provided on the base material via an insulating resin layer and through holes formed in the insulating resin layer. A semiconductor device comprising: a wiring part connected to the wiring part; and an inductive element provided on the wiring part via an insulating resin layer and connected to the wiring part through a hole formed in the insulating resin layer. And a step of forming a shield part in a region located between the base material and the wiring part and overlapping at least the induction element in the thickness direction.

  As described above, according to the present invention, since the shield portion located between the base material and the wiring portion is provided at least in a region overlapping with the induction element in the thickness direction, the shield portion removes the induction element from the induction element. The magnetic flux can be properly blocked. Therefore, it is possible to prevent the magnetic flux of the inductive element from affecting the devices on the semiconductor substrate, and this inductive element can be arranged freely, so that the degree of freedom in design such as rewiring can be increased.

  Hereinafter, a semiconductor device to which the present invention is applied and a manufacturing method thereof will be described in detail with reference to the drawings. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for convenience, and the dimensional ratios of the respective components are the same as the actual ones. Not exclusively.

  As shown in FIGS. 1, 2, and 3, a semiconductor device 1 to which the present invention is applied has an inductive element 3 for impedance matching of a high-frequency semiconductor element formed on, for example, a semiconductor substrate 2 as a base material. is there.

  The semiconductor substrate 2 includes, for example, a first electrode 4a and a second electrode 4b constituting an electrode part, and a ground electrode constituting a ground part on the surface of a silicon wafer 2a on which an integrated circuit (not shown) is formed. 5. A passivation film 6 is formed on the semiconductor substrate 2 so as to cover the entire surface of the silicon wafer 2a on which the electrodes 4a, 4b, and 5 are formed. The passivation film 6 is formed with openings 7a, 7b, and 7c that expose the first electrode 4a, the second electrode 4b, and the ground electrode 5. The semiconductor substrate 2 is not limited to a wafer-like one such as the above-described silicon wafer 2a, but may be one obtained by cutting (dicing) the silicon wafer 2a as individual semiconductor chips.

  The semiconductor device 1 includes a first insulating resin layer 8, a shield layer 9, a second insulating resin layer 10, a lower wiring layer 11, and a third insulating resin layer 12 on the semiconductor substrate 2. And the upper wiring layer 13 are sequentially stacked.

  Among these, the first insulating resin layer 8 is formed so as to cover the surface of the semiconductor substrate 2. In addition, at the positions directly above the first electrode 4a, the second electrode 4b, and the ground electrode 5, that is, the positions facing the openings 7a, 7b, and 7c, hole portions that respectively penetrate the first insulating resin layer 8 in the thickness direction. 14a, 14b, and 14c are formed.

  The shield layer 9 has a shield portion 15 on the surface of the first insulating resin layer 8. The shield portion 15 is provided immediately below the inductive element 3 arranged in the upper wiring layer 13 described later, that is, in a region overlapping with the inductive element 3 in the thickness direction. The shield part 15 is electrically connected to the ground electrode 5 through a conductive part 5a formed in a hole part 14c serving as a contact hole.

  The second insulating resin layer 10 is formed so as to cover the surface of the first insulating resin layer 8 on which the shield portion 15 is formed. Further, the second insulating resin layer 10 is penetrated in the thickness direction immediately above the first electrode 4a and the second electrode 4b, that is, at a position continuous with the holes 14a and 14b of the first insulating resin layer 8. Holes 16a and 16b are formed.

  The lower wiring layer 11 has a first wiring part 17 a and a second wiring part 17 b on the surface of the second insulating resin layer 10. The first wiring portion 17a and the second wiring portion 17b are formed as a rewiring layer that performs electrical connection between the first electrode 4a and the second electrode 4b and the induction element 3. is there.

  At one end of the first wiring portion 17a and the second wiring portion 17b, substantially rectangular contact pads 18a and 18b are provided, respectively. Among these, the contact pad 18a of the first wiring part 17a is electrically connected to the first electrode 4a through the conductive part 19a formed in the hole parts 14a and 16a serving as contact holes. On the other hand, the contact pad 18b of the second wiring portion 17b is electrically connected to the second electrode 4b through a conductive portion 19b formed in the hole portions 14b and 16b serving as contact holes.

  The third insulating resin layer 12 is formed so as to cover the surface of the second insulating resin layer 10 on which the first and second wiring portions 17a and 17b are formed. In addition, holes 20a and 20b that penetrate the third insulating resin layer 12 in the thickness direction are respectively formed immediately above the other end side of the first wiring portion 17a and the other end side of the second wiring portion 17b. ing.

  The upper wiring layer 13 has the inductive element 3 on the surface of the third insulating resin layer 12. This inductive element 3 has a coil portion 3a formed in a spiral shape, and this coil portion 3a is disposed immediately above the shield portion 15, that is, at a position overlapping the shield portion 15 in the thickness direction. And the edge part of the inner peripheral side of the coil part 3a is electrically connected with the other end side of the 1st wiring part 17a via the electroconductive part 21a formed in the hole 20a used as a contact hole. On the other hand, the outer peripheral end of the coil portion 3a is electrically connected to the other end side of the second wiring portion 17b via a conductive portion 21b formed in a hole portion 20b serving as a contact hole.

  In the semiconductor device 1 having the above-described structure, the shield portion 15 grounded to the semiconductor substrate 4 via the ground electrode 5 has the thickness of the induction element 3 and the thickness between the second and third insulating resin layers 10 and 12. It is arranged at an overlapping position in the direction.

  Specifically, as shown in FIG. 1, the shield portion 15 is preferably formed in a region 15 </ b> A that overlaps in the thickness direction with a region inside at least the innermost peripheral portion of the coil portion 3 a where magnetic flux concentrates. . More preferably, the shield portion 15 is preferably formed in a shape corresponding to the coil portion 3a, that is, in a region 15B overlapping with a region inside the outermost peripheral portion of the coil portion 3a in the thickness direction. More preferably, the shield portion 15 is formed in a region 15C that is large enough to block the magnetic flux from the coil portion 3a, that is, overlaps in the thickness direction up to a region outside the outermost peripheral portion of the coil portion 3a. Preferably it is.

  As described above, the shield portion 15 blocks the magnetic flux from the induction element 3, thereby preventing the magnetic flux from the induction element 3 from affecting the devices on the semiconductor substrate 2. Therefore, in this semiconductor device 1, since the inductive element 3 can be freely arranged, the degree of freedom in design such as rewiring can be increased.

  By the way, in this semiconductor device 1, the distance D between the shield part 15 and the induction element 3 shown in FIG. 3 corresponds to the total thickness of the second insulating resin layer 10 and the third insulating resin layer 12. Yes. In the semiconductor device 1, the degree of capacitive coupling between the shield portion 15 and the inductive element 3 is changed by the distance D, and the self-resonant frequency of the inductive element 3 is affected.

  Therefore, the Q value of the inductive element 3 when the distance D between the shield portion 15 and the inductive element 3 is changed within a range of 5 μm to 80 μm, for example, was measured. The measurement results are shown in FIG. Further, the self-resonant frequency of the inductive element 3 when the distance D between the shield part 15 and the inductive element 3 was changed, for example, in the range of 5 μm to 80 μm was measured. The measurement results are shown in FIG. In the measurements shown in FIGS. 4 and 5, the thickness of the first insulating resin layer 8 is constant at 10 μm, and the number of turns of the coil portion 3a of the induction element 3 is 3.5 turns.

  From the measurement results shown in FIG. 4, it can be seen that although the Q value gradually increases as the distance D increases, the increase in the Q value saturates when it exceeds 40 μm. Further, from the measurement results shown in FIG. 5, the self-resonant frequency increases rapidly until the distance D reaches 10 μm, but as the distance D exceeds 10 μm, the self-resonant frequency gradually increases and exceeds 40 μm. It can be seen that the rise in is saturated.

  Therefore, the distance D between the shield part 15 and the induction element 3 is preferably 10 μm or more and 40 μm or less from the viewpoint of the manufacturing cost and manufacturing conditions of the semiconductor device 1.

  As described above, in this semiconductor device 1, the capacitive coupling between the shield part 15 and the induction element 3 can be suppressed by setting the distance D between the shield part 15 and the induction element 3 to 10 to 40 μm. It is possible to prevent the Q value and the self-resonant frequency of the inductive element 3 from being lowered.

Next, a method for manufacturing the semiconductor device 1 to which the present invention is applied will be described.
When manufacturing the semiconductor device 1, first, as shown in FIG. 6, a silicon wafer 2a to be a semiconductor substrate 2 on which an integrated circuit (not shown) is formed is prepared, and the surface of the silicon wafer 2a is prepared. The first electrode 4a, the second electrode 4b, and the ground electrode 5 are formed. Specifically, as the first electrode 4a, the second electrode 4b, and the ground electrode 5, for example, a substantially rectangular Al pad can be formed. Further, after forming the first electrode 4a, the second electrode 4b, and the ground electrode 5, a passivation film 6 is formed to cover the entire surface of the silicon wafer 2a on which the electrodes 4a, 4b, and 5 are formed. For example, SiN or SiO ₂ can be used for the passivation film 6. Moreover, when forming the passivation film 6, LP-CVD etc. can be used, for example. The thickness of the passivation film 6 is, for example, 0.1 μm to 0.5 μm. Then, after the passivation film 6 is formed, the passivation film 6 is patterned by a photolithography technique so that the first electrode 4a, the second electrode 4b, and the ground electrode 5 are exposed to the passivation film 6. 7a, 7b and 7c are formed.

  Next, as shown in FIG. 7, a first insulating resin layer 8 that covers the entire surface of the semiconductor substrate 2 is formed. For the first insulating resin layer 8, for example, a polyimide resin, an epoxy resin, a silicone resin, or the like can be used. Further, when the first insulating resin layer 8 is formed, for example, a spin coating method, a printing method, a laminating method, or the like can be used. Moreover, the thickness of the 1st insulating resin layer 8 is 1 micrometer-10 micrometers, for example. Then, after the first insulating resin layer 8 is formed, the first insulating resin layer 8 is patterned by a photolithography technique, so that the first electrode 4a, the second electrode 4b, and the ground electrode 5 are directly above. Then, holes 14a, 14b, and 14c that penetrate the first insulating resin layer 8 in the thickness direction are formed.

  Next, as shown in FIG. 8, a shield portion 15 to be the shield layer 9 is formed on the first insulating resin layer 8. The shield portion 15 is preferably formed in advance at a position overlapping with the induction element 3 in the thickness direction with a second and third insulating resin layers 10 to be described later interposed therebetween, and blocks the magnetic flux from the induction element 3. For example, it is formed in a substantially rectangular shape. Further, for example, Al, Cu, Au or the like can be used for the shield part 15. Moreover, when forming the shield part 15, sputtering method, a vapor deposition method, a plating method etc. can be used, for example. Moreover, the thickness of the shield part 15 is 1 micrometer-10 micrometers, for example. The shield portion 15 is electrically connected to the ground electrode 5 through the conductive portion 5a embedded in the hole portion 14c serving as a contact hole.

  Next, as shown in FIG. 9, a second insulating resin layer 10 that covers the entire surface of the first insulating resin layer 8 on which the shield layer 9 is formed is formed. For example, a polyimide resin, an epoxy resin, a silicone resin, or the like can be used for the second insulating resin layer 10. Further, when the second insulating resin layer 10 is formed, for example, a spin coating method, a printing method, a laminating method, or the like can be used. Then, after the second insulating resin layer 10 is formed, the second insulating resin layer 10 is patterned by a photolithography technique, thereby penetrating the second insulating resin layer 10 in the thickness direction and the first insulating resin layer 10. Holes 16a and 16b continuous with the holes 14a and 14b of the resin layer 8 are formed.

  Next, as shown in FIG. 10, the first wiring portion 17 a and the second wiring portion 17 b that become the lower wiring layer 11 are formed on the second insulating resin layer 10. These first and second wiring portions 17a and 17b can be formed by, for example, electrolytic copper plating. Moreover, the thickness of the 1st and 2nd wiring parts 17a and 17b is 1 micrometer-10 micrometers, for example.

  Further, substantially rectangular contact pads 18a and 18b are formed at one ends of the first wiring portion 17a and the second wiring portion 17b, respectively. Among these, the contact pad 18a of the first wiring part 17a is electrically connected to the first electrode 4a through the conductive part 19a embedded in the hole parts 14a and 16a serving as contact holes. On the other hand, the contact pad 18b of the second wiring portion 17b is electrically connected to the second electrode 4b by the conductive portion 19b formed in the hole portions 14b and 16b serving as contact holes.

  Next, as shown in FIG. 11, a third insulating resin layer 12 covering the entire surface of the second insulating resin layer 10 on which the lower wiring layer 11 is formed is formed. For the third insulating resin layer 12, for example, polyimide resin, epoxy resin, silicone resin, or the like can be used. Further, when the third insulating resin layer 12 is formed, for example, a spin coating method, a printing method, a laminating method, or the like can be used. And after forming this 3rd insulating resin layer 12, the 3rd insulating resin layer 12 is patterned by the photolithographic technique, The other end side of the 1st wiring part 17a and the 2nd wiring part 17b Holes 20a and 20b penetrating the third insulating resin layer 12 in the thickness direction are formed immediately above the other end side.

  Next, as shown in FIG. 12, the inductive element 3 to be the upper wiring layer 13 is formed on the third insulating resin layer 12. Specifically, the coil portion 3a of the induction element 3 is formed immediately above the shield portion 15, that is, at a position overlapping the shield portion 15 in the thickness direction. The coil portion 3a of the induction element 3 can be formed by, for example, electrolytic copper plating. Moreover, the thickness of the coil part 3a is 1 micrometer-10 micrometers, for example.

Further, the inner peripheral end of the coil portion 3a is electrically connected to the other end side of the first wiring portion 17a through a conductive portion 21a formed in the hole portion 20a serving as a contact hole. On the other hand, the outer peripheral end portion of the coil portion 3a is electrically connected to the other end side of the second wiring portion 17b through a conductive portion 21b formed in the hole portion 20b serving as a contact hole.
The semiconductor device 1 can be manufactured through the above steps.

  In the semiconductor device 1 manufactured through the above steps, the shield portion 15 grounded to the semiconductor substrate 4 via the ground electrode 5 has the inductive element sandwiching the second and third insulating resin layers 10 and 12 therebetween. 3 and a position overlapping with each other in the thickness direction. Thereby, the shield part 15 of the semiconductor device 1 to be manufactured can block the magnetic flux from the induction element 3, and the magnetic flux from the induction element 3 can be prevented from affecting the devices on the semiconductor substrate 2. Therefore, in the method for manufacturing the semiconductor device 1 to which the present invention is applied, the inductive element 3 can be freely arranged, so that the degree of freedom of design such as rewiring can be increased.

  In the method for manufacturing the semiconductor device 1, the distance D between the shield portion 15 and the induction element 3, that is, the total thickness of the second insulating resin layer 10 and the third insulating resin layer 12 is 10 to 40 μm. By doing so, it is possible to prevent capacitive coupling from occurring between the shield part 15 of the semiconductor device 1 to be manufactured and the inductive element 3, and to reduce the Q value and the self-resonant frequency of the inductive element 3. Can be prevented.

  The semiconductor device 1 has a configuration in which one inductive element 3 is disposed on the semiconductor substrate 2. However, the configuration is not limited to such a configuration, and a plurality of inductive elements 3 are disposed on the semiconductor substrate 2. It can also be set as the structure which carried out. The semiconductor device 1 may have a configuration in which a sealing layer covering the third insulating resin layer 12 on which the inductive element 3 is formed is provided as necessary. In this case, the sealing layer may be formed of, for example, polyimide resin, epoxy resin, silicone resin or the like with a thickness of about 10 to 150 μm. In the sealing layer, an opening for exposing a terminal for external connection is formed.

  The present invention is not necessarily limited to the semiconductor device 1 described above. For example, the present invention can also be applied to a semiconductor device such as a non-contact IC tag in which an induction element functions as an antenna coil. That is, the present invention can be widely applied to semiconductor devices in which induction elements are formed on a semiconductor substrate with an insulating resin layer interposed therebetween.

FIG. 1 is a perspective view showing a configuration of a semiconductor device to which the present invention is applied. FIG. 2 is a plan view showing the structure of the semiconductor device shown in FIG. 3 is a cross-sectional view taken along line AA shown in FIG. FIG. 4 is a characteristic diagram showing the relationship between the distance D and the Q value. FIG. 5 is a characteristic diagram showing the relationship between the distance D and the self-resonant frequency. FIG. 6 is a view for explaining a manufacturing process of the semiconductor device shown in FIG. 1, and is a cross-sectional view showing a state in which a semiconductor substrate is formed. FIG. 7 is a view for explaining a manufacturing process of the semiconductor device shown in FIG. 1, and is a cross-sectional view showing a state in which a first insulating resin layer is formed. FIG. 8 is a view for explaining a manufacturing process of the semiconductor device shown in FIG. 1, and is a cross-sectional view showing a state in which a shield layer is formed. FIG. 9 is a view for explaining a manufacturing process of the semiconductor device shown in FIG. 1, and is a cross-sectional view showing a state in which a second insulating resin layer is formed. FIG. 10 is a view for explaining a manufacturing process of the semiconductor device shown in FIG. 1, and is a cross-sectional view showing a state in which a lower wiring layer is formed. FIG. 11 is a view for explaining a manufacturing process of the semiconductor device shown in FIG. 1, and is a cross-sectional view showing a state in which a third insulating resin layer is formed. FIG. 12 is a view for explaining a manufacturing process of the semiconductor device shown in FIG. 1, and is a cross-sectional view showing a state in which an upper wiring layer is formed.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor substrate, 3 ... Inductive element, 3a ... Coil part, 4a ... 1st electrode, 4b ... 2nd electrode, 5 ... Ground electrode, 5a ... Conductive part, 6 ... Passivation film, 7a , 7b, 7c ... opening, 8 ... first insulating resin layer, 9 ... shield layer, 10 ... second insulating resin layer, 11 ... lower wiring layer, 12 ... third insulating resin layer, 13 ... upper part Side wiring layer, 14a, 14b, 14c ... hole, 15 ... shield, 16a, 16b ... hole, 17a ... first wiring, 17b ... second wiring, 18a, 18b ... contact pad, 19a, 19b ... conductive portion, 20a, 20b ... hole, 21a, 21b ... conductive portion

Claims (6)

A base material provided with an electrode part;
A wiring part provided on the base material via an insulating resin layer, and connected to the electrode part through a hole formed in the insulating resin layer;
An inductive element provided on the wiring part via an insulating resin layer and connected to the wiring part through a hole formed in the insulating resin layer;
A semiconductor device, wherein a shield portion is provided in a region located between the base material and the wiring portion and overlapping at least the induction element in the thickness direction. The inductive element has a coil portion formed in a spiral shape,
The semiconductor device according to claim 1, wherein the shield portion is provided in a region overlapping at least a region inside the innermost peripheral portion of the coil portion in the thickness direction.   The semiconductor device according to claim 2, wherein the shield portion is further provided in a region overlapping with a region inside the outermost peripheral portion of the coil portion in the thickness direction.   The semiconductor device according to claim 3, wherein the shield portion is further provided in a region overlapping with a region outside the outermost peripheral portion of the coil portion in the thickness direction.   2. The semiconductor device according to claim 1, wherein 10 μm ≦ D ≦ 40 μm, where D is a distance between the shield part and the inductive element. A base material provided with an electrode part;
A wiring part provided on the base material via an insulating resin layer, and connected to the electrode part through a hole formed in the insulating resin layer;
A method of manufacturing a semiconductor device comprising: an inductive element provided on the wiring portion via an insulating resin layer and connected to the wiring portion through a hole formed in the insulating resin layer,
A method of manufacturing a semiconductor device, comprising: forming a shield portion in a region located between the base material and the wiring portion and overlapping at least the induction element in the thickness direction.

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