KR100863009B1 - Substrate structure with built in inductor and method of manufacturing the same - Google Patents

Abstract

A substrate structure including an inductor and a manufacturing method thereof are provided to improve the Q factor of the inductor by reducing parasitic capacitance between conductive patterns. A base member(100) includes a conductive layer(110). An inductor includes a plurality of conductive patterns(120,130,140) which are stacked on an upper surface of the base member. An insulating layer is inserted between the conductive patterns. The conductive patterns are concentric patterns having a frame structure. The adjacent conductive patterns of the conductive patterns are arranged cornerwise not to be overlapped with each other. The conductive layer applies a predetermined signal to one conductive pattern selected from the conductive patterns.

Description

Substrate Structure With Built In Inductor And Method Of Manufacturing The Same

1 is a cross-sectional view showing a substrate structure containing a typical inductor;

2 is an exploded perspective view of a substrate structure having an inductor according to an embodiment of the present invention;

3 is a plan view of a substrate structure having an inductor according to an embodiment of the present invention;

4 is a plan view of a substrate structure having an inductor according to another embodiment of the present invention;

5A and 5B are plan views of a substrate structure having an inductor according to another embodiment of the present invention;

6 to 8 are cross-sectional views for each process for explaining a method of manufacturing a substrate structure having an inductor according to an embodiment of the present invention;

9 is a cross-sectional view illustrating a contact portion of an inductor according to an embodiment of the present invention;

10 is an equivalent circuit diagram of a semiconductor substrate structure having an inductor according to an embodiment of the present invention;

11 is a graph showing a Q factor of an inductor against frequency in accordance with an embodiment of the present invention;

12 is a table comparing and analyzing various characteristics of the staggered inductor and the conventional multilayer inductor of the present invention, and

13 is a plan view illustrating an inductor according to another exemplary embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

100 base member 110 conductive layer

120: first conductive pattern 130: second conductive pattern

140: third challenge pattern

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a substrate structure with an inductor and a method of manufacturing the same.

In recent years, along with the spread and development of portable small electronic devices, portable convenience and high performance of electronic devices have been demanded. Semiconductor devices used in such electronic devices are also required to be small, light, thin and multifunctional.

For this reason, there is a growing demand for modular products and packaged products using small and high density packaging technology. As part of this, a multichip package or a system in package (SiP), in which a semiconductor chip and a passive element are mounted at the same time, has been developed.

Conventionally, a silicon substrate is used as a semiconductor substrate on which packages are mounted. Since the silicon substrate has conductivity as is known, leakage current and induction current may be generated. Accordingly, silicon substrates are not suitable for SiP for radio frequency (RF) circuits such as wireless devices.

In order to solve the problem of the silicon substrate, a ceramic substrate such as a low temperature co-fired ceramic (LTCC) substrate excellent in terms of leakage current and induction current has been proposed.

LTCC substrate has the advantage of good heat transfer and high strength and no warpage. Since the LTCC substrate is composed of multiple ceramic layers, a passive element such as an inductor or a capacitor may be embedded between each ceramic layer.

The inductor formed on the LTCC substrate may be formed of conductive patterns formed in a frame shape having the same size between each ceramic layer.

The inductor embedded in the LTCC substrate is important to secure a high Q factor (Quality Factor) to improve the performance of the electronic device. The Q factor may vary depending on the number of turns of the inductor, the width and thickness of the conductive pattern, the spacing, radius, and shape of the conductive pattern.

This Q factor can be expressed by the following equation.

<Expression>

Q = 2π (Es / EL)

Here, Es represents magnetic energy stored in the net, and EL represents energy lost in every oscillation period. According to the above formula, in order to secure a high Q factor, the coil winding count (ie, the number of conductive patterns stacked) and the larger the thickness and width of the conductive pattern are advantageous so that the magnetic energy stored in the net can be increased. At this time, in the case of the LTCC substrate, the number of ceramic layers to be laminated is limited, so that the Q factor can be secured by adjusting the thickness and width of the conductive pattern.

However, when the thickness and width of the conductive patterns having the same size are increased in order to secure a high Q factor, as shown in FIG. 1, the parasitic capacitance Cj is increased between the upper and lower conductive patterns 20. have. This increase in parasitic capacitance results in a loss of Q factor.

Therefore, there is an urgent need for a substrate structure capable of reducing parasitic capacitance while improving the Q factor of the inductor.

Accordingly, it is an object of the present invention to provide a substrate structure capable of securing a high Q factor.

Another object of the present invention is to provide a substrate structure which can reduce the parasitic capacitance while improving the inductor Q factor.

Still another object of the present invention is to provide a method of manufacturing the above-described substrate structures.

In order to achieve the above object of the present invention, the semiconductor substrate structure of the present invention, the base member, 인덕터 an inductor having a plurality of conductive patterns stacked on the base, and 절연 insulating layer interposed between the conductive patterns, respectively The plurality of conductive patterns may be concentric patterns having a frame shape, and adjacent conductive patterns among the plurality of conductive patterns may be disposed to be shifted so as not to overlap each other.

The inductor may include first to third conductive patterns, and the second conductive pattern may be arranged in a different size from the first conductive pattern. The second conductive pattern may be disposed in a space partitioned by the first conductive pattern. In addition, the second conductive pattern may be disposed outside the first conductive pattern.

The third conductive pattern is formed to have a different size from the second conductive pattern. The third conductive pattern may be disposed to overlap the first conductive pattern, and the third conductive pattern may be located outside the first conductive pattern or may be located in a space partitioned by the second conductive pattern. have.

The insulating layer may be one of a low dielectric film such as spin on glass (SOG), SiOC, SiOG, porous silicon oxide film, undoped silicate glass (USG), and tetrahedral silicate glass (TEOS), or a ceramic layer may be used. have.

The conductive patterns constituting the inductor may have a substantially rectangular frame shape or a substantially ring shape.

The conductive patterns constituting the inductor may be electrically connected by via contacts, and the conductive patterns constituting the inductor may further include contact pads for via contacts.

The base member may further include a ground layer electrically connected to a conductive pattern constituting the inductor.

According to another embodiment of the present invention, a substrate structure includes a base member, a conductive layer disposed on the base member, a first conductive pattern disposed to have a substantially frame shape on the conductive layer, and a first conductive pattern formed on the first conductive pattern. A second conductive pattern disposed on an upper portion of the first insulating layer while being electrically connected to the first conductive pattern, and arranged to have a substantially frame shape in a space partitioned by the first conductive pattern; A second insulating layer disposed over the first insulating layer on which the conductive pattern is formed, and a third conductive layer formed on the second insulating layer while being electrically connected to the second conductive pattern and overlapping the first conductive pattern. Contains a pattern.

A method of manufacturing a substrate structure according to another embodiment of the present invention is as follows. First, a base member having a conductive layer is prepared, and then a first conductive pattern having a substantially frame shape is formed on the base member. A first insulating layer is formed on an upper portion of the base member on which the first conductive pattern is formed, and is electrically connected to the first conductive pattern on the first insulating layer while maintaining the shape of the first conductive pattern, wherein the first conductive pattern is maintained. A second conductive pattern having a different size from the conductive pattern is formed. Thereafter, a second insulating layer is formed on the first insulating layer on which the second conductive pattern is formed, and the second conductive pattern is electrically connected to the second conductive pattern on the second insulating layer, thereby maintaining the formation of the second conductive pattern. And forming a third conductive pattern having a different size from the second conductive pattern.

Between forming the first insulating layer and forming the second conductive pattern, and forming the second insulating layer and forming the third conductive pattern, the lower portion of the insulating layer The method may further include forming a via hole exposing the conductive pattern.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 and 3, the inductor 200 according to the present embodiment includes a plurality of conductive patterns 120, 130, and 140 stacked on the base member 100. These conductive patterns 120, 130 and 140 may be formed in substantially the same frame shape with the window W therein, and the conductive patterns 120, 130 and 140 may be arranged in a concentric manner with different window widths (x1, x2, x3). It can have Preferably, adjacently disposed conductive patterns 120 and 130 and 130 and 140 are disposed to be shifted so as not to overlap each other. When the conductive patterns 120, 130, and 140 are stacked according to this rule, one side edges of the conductive patterns 120, 130, and 140 form a staggered shape. Such a structure will be referred to as &quot; stere type inductor &quot; in this embodiment.

The conductive patterns 120, 130, and 140 may be formed of, for example, a first conductive pattern 120, a second conductive pattern 130, and a third conductive pattern 140, and may be formed of a metal material having excellent conductivity. have.

In the present exemplary embodiment, in order to reduce parasitic capacitance between adjacent conductive patterns, the second pattern 130 is formed to have a different size from the first conductive pattern 120 so as not to overlap with the first conductive pattern 120. The third conductive pattern 140 is also formed to have a different size from the second conductive pattern 130 so as not to overlap with the second conductive pattern 130.

For example, the first conductive pattern 120 may have a substantially rectangular frame shape, and the second conductive pattern 130 may define the first conductive pattern 120 as illustrated in FIGS. 2 and 3. It may be formed so as to be disposed in a space reduced in proportion, that is, the space partitioned by the first conductive pattern 120. In addition, as shown in FIG. 4, the first conductive pattern 120 may be enlarged at a predetermined ratio, that is, the first conductive pattern 120 may be disposed outside the first conductive pattern 120. 130a of FIG. 4 illustrates an enlarged second conductive pattern. In this case, when the size of the second conductive pattern 130 is reduced as described above, the width and thickness of the second conductive pattern 130 may be adjusted so that the overall inductance is not reduced.

In addition, as shown in FIGS. 2 to 4, the third conductive pattern 140 has the same size as the first conductive pattern 120 and overlaps with each other, or as shown in FIG. 5A, the first conductive pattern 140. The pattern 120 may be formed to have a larger size, or as shown in FIG. 5B, may be formed to have a smaller size than the second conductive pattern 130. In this case, when the third conductive pattern 140 is formed differently from the size of the first conductive pattern 120, the size and line width should be determined in consideration of the overall inductance.

Meanwhile, an insulating layer (not shown) is interposed between the first conductive pattern 120, the second conductive pattern 130, and the third conductive pattern 140. The insulating layer may be formed of an insulating film (hereinafter, referred to as a low dielectric film) or a ceramic layer having a low dielectric constant so as to reduce parasitic capacitance between the first, second, and third conductive patterns 120, 130, and 140. As the low dielectric film, for example, spin on glass (SOG), SiOC, SiOG, porous silicon oxide, USG (undoped silicate glass), and TEOS (Tetratehylortho Silicate Glass) may be used. 2 to 5B, the insulating layer is omitted on the assumption that the insulating layer is transparent.

In addition, the first conductive pattern 120, the second conductive pattern 130, and the third conductive pattern 140 are electrically connected to each other. Preferably, each of the first conductive pattern 120 and the second conductive pattern 130, and the second conductive pattern 130 and the third conductive pattern 140 may be connected by a via contact VC. In this case, the second and third conductive patterns 130 and 140 may include contact pads 131 and 141 extending by a predetermined length for the via contact VC. A portion of the contact pads 131 and 141 may extend by a predetermined length in a line that does not deform the shape of the conductive patterns 120, 130 and 140.

In addition, a conductive layer 110 provided with a ground voltage is interposed between the base member 100 and the first conductive pattern 120 to ground the first conductive pattern 120. Of course, a predetermined voltage may be applied to the conductive layer 110 in addition to the ground voltage.

A method of manufacturing a substrate having an inductor having the above-described structure will be described with reference to FIGS. 6 to 8.

With reference to the drawing, the base member 100 is prepared. The base member 100 may be an insulating member such as a ceramic layer. A conductive layer 110 to be provided as a ground is formed on the base member 100. After forming the coil metal layer on the ground conductive layer 110, the coil metal layer is patterned by a known photolithography process and an etching process to form a first conductive pattern 120. The first conductive pattern 120 may have a substantially frame shape as described above.

Referring to FIG. 7, after forming the first insulating layer 125 on the conductive layer 110 on which the first conductive pattern 120 is formed, a via hole may be exposed to expose a predetermined portion of the first conductive pattern 120. (Not shown). A coil metal layer is formed on the first insulating layer 125 where the via hole is formed to fill the via hole, and a second portion of the coil metal layer is patterned to form a second conductive pattern 130. In this case, the metal layer filled in the via hole is a via contact VC electrically connecting the first conductive pattern 120 and the second conductive pattern 130. The second conductive pattern 130 maintains the shape of the first conductive pattern 130, but may be formed to have a smaller size than the first conductive pattern 120, as shown in FIG. 7, and the first conductive pattern 120. It may also be formed in a size larger than).

Referring to FIG. 8, a second insulating layer 135 is formed on the first insulating layer 125 on which the second conductive pattern 120 is formed. A via hole (not shown) is formed in the third insulating layer 135 to expose a predetermined portion of the second conductive pattern 120. A coil metal layer is formed on the third insulating layer 135 to fill the via hole, and then a predetermined portion is patterned to form the third conductive pattern 140. The third conductive pattern 140 maintains the substantially shape of the second conductive pattern 130 but is formed in a different size from the second conductive pattern 130. For example, the third conductive pattern 140 may be formed to overlap the first conductive pattern 120. Thereafter, the third insulating layer 145 and the cap insulating layer 150 are sequentially stacked on the third conductive pattern 140 to complete the substrate structure.

Here, as the above-described insulating layers 110, 125, 135, 145, and 150 to insulate the conductive patterns 120, 130, and 140, a low dielectric layer or a ceramic layer may be used.

9 is a cross-sectional view illustrating an electrical connection relationship between the first conductive patterns and the third conductive patterns 120, 130, and 140. The first conductive pattern 120, the second conductive pattern 130, the second conductive pattern 130, and the third conductive pattern 140 are connected by the via contact VC, respectively, and the via contact VC is In order to be formed, the second conductive pattern 130 and the third conductive pattern 140 may include contact pads 131 and 141 extending by a predetermined length, respectively.

As shown in FIG. 8, the semiconductor substrate structure including the inductor of the present invention has a structure between the first conductive pattern 120 and the second conductive pattern 130, and the second conductive pattern 130 and the third conductive pattern. Since there is no overlapping portion between the patterns 140, parasitic capacitors between the conductive patterns 120, 130, and 140 are hardly generated. In some cases, the first conductive pattern 120 and the third conductive pattern 140 may overlap, but there are two insulating layers between the first conductive pattern 120 and the third conductive pattern 140. 125 and 135 and sufficiently spaced apart from each other, and the insulating layers 125 and 135 have a very low dielectric constant, such as a low dielectric film or a ceramic layer, and thus are formed between the first conductive pattern 120 and the third conductive pattern 140. Parasitic capacitance can be almost neglected. Therefore, the parasitic capacitance between the first, second, and third conductive patterns 120, 130, and 140 constituting the inductor can be significantly reduced.

Figure 10 shows an equivalent circuit of a semiconductor substrate structure incorporating the inductor of the present invention. By forming the inductor Ls, parasitic resistance Rs, parasitic capacitor Cs, and ground capacitor Cg may be incidentally generated. At this time, the parasitic resistance (Rs) is a resistance derived from the length and thickness of each conductive pattern (120,130,140), the parasitic capacitor (Cs) is a parasitic capacitor generated incidentally between the conductive patterns (120,130,140), the ground capacitor (Cg) Is a parasitic capacitor generated between the first conductive pattern 120 and the ground layer 110.

In an equivalent circuit, the inductor Ls is connected in series with the parasitic resistor Rs and connected in parallel with the parasitic capacitor Cs and the ground capacitor Cg. Accordingly, RLC parallel resonance may occur between the inductor Ls, the resistor Rs, and the parasitic capacitor Cs. At this time, as is known, the RLC resonance frequency is a factor that can represent the Q factor of the inductor, and the larger the RLC resonant frequency, the better the Q factor.

When the conductive patterns 120, 130, and 140 constituting the inductor Ls are staggered as in this embodiment, the parasitic capacitance Cs is greatly reduced, thereby increasing the RLC resonant frequency. As a result, a high Q factor can be secured.

11 is a graph showing a Q factor of an inductor against frequency according to an embodiment of the present invention. 11 is a case where a stacked inductor according to the prior art is used, and ⓑ is a case where a staggered inductor according to the present embodiment is used.

Referring to FIG. 11, when the staggered inductor is used as in the present invention, the frequency band is 0.6 GHZ wider than the stacked inductor, and the Q factor and the resonant frequency according to the frequency are also superior to those of the related art.

12 is a table comparing and analyzing various characteristics of the staggered inductor and the conventional multilayer inductor of the present invention. According to Fig. 12, the staggered inductor of this embodiment is excellent in terms of the parasitic capacitor Cs, the resonance frequency fres, the maximum frequency f max and the maximum Q factor Q max which determine the performance of the inductor. It became.

The present invention is not limited to the above embodiment.

In the present embodiment, although the first to third conductive patterns 120, 130, and 140 are used as the conductive patterns constituting the inductor, the present invention is not limited thereto. Or if it forms in three layers or less, it is a matter of course that all are included in this invention.

In addition, in the present exemplary embodiment, the first to third conductive patterns 120, 130, and 140 constituting the inductor are formed in a rectangular frame shape, but may be formed in a ring shape as shown in FIG. 13. In this case, the contact pad portion is omitted for convenience of description.

In addition, in the present embodiment, the first to third conductive patterns 120, 130 and 140 can be used as metal films having high conductivity. In this case, when a metal film difficult to be etched such as copper is used as the first to third conductive patterns 120, 130 and 140, the side surfaces of the first to third conductive patterns 120, 130 and 140 maintain a staggered shape as described above. It will be apparent to those skilled in the art that they can be formed in the form of damascene.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

As described in detail above, according to the present invention, the multilayer conductive patterns constituting the inductor are arranged in a staggered form, that is, adjacent multilayer conductive patterns do not overlap each other. Accordingly, the parasitic capacitance between the multilayer conductive patterns constituting the inductor can be reduced, thereby improving the Q factor of the inductor.

Claims (21)

A base member having a conductive layer; An inductor having a plurality of conductive patterns stacked on the base member; And An insulating layer interposed between the conductive patterns, The plurality of conductive patterns are concentric patterns having a frame shape, Adjacent conductive patterns among the plurality of conductive patterns are disposed to be shifted so as not to overlap each other, And the conductive layer provides a predetermined signal to one selected from the plurality of conductive patterns. The method of claim 1, The inductor comprises at least first, second and third conductive patterns sequentially stacked, And the second conductive pattern is disposed in a space partitioned by the first conductive pattern. The method of claim 1, The inductor comprises at least first, second and third conductive patterns sequentially stacked, The second conductive pattern is disposed on the outer periphery of the first conductive pattern. The method of claim 2 or 3, And the third conductive pattern is disposed to overlap with the first conductive pattern. The method of claim 2 or 3, The third conductive pattern is disposed to have a different size than the first conductive pattern. The method of claim 1, The insulating layer is a substrate structure of one of a low dielectric film, such as spin on glass (SOG), SiOC, SiOG, porous silicon oxide film, undoped silicate glass (USG), and Teteratehylortho Silicate Glass (TEOS). The method of claim 1, The insulating layer is a substrate structure. The method of claim 1, The plurality of conductive patterns constituting the inductor has a substantially rectangular frame shape. The method of claim 1, And a plurality of conductive patterns constituting the inductor have a substantially ring shape. The method of claim 2 or 3, And a plurality of conductive patterns constituting the inductor are electrically connected to each other by via contacts. The substrate structure of claim 10, wherein the plurality of conductive patterns constituting the inductor further comprises a contact pad extending for the via contact. delete A base member; A conductive layer disposed on the base member; A first conductive pattern disposed on the conductive layer to have a substantially frame shape; A first insulating layer formed on the first conductive pattern; A second conductive pattern electrically connected to the first conductive pattern and disposed on the first insulating layer and disposed to have a substantially frame shape in a space partitioned by the first conductive pattern; A second insulating layer disposed on the first insulating layer on which the second conductive pattern is formed; And And a third conductive pattern formed on the second insulating layer while being electrically connected to the second conductive pattern and overlapping the first conductive pattern. The method of claim 13, The substrate structure further comprises an insulating layer formed on the second insulating layer formed with the third conductive pattern. The method of claim 13, And the first conductive pattern and the second conductive pattern, and the second conductive pattern and the third conductive pattern are connected by via contacts, respectively. The method of claim 13, The insulating layer is a substrate structure of a spin on glass (SOG), SiOC, SiOG, porous silicon oxide film, undoped silicate glass (USG), Teteratehylortho Silicate Glass (TEOS) or a ceramic layer. The method of claim 13, The ground layer is applied with a ground voltage, And the conductive layer and the first conductive pattern are electrically connected to each other. The method of claim 13, The first to third conductive patterns are concentric patterns. Providing a base member having a conductive layer; Forming a first conductive pattern having a substantially frame shape on the base member; Forming a first insulating layer on the base member on which the first conductive pattern is formed; Forming a second conductive pattern on the first insulating layer, the second conductive pattern having a different size from the first conductive pattern while maintaining a shape of the first conductive pattern while being electrically connected to the first conductive pattern; And Forming a second insulating layer on the first insulating layer on which the second conductive pattern is formed; Forming a third conductive pattern on the second insulating layer, the third conductive pattern having a different size from the second conductive pattern while maintaining the shape of the second conductive pattern while being electrically connected to the second conductive pattern. A method for producing a substrate structure. The method of claim 19, Between forming the first insulating layer and forming the second conductive pattern, and between forming the second insulating layer and forming the third conductive pattern, And forming a via hole exposing a lower conductive pattern in the insulating layer. The method of claim 19, Forming the third conductive pattern, And forming a third conductive pattern to overlap the first conductive pattern.

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