KR100632464B1 - Integrated circuit including passive device shield structure and method of manufacturing the same - Google Patents

Abstract

Integrated circuit devices include semiconductor substrates and flux line generation passive devices on the semiconductor substrate. The dummy gate structure is arranged on the semiconductor substrate in the passive element lower region. The dummy gate includes a plurality of segments, each segment including a portion extending in the first direction and a portion extending in the second direction, and the portion extending in the second direction is one end of the portion extending in the first direction. Each segment extending from the first direction and extending in the first direction extends at substantially the same angle in the second direction and is spaced apart from each other at predetermined intervals.

Passive Components, Flux Lines, Shields

Description

Integrated circuit devices including passive device shielding structures and method of forming the same}

1A is a perspective view illustrating a magnetic field and an eddy current in an integrated circuit device.

1B is a perspective view illustrating a magnetic field and an eddy current in an integrated circuit device.

2 is a cross-sectional view illustrating an integrated circuit device including a passive device shield structure according to some embodiments of the present invention.

3 is a partial perspective view of FIG. 2.

4 is a plan view of the device of FIG.

5 is a plan view illustrating a conductive contact with a ground in a passive device shield structure according to some embodiments of the present invention.

6 is a graph illustrating a result of measuring a Q coefficient of an integrated circuit device according to example embodiments.

7 is a cross-sectional view illustrating an integrated circuit including a passive device shield structure according to another embodiment of the present invention.

8 is a top plan view of FIG. 7.

9 is a cross-sectional view of an integrated circuit device including a passive device shield structure according to still another embodiment of the present invention.

10 is a cross-sectional view of an integrated circuit device including a passive device shield structure according to still another embodiment of the present invention.

11 is a flow chart illustrating a fabrication stage of an integrated circuit device including a passive device shield structure in accordance with some embodiments of the present invention.

12 is a flowchart illustrating a fabrication process of an integrated circuit device including a passive device shield structure according to another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: semiconductor substrate 110: device isolation region

111: dummy gate structure 130: conductive region

140: interlayer insulating film 150: inductor

160, 175: flux line 170a, 170b: eddy current

200: challenge screen

TECHNICAL FIELD The present invention relates to integrated circuit devices, and more particularly, to an integrated circuit device having a passive device and a method of manufacturing the same.

Different electronic components are formed together in one integrated circuit device instead of in separate circuits, reducing cost, size, and / or package complexity. Such integrated circuit devices are referred to as system on chip (SOC) devices. Various commercial products including such integrated circuit devices, such as wireless communication devices, operate in the radio frequency (RF) band. In the case of such devices, passive devices such as inductors and capacitors are important elements of analog circuits and / or RF circuits. The performance of the inductor is mainly expressed by the Q (Quality) coefficient. The Q coefficient is represented by the following equation.

Where ω represents an angular frequency.

The inductor generates a magnetic field during operation. Eddy current or the like is generated by the generation of a magnetic field passing through the integrated circuit element. As shown in FIGS. 1A and 1B, the eddy current is determined by the direction of the magnetic field 60 when the B field 60 is formed by the inductor 50 formed on the interlayer insulating film 40 on the substrate 10. It is a circular current 70 occurring in the vertical substrate 10. The eddy current 70 dissipates power in the substrate 10 and takes energy from the inductor 50 to lower the Q coefficient. In addition, due to the eddy current 70 flowing through the surface of the substrate 10, substrate noise coupling occurs between adjacent inductors 50 or between the inductor 50 and another element (eg, a passive element such as a capacitor or an active element). In addition, parasitic capacitance is generated between the shield pattern 20 formed in the interlayer insulating film 40 and the inductor 50.

It is an object of the present invention to provide an integrated circuit device including a passive device shield structure.

Another object of the present invention is to provide a method of manufacturing an integrated circuit device including the passive device shield structure.

Technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

The integrated circuit device according to the embodiments of the present invention for achieving the technical problem is a semiconductor substrate, a flux line generation passive element formed on the semiconductor substrate, and a dummy gate structure arranged on the semiconductor substrate under the passive element The dummy gate may include a plurality of segments, each segment including a portion extending in a first direction and a portion extending in a second direction, and the portion extending in the second direction may extend in the first direction. Extending at a predetermined angle from one end of the portion, wherein each segment extending in the first direction extends in the second direction in the first direction and each segment extends at substantially the same angle in the second direction and is mutually The dummy gate structure may be arranged to be spaced apart by a predetermined interval.

In the integrated circuit device according to other embodiments of the present invention, the dummy gate structure is formed to block flux lines generated by the passive device from penetrating into the semiconductor substrate. The passive element is an inductor, at least half of the segments extending in a direction perpendicular to the inductor placed thereon. The passive element may be a capacitor. The dummy gate structure may include a plurality of sets of segments arranged in a symmetrical pattern.

The integrated circuit device according to still another embodiment of the present invention further includes a plurality of device isolation regions under the passive device, and the dummy gate structure segments are formed on the device isolation region to define a first shield. The semiconductor device may further include a plurality of conductive regions formed between the device isolation regions to define a complementary second shield. The conductive region may be a metal silicide pattern on the semiconductor substrate. The semiconductor device may further include an interlayer insulating layer covering the dummy gate structure and the plurality of conductive regions and having the passive element disposed thereon.

In accordance with still another aspect of the present invention, an integrated circuit device may be formed to extend in the interlayer insulating layer around the passive device, and define a boundary surrounding the passive device, and the flux line generated by the passive device may be the boundary. It may further include a conductive screen formed to limit the penetration beyond. The conductive screen may include a plurality of conductive columns formed to extend along the boundary and spaced apart from each other into the interlayer insulating layer, and each conductive column may include a plurality of conductive elements spaced apart from each other and electrically connected to each other. A flux line formed extending from the interlayer insulating film around the passive element, defining a second boundary around the passive element, spaced apart from the conductive screen, and beyond the second boundary by the passive element It may further comprise a complementary conductive screen formed to limit penetration.

In an integrated circuit device according to still another embodiment of the present invention, the passive device lower portion includes a passive device region of an integrated circuit device, and the integrated circuit device is disposed on the semiconductor substrate adjacent to the outside of the boundary of the passive device region. The display device may further include an active device region, and the active device region may include an active device gate electrode formed when the plurality of dummy gate electrodes are formed. In other embodiments, the active device gate electrode may be formed on the same layer as the dummy gate structure.

In the integrated circuit device according to still another embodiment of the present invention, the dummy gate structure may include a gate insulating film on the semiconductor substrate and a conductive gate electrode on the gate insulating film. The dummy gate structure may further include a silicide layer on the gate electrode and insulating sidewalls of sidewalls of the gate insulating layer, the gate electrode, and the silicide layer.

In an integrated circuit device according to still another embodiment of the present invention, the interlayer insulating film may include first and second interlayer insulating films, and the first interlayer insulating film may be formed on the dummy gate electrode, and the plurality of conductive regions may be formed. The interlayer insulating layer may be formed on a first interlayer insulating layer, and the second interlayer insulating layer may be formed on the plurality of conductive regions. The semiconductor device may further include a metal contact connected to the dummy gate structure in a central region of the lower portion of the passive element to connect the dummy gate structure to ground.

In accordance with still another aspect of the present invention, an integrated circuit device includes a semiconductor substrate, a flux line generating passive element on the semiconductor substrate, and a flux line arranged on the semiconductor substrate below the passive element and generated by the passive element. The dummy gate structure may be arranged to block penetration of the semiconductor substrate, and a metal contact may be connected to the dummy gate structure in a central region of the lower portion of the passive element to connect the dummy gate structure to ground.

In accordance with still another aspect of the present disclosure, an integrated circuit device includes a semiconductor substrate, a first interlayer insulating layer on the semiconductor substrate, a second interlayer insulating layer on the first interlayer insulating layer, a third interlayer insulating layer on the second interlayer insulating layer, and the first interlayer insulating layer on the second interlayer insulating layer. A flux line generating passive element on a three interlayer insulating film, a first grounded conductive shield pattern formed on the first interlayer insulating film in the lower area of the passive element, and a second ground formed on the second interlayer insulating film in the lower area of the passive element It may comprise a conductive shield pattern. The first and second grounded conductive shield patterns may be metal patterns.

In accordance with still another aspect of the present invention, an integrated circuit device includes a semiconductor substrate, a flux line generating passive element on the semiconductor substrate, and a flux line generated by the passive element formed in the semiconductor substrate below the passive element. A plurality of device isolation regions having a plurality of segments defining a first shield pattern that prevents penetration into a substrate, and the flux lines formed between the plurality of device isolation regions and generated by the passive elements are the semiconductor It can include a plurality of conductive elements defining a complementary second shield pattern that prevents penetration into the substrate. The plurality of conductive elements may be a dummy gate structure or a metal silicide pattern.

In accordance with still another aspect of the present invention, an integrated circuit device includes a semiconductor substrate, a flux line generating capacitor on the semiconductor substrate, and a flux line arranged on the semiconductor substrate in the capacitor subregion and generated by the capacitor. It may include a dummy gate structure to block penetration into the substrate.

According to another aspect of the present invention, there is provided a method of manufacturing an integrated circuit device, including forming an active device region and a passive device region in a semiconductor substrate, and forming a gate electrode of the active device on the active device region. Simultaneously forming a dummy gate electrode in a passive device region, forming a first interlayer insulating film on the gate electrode and the dummy gate electrode, and penetrating the first interlayer insulating film to be in contact with a center of the dummy gate electrode Forming a metal layer pattern in contact with the metal plug to connect the dummy gate electrode to ground, forming a second interlayer insulating layer on the metal layer pattern, and forming the second interlayer insulating layer on the dummy gate electrode Forming a flux line generation passive element on the second interlayer insulating film It can be included.

According to another aspect of the present invention, there is provided a method of fabricating an integrated circuit device, including forming an active device region and a passive device region in a semiconductor substrate, and forming a gate electrode of the active device in the active device region in the passive device region. Simultaneously forming a dummy gate electrode structure in the dummy gate electrode structure, wherein the dummy gate electrode structure includes a plurality of segments, each segment including a portion extending in a first direction and a portion extending in a second direction, and the second direction Extends at a predetermined angle from one end of the portion extending in the first direction, and the segments extending in the first direction are each segment extending in the second direction in the first direction. Dummy gates that extend at substantially the same angle in two directions and are spaced apart from each other by a predetermined interval Forming a structure, forming an interlayer insulating film on the gate electrode and the dummy gate electrode structure, and generating a flux line generating passive element on the interlayer insulating film on the dummy gate electrode structure. .

In accordance with still another aspect of the present invention, an integrated circuit device includes a semiconductor substrate, a flux line generation passive element on the semiconductor substrate, and a peripheral portion of the passive element and between the passive element and the semiconductor substrate. A three-dimensional magnetic field shield arranged to block the flux line from the passive element from penetrating into the semiconductor substrate and from penetrating the periphery surrounding the passive element, the flux line from the passive element. It may include.

In accordance with still another aspect of the present invention, an integrated circuit device includes a semiconductor substrate, a flux line generation passive device on the semiconductor substrate, and a plurality of dummy arrays arranged on the semiconductor substrate under the passive device. As a gate structure, each dummy gate structure may include a plurality of dummy gate structures arranged to be spaced apart from each other and blocking flux lines generated by the passive element from penetrating the semiconductor substrate. In addition, an interlayer insulating film on the plurality of dummy gate structures, a metal film connected to ground on the interlayer insulating film, and a plurality of dummy gate structures extending from the metal film to connect the plurality of dummy gate structures to the ground through the metal film. It may include a plurality of conductive contacts.

In accordance with still another aspect of the present invention, an integrated circuit device includes a semiconductor substrate, a first interlayer insulating layer on the semiconductor substrate, a second interlayer insulating layer on the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer. A third interlayer dielectric layer, a flux line generation passive element on the third interlayer dielectric layer, a first metal conductive shield pattern on the first interlayer dielectric layer in the passive element lower region, and a second interlayer dielectric layer on the passive element lower region It may include a 2 metal conductive shield pattern.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments make the disclosure of the present invention complete, and the scope of the invention to those skilled in the art. It is provided for the purpose of full disclosure, and the invention is only defined by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

When an element or layer is referred to as another element or layer “on”, “connected to” or “coupled to” it is directly connected to another element, directly on another element, or It includes both the case where it is coupled or through another layer or other element in between. On the other hand, when a device is referred to as "directly on", "directly connected to" or "directly coupled to", it means that there is no intervening device or layer in between. Like reference numerals refer to like elements throughout. "And / or" includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections are not limited by these terms. Of course. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, the first element, the first component, the first region, the first layer, or the first section, which are mentioned below, are within the technical spirit of the present invention. Of course, it may also be a second section.

The spatially relative terms "below", "beneath", "lower", "above", "upper" and the like are shown as one element as shown in the drawings. Or may be used to easily describe the correlation of components with other elements or components, and spatially relative terms may include different orientations of the element in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figures, a device described as "below" or "beneath" of another device is "above" of the other device. Thus, the exemplary term "below" may include both directions below and above.The device may be oriented in other directions as well, so spatially relative terms may be interpreted according to orientation. have.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms used in the present specification (including technical and scientific terms) may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

Embodiments described herein will be described with reference to cross-sectional views, which are ideal schematic diagrams of the invention. Accordingly, the shape of the exemplary diagram may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched regions shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and not to limit the scope of the invention.

Several embodiments of the present invention are described below with reference to FIGS. 2-5. 2 is a cross-sectional view of an integrated circuit device (semiconductor device) including a passive device shield in accordance with some embodiments of the present invention. As shown in FIG. 2, the integrated circuit board 100 includes a trench device isolation region 110 in which a dummy gate structure 111 is arranged thereon. The dummy gate structure 111 shown in FIG. 2 includes a gate insulating film 112 and a conductive gate electrode 115 formed of a polysilicon layer 115 and a silicide layer 118 thereon. The dummy gate structure 111 of FIG. 2 includes an insulating sidewall S formed on sidewalls of the gate insulating layer 112, the polysilicon layer 115, and the silicide layer 118.

The dummy gate structure 111 is arranged on the integrated circuit board 100 in the passive region underneath, which is illustrated by the inductor 150, as shown in FIG. The dummy gate structure 111 is formed to block the flux line 160 generated by the inductor 150 from penetrating the integrated circuit board 100 to define the first shield pattern. As schematically shown in FIG. 2, the flux line 160 generated by the magnetic field of the inductor 150 may cause eddy currents 170A and 170B that may degrade the performance of the inductor 150. It may flow to adjacent devices formed in other areas of the integrated circuit board 100. Eddy currents 170A, 170B may be reduced or further eliminated by a shield structure provided in accordance with various embodiments of the present invention.

A plurality of conductive regions 130 are provided between the device isolation regions 110. The conductive region 130 is formed to define a complementary second shield. For example, the conductive region 130 may be metal silicide. The metal in the metal silicide may be cobalt, nickel, tungsten and / or titanium. As shown in the embodiment of FIG. 2, the interlayer insulating layer 140 is disposed over the entire surface of the integrated circuit board 100 to cover the dummy gate structure 111 and the conductive region 130. The inductor 150 is formed on the upper surface of the interlayer insulating layer 140.

As shown in the embodiment of FIG. 2, a conductive screen 200 is positioned within the interlayer dielectric region 140 around the inductor 150 to define the boundary of the inductor 150. The conductive screen 200 is formed to restrict the flux line 175 generated by the inductor 150 from penetrating outside the conductive screen 200. The conductive screen 200 may be formed of multilayer metal patterns M1 to Mn formed in the interlayer insulating layer 140 formed on the integrated circuit board 100. Accordingly, the interlayer insulating layer 140 illustrated in FIG. 2 may be a multilayer insulating layer having metal patterns M1 to Mn interposed therebetween. The upper metal layer Mn defining the top layer of the conductive screen 200 may be formed of the same metal as the inductor 150.

As shown in FIG. 3, which is a perspective view of FIG. 2, the conductive screen 200 may include a plurality of columns of conductive elements formed extending within the interlayer insulating film 140 along the boundary. The columns may be spaced apart from each other, and each column may include a plurality of conductive elements M1 to Mn spaced apart from each other. As shown in FIGS. 2 and 3, the plurality of conductive elements constituting the conductive column may be connected by a metal contact MC. The conductive screen 200 is coupled and grounded in contact with the conductive region 130 defining the complementary shield pattern 130. The conductive screen 200 used in combination with shield pattern 120 and complementary shield pattern 130 defines a first boundary of inductor 150.

4 is a top view of the device shown in FIGS. 2 and 3. As shown in FIG. 4, in some embodiments of the present invention, a complementary conductive screen 210 may be further provided. The complementary conductive screen 210 defines a second boundary within the interlayer insulating film around the inductor 150 that is spaced apart from the conductive screen 200 by a predetermined distance and surrounds the inductor 150. As shown in FIG. 4, the complementary conductive screen 210 is arranged in an offset form with the conductive screen 200. Complementary conductive screen 210 is formed to limit the flux lines generated by inductor 150 from penetrating outside the second boundary or affecting other devices formed outside the second boundary.

4 illustrates various aspects of a dummy gate structure 111 pattern. In particular, as shown in the top view of FIG. 4, the dummy gate structure 111 includes a plurality of segments 111i-111n. Each of the segments 111i to 111n includes a portion 111a extending in the first direction and a portion 111b extending in the second direction to form a predetermined angle from the end of the portion 111a extending in the first direction. In addition, as shown in FIG. 4, the portions 111a and 111b in the respective segments 111i to 111n are substantially extended at the same angle and spaced apart so that the conductive regions 130 may be disposed therebetween. Are arranged. The relative arrangement of the segments 111i-111n with respect to the inductor 150 is shown in a direction substantially perpendicular to the inductor 150 where at least half of each of the segments 111i-111n lies thereon, as shown. Extends. Such a vertical arrangement may increase the shielding effect by the shields 111 and 130.

In addition, as shown in FIG. 4, the dummy gate structure may include a plurality of sets of segments 111i to 111n arranged in a symmetrical pattern. As shown in FIG. 4, four set patterns are arranged in each quarter region below the inductor 150 and are arranged symmetrically in each quarter region.

As described above, according to an embodiment of the present invention, a plurality of dummy gate structures are arranged on an integrated circuit formed in a passive element lower region such as the inductor 150, and the flux line generated by the inductor 150 is a semiconductor substrate. Arranged away from each other to prevent penetration into 100.

The dummy gate structure and conductive screen 200 defining the shield, and in some embodiments, the complementary shield pattern 130 and the complementary conductive screen 210 are formed around the inductor 150 and the inductor 150 and the substrate 100. It is possible to provide a three-dimensional electromagnetic shield arranged in between. The electromagnetic shield prevents the flux line from the inductor 150 from penetrating into the semiconductor substrate 100 and the flux line from the inductor 150 from penetrating the boundary around the inductor 150 to penetrate the outside. Can be. In addition, as described below with reference to FIG. 5, a metal contact connects the dummy gate structure 111 to the ground in the center area under the inductor 150.

5 is a top view illustrating a conductive contact arrangement of a grounded device shield structure according to some embodiments of the present invention. FIG. 5 is an enlarged top view of the central region C of FIG. 4. As shown in FIG. 5, a centrally located contact is provided to a dummy gate 111 defining a first shield pattern through a centrally located metal contact 505, and a predetermined angle with the metal contact 500 is provided. Connection lines 510 form a central contact for the conductive region 130. Connection lines 510 having a predetermined angle in the form of an offset are provided to connect the dummy gates 111 to each contact pad 505. Similarly, each shield structure may be connected to ground through a common contact point in the central region rather than in a separate structure.

The layout of the metal contacts in the center allows the best ground contact to be placed in the region or the center region where the field strength of the flux line generated from the passive element such as the inductor 150 is greatest. The connecting lines 510 having a predetermined angle are arranged at predetermined intervals from each other to form a symmetrical arrangement, as shown in FIG. 4, to define each conductive region 130 defining a complementary shield pattern therebetween. Improved or more effective ground contact can be made to each segment of the dummy gate structure 111 to which it is placed. Improved shield performance can be obtained by connecting all dummy gate structure 111 segments and / or all conductive regions 130 to ground and arranging connections to ground in the center. Accordingly, the metal contacts 500 and 505 are connected to the segments and / or the conductive regions 130 of the dummy gate structure 111 in the center region C under the inductor 150 to be connected to the dummy gate structure 111. Segments and / or conductive regions 130 are connected to ground. A metal film or other conductive film connected to ground may be placed on the dummy gate structure 111 and the conductive regions 130, and a plurality of conductive contacts may be placed from the metal film to the dummy gate structure 111 and / or conductive regions. 130 and / or metal contact regions 500 and 505 to connect them to ground through the metal film.

6 is a graph illustrating a result of measuring a Q coefficient of an integrated circuit device according to some embodiments of the present disclosure described with reference to FIGS. 2 to 5. The graph ① of FIG. 6 shows the Q coefficient for each frequency measured for the embodiments illustrated in FIGS. 2-5, and the graph ② shows the Q coefficient for each frequency measured for the conventional structure. Measurement of the Q factor is to measure the Q factor for the 0.5GHz to 40.5 GHz frequency range by using a network analyzer ^{(Network Analyzer) 8510C ® (Agilent}社). As shown in FIG. 6, it can be seen that according to the embodiments of the present invention, the Q factor is increased by about 14% compared to the conventional case.

Other embodiments of the invention are shown in FIG. As described with reference to FIG. 2, the embodiments illustrated in FIG. 7 provide a first shield defined by a dummy gate structure (pattern) 111 placed on the device isolation region 110 in the semiconductor substrate 100. Include. The dummy gate structure 111 illustrated in FIG. 7 includes a gate insulating film 112 and a gate insulating film 112 formed on the semiconductor substrate 100, and more particularly, on the isolation region 110 in the semiconductor substrate 100. And a conductive gate electrode comprising a polysilicon layer 115 and a silicide layer 118 on. Insulating sidewall spacers S may be formed on sidewalls of the gate insulating layer 112, the polysilicon gate electrode layer 115, and the silicide layer 118. In addition, as described with reference to FIG. 2, conductive regions 130 are formed between the device isolation regions 110 to define a complementary second shield. The dummy gate electrode structure 11 and the conductive regions 130 suppress or eliminate the flow of eddy currents such as the eddy currents 170a and 170b as shown in FIG. 7.

In the embodiments shown in FIG. 7, the passive element generating the flux line is a capacitor 340. Capacitor 340 includes a lower electrode 310, a dielectric 320, and an upper electrode 330 on the dielectric 320. The capacitor 340 is disposed on the interlayer insulating layer 140 on the semiconductor substrate 100 including the dummy gate structure 111 and the conductive regions 130. Although not shown in FIG. 7, the conductive screen 200 and / or the complementary conductive screen 210 may be applied to the embodiments shown in FIG. 7.

7 also illustrates an integrated circuit device comprising a substrate active device region remote from the passive electronic device 340. In particular, the lower region of the capacitor 340, which is a passive element, is the passive element region, and the integrated circuit element is the first and / or second shield and / or to the right region of FIG. 7, adjacent to the passive element region that includes the capacitor 340. FIG. It may further comprise an active device region present outside of the boundary defined by the conductive screen (s) in combination therewith. As shown in FIG. 7, the active device region may include an active device gate electrode formed while forming the dummy gate structure 111. As illustrated in FIG. 7, the active device gate electrode 180 may be formed of the same layer as the dummy gate electrode structure 111. In addition, although the active device region including the active device gate electrode 180 is not illustrated in FIG. 2, the active device region may be applied to the embodiment illustrated in FIG. 2.

FIG. 8 is a top view of the device shown in FIG. 7. As shown in FIG. 8, the dummy gate structure 111 and the conductive regions 130 may be arranged in the lower region of the capacitor 340 similarly as described with reference to FIG. 4. Although conductive screen 200 and complementary conductive screen 210 are not shown in FIGS. 7 and 8, of course, they may be included.

Still other embodiments of the present invention will be described with reference to FIG. 9. As shown in FIG. 9, a shield pattern made of the dummy gate structure 930 is arranged on the semiconductor substrate 100 in the region below the inductor 150 made of the passive element, for example, the metal layer Mn. The dummy gate structure 930 includes a polysilicon layer 115, a silicide layer 118, and sidewall spacers. The interlayer insulating layer 140 includes a first interlayer insulating layer 140a formed on the dummy gate structure 930. A plurality of conductive regions 920 defining the second shield pattern are formed on the first interlayer insulating layer 140a. The second interlayer insulating layer 140b is formed on the first interlayer insulating layer 140a and the conductive regions 920. An inductor 150 is formed on the second interlayer insulating film 140b. As shown in FIG. 9, the conductive regions 920 are disposed between the dummy gate structure 930 to define a complementary shield pattern disposed under the inductor 150. As described in the previous embodiments, the complementary shield patterns 920 and 930 are respectively grounded.

10 is a cross-sectional view of an integrated circuit device including a passive device shield according to still another embodiment of the present invention. As shown in FIG. 10, a first interlayer insulating layer 140a is formed on the semiconductor substrate 100. The second interlayer insulating layer 140b is formed on the first interlayer insulating layer 140a, and the third interlayer insulating layer 140c is formed on the second interlayer insulating layer 140b. The first to third interlayer insulating layers 140a, 140b, and 140c constitute the interlayer insulating layer 140.

A passive element for generating the flux line illustrated by the inductor 150 is formed on the third interlayer insulating film 140c. A first grounded conductive shield pattern 1030 is formed on the first interlayer insulating layer 140a in the lower region of the inductor 150. A second grounded conductive shield pattern 1020 is formed on the second interlayer insulating layer 140b in the lower region of the inductor 150. Each conductive shield pattern 1020 and 1030 are complementarily patterned with each other. As illustrated in FIG. 10, the shield patterns 1020 and 1030 may be formed of stacked metal layers Mn-k and Mn− (k + 1). For example, the Mn− (k + 1) layer may be a first metal film that functions as a connection wiring in an adjacent active element region of the integrated circuit device. Similarly, Mn-k layers can be used as interconnects in adjacent active device regions of integrated circuit devices.

Each of the metal layers Mn-k and Mn- (k + 1) may be formed in the same layer at the same time as the formation of the metal conductive pattern used in the active element region. Accordingly, the metal film defining the shield structure in FIG. 10 may be formed together in the middle of the manufacturing process of the integrated circuit device, similar to the dummy gate structure mentioned above. Each of the first and second grounded conductive shields 1020 and 1030 may be the aforementioned metal film, which may be grounded at the center of the lower region of the passive element.

Hereinafter, another embodiment of the present invention will be described with reference to FIG. 2. Although FIG. 2 was used to describe embodiments including a conductive pattern defining a shield that is complementary to the dummy gate structure under the inductor 150, in another embodiment of the present invention, the dummy gate structure ( The device isolation region 110 may be formed to prevent the flux line generated by the passive device such as the inductor 150 from penetrating the semiconductor substrate 100 without using the 111. In some embodiments using the device isolation region 110 without the dummy gate structure 111, a plurality of conductive regions 130 are formed between the device isolation regions 110 to form a flux line generated by the inductor 150. The second shield pattern may be defined to prevent penetration into the semiconductor substrate 100. In some embodiments, the dummy gate structure 111 may be formed between the isolation regions 110 in which the conductive regions 130 are located in FIG. 2. Thus, in other embodiments of the present invention, the device isolation region 110 may be used as a complementary shield pattern in combination with the conductive regions 130 or the dummy gate structure 111.

A method of manufacturing an integrated circuit device according to various embodiments of the present disclosure will be described with reference to the exemplary flowchart of FIG. 11.

First, an active device region and a passive device region are formed on a semiconductor substrate (1100). A gate electrode of the active element is formed in the active element region, and at the same time, a dummy gate electrode is formed in the passive element region (1105). The first interlayer insulating layer is formed on the gate electrode and the dummy gate electrode (1110). A metal plug penetrating through the first interlayer insulating layer is formed in contact with the center region of the dummy gate electrode (1115). In operation 1120, a metal film pattern for contacting the metal plug to ground the dummy gate electrode is formed. A second interlayer insulating film is formed on the metal film pattern (1125). Finally, a passive element for generating a flux line, such as an inductor, is formed on the interlayer insulating layer on the dummy gate electrode (1130).

 A method of manufacturing an integrated circuit device according to other embodiments of the present invention will be described with reference to the exemplary flowchart of FIG. 12. As shown in FIG. 12, an active device region and a passive device region are formed on a semiconductor substrate (1200). A gate electrode of the active element is formed in the active element region and a dummy gate electrode structure is simultaneously formed in the passive element region (1205). The dummy gate electrode structure includes a plurality of segments. Each segment includes a portion extending in the first direction and a portion extending in the second direction. One group of segments extends substantially at the same angle and is arranged spaced apart from one another. An interlayer insulating layer is formed on the gate electrode and the dummy gate electrode structure (1210). A flux line generating passive element, such as an inductor or capacitor, is formed over the interlayer dielectric on the dummy gate electrode structure (1215).

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the present invention, a dummy gate structure and / or a conductive region placed between the substrate and the passive element and functioning as a shield can effectively block penetration of the flux line generated by the passive element into the substrate. In addition, the inclusion of a shield structure and / or a conductive screen can effectively block flux lines or eddy currents from penetrating into active element regions other than passive elements.

Claims (67)

Semiconductor substrates; A flux line generating passive element formed on the semiconductor substrate; And A dummy gate structure arranged on the semiconductor substrate under the passive element, wherein the dummy gate includes a plurality of segments, each segment including a portion extending in a first direction and a portion extending in a second direction, The portion extending in the second direction extends at an angle from one end of the portion extending in the first direction, and the segments extending in the first direction are angles extending in the second direction in the first direction. The segments comprise dummy gate structures each extending at substantially the same angle in the second direction and arranged spaced apart from one another. The integrated circuit device of claim 1, wherein the dummy gate structure is configured to block a flux line generated by the passive device from penetrating into the semiconductor substrate. 3. The integrated circuit device of claim 2, wherein the passive device is an inductor and at least half of the segments extend in a direction perpendicular to the inductor overlying it. 3. The integrated circuit device of claim 2, further comprising a plurality of device isolation regions under the passive device, wherein the dummy gate structure segments are formed on the device isolation region to define a first shield. 5. The integrated circuit device of claim 4, further comprising a plurality of conductive regions formed between the device isolation regions to define a complementary second shield. 6. The integrated circuit device of claim 5, wherein the plurality of conductive regions comprises a metal silicide pattern on the semiconductor substrate. 6. The integrated circuit device of claim 5, further comprising an interlayer insulating film covering the dummy gate structure and the plurality of conductive regions and on which the passive element is placed. 8. The method of claim 7, wherein the boundary extends in the interlayer insulating film around the passive element and defines a boundary surrounding the passive element and restricts flux lines generated by the passive element from penetrating outside the boundary. The integrated circuit device further comprising a conductive screen formed to. 10. The plurality of conductive elements of claim 8, wherein the conductive screen includes a plurality of conductive columns formed to extend along the boundary and spaced apart from each other into the interlayer insulating film, each conductive column being spaced apart from each other and electrically connected to each other. Integrated circuit device including the. The integrated circuit device of claim 9, wherein the passive device comprises an inductor. 11. The semiconductor device of claim 10, wherein the passive device underside comprises a passive device region of an integrated circuit device, wherein the integrated circuit device further comprises an active device region on the semiconductor substrate adjacent to the outside of the boundary of the passive device region, And the active device region includes an active device gate electrode formed when the plurality of dummy gate electrodes are formed. The semiconductor device of claim 10, wherein the passive device subregion includes a passive device region of the integrated circuit device, and the integrated circuit device further includes an active device region on the semiconductor substrate adjacent to the outside of the boundary of the passive device region. And the active device region includes an active device gate electrode formed of the same layer as the plurality of dummy gate electrodes. 10. The device of claim 9, being formed extending in the interlayer insulating film around the passive element, defining a second boundary around the passive element, spaced apart from the conductive screen, and generated by the passive element beyond the second boundary. And a complementary conductive screen configured to limit penetration of the flux line to the outside. 8. The integrated circuit device of claim 7, wherein the dummy gate structure comprises a gate insulating film on the semiconductor substrate and a conductive gate electrode on the gate insulating film. The integrated circuit device of claim 14, wherein the dummy gate structure further includes a silicide layer on the gate electrode and insulating sidewalls of sidewalls of the gate insulating layer, the gate electrode, and the silicide layer. The method of claim 7, wherein the interlayer insulating film includes first and second interlayer insulating films, wherein the first interlayer insulating film is formed on the dummy gate electrode, and the plurality of conductive regions are formed on the first interlayer insulating film. And the second interlayer insulating layer is formed on the plurality of conductive regions. 17. The integrated circuit device of claim 16, wherein the passive device comprises a capacitor. 6. The integrated circuit device of claim 5, further comprising a metal contact coupled to the dummy gate structure at a central region below the passive element to connect the dummy gate structure to ground. 19. The integrated circuit device of claim 18, further comprising a metal contact connected to the plurality of conductive regions in a central region below the passive element to couple the plurality of conductive regions to ground. 3. The integrated circuit device of claim 2, further comprising a metal contact connected to the dummy gate structure in a central region below the passive element and connecting the dummy gate structure to ground. 3. The integrated circuit device of claim 2, wherein the dummy gate structure comprises a plurality of sets of segments arranged in a symmetrical pattern. Semiconductor substrates; A flux line generating passive element on the semiconductor substrate; A dummy gate structure arranged on the semiconductor substrate under the passive element and arranged to block flux lines generated by the passive element from penetrating into the semiconductor substrate; And And a metal contact connected to the dummy gate structure in a central region below the passive element to connect the dummy gate structure to ground. 23. The integrated circuit device of claim 22, wherein the passive element is an inductor, the dummy gate structure includes a plurality of segments extending in one direction, and at least half of the plurality of segments extend perpendicular to the inductor. 23. The integrated circuit device of claim 22, further comprising a plurality of device isolation regions in an area below the passive device, wherein the dummy gate structure segments overlie the device isolation region to define a first shield. 25. The integrated circuit device of claim 24, further comprising a plurality of conductive regions formed between the device isolation regions to define a complementary second shield. 26. The integrated circuit device of claim 25, wherein the plurality of conductive regions comprises a metal silicide pattern on the semiconductor substrate. 27. The integrated circuit device of claim 25, further comprising an interlayer insulating layer covering the dummy gate structure and the plurality of conductive regions and on which the passive element is placed. 28. The method of claim 27, further comprising a boundary extending around the passive element and defining a boundary surrounding the passive element, wherein a flux line generated by the passive element penetrates outside the boundary. An integrated circuit device further comprising a conductive screen configured to limit that. 29. The plurality of conductive elements of claim 28, wherein the conductive screen comprises a plurality of conductive columns formed to extend along the boundary and spaced apart from each other into the interlayer insulating film, each conductive column being spaced apart from each other and electrically connected to each other. Integrated circuit device including the. 30. The integrated circuit device of claim 29, wherein the passive device comprises an inductor. 31. The semiconductor device of claim 30, wherein the passive device underside comprises a passive device region of an integrated circuit device, the integrated circuit device further comprising an active device region on the semiconductor substrate adjacent outside the boundary of the passive device region, And the active device region includes an active device gate electrode formed when the plurality of dummy gate electrodes are formed. 31. The semiconductor device of claim 30, wherein the passive device subregion comprises a passive device region of the integrated circuit device, and the integrated circuit device further comprises an active device region on the semiconductor substrate adjacent outside the boundary of the passive device region. And the active device region includes an active device gate electrode formed of the same layer as the plurality of dummy gate electrodes. 30. The passive element of claim 29, being formed extending in the interlayer insulating film around the passive element, defining a second boundary around the passive element, spaced apart from the conductive screen, and beyond the second boundary by the passive element. And a complementary conductive screen formed to limit penetration of the generated flux line to the outside. 28. The integrated circuit device of claim 27, wherein the dummy gate structure comprises a gate insulating film on the semiconductor substrate and a conductive gate electrode on the gate insulating film. 28. The method of claim 27, wherein the interlayer insulating film includes first and second interlayer insulating films, wherein the first interlayer insulating film is formed on the dummy gate electrode, and the plurality of conductive regions are formed on the first interlayer insulating film. And the second interlayer insulating layer is formed on the plurality of conductive regions. 36. The integrated circuit device of claim 35, wherein the passive device comprises a capacitor. 27. The integrated circuit device of claim 26, further comprising a metal contact connected to the plurality of conductive regions in a central region below the passive element to couple the plurality of conductive regions to ground. 23. The integrated circuit device of claim 22, wherein the dummy gate structure includes a plurality of sets of segments arranged in a symmetrical pattern. Semiconductor substrates; A first interlayer insulating film on the semiconductor substrate; A second interlayer insulating film on the first interlayer insulating film; A third interlayer insulating film on the second interlayer insulating film; A flux line generating passive element on the third interlayer insulating film; A first grounded conductive shield pattern formed on the first interlayer insulating layer in the passive element lower region; And And a second grounded conductive shield pattern formed on the second interlayer insulating layer in the lower region of the passive element. 40. The integrated circuit device of claim 39, wherein the first and second grounded conductive shield patterns are metal patterns. Semiconductor substrates; A flux line generating passive element on the semiconductor substrate; A plurality of device isolation regions formed in the semiconductor substrate beneath the passive device, the plurality of device isolation regions having a plurality of segments defining a first shield pattern which prevents the flux line generated by the passive device from penetrating into the semiconductor substrate; And And a plurality of conductive elements formed between the plurality of device isolation regions to define a complementary second shield pattern that prevents the flux lines generated by the passive elements from penetrating into the semiconductor substrate. 42. The integrated circuit device of claim 41, wherein the plurality of conductive elements comprises a dummy gate structure. 42. The integrated circuit device of claim 41, wherein the plurality of conductive elements comprises a metal silicide pattern. Semiconductor substrates; A flux line generating capacitor on the semiconductor substrate; And And a dummy gate structure arranged on the semiconductor substrate in the capacitor subregion and blocking flux lines generated by the capacitor from penetrating into the semiconductor substrate. Forming an active device region and a passive device region in the semiconductor substrate; Simultaneously forming a gate electrode of an active element in the active element region and a dummy gate electrode in the passive element region; Forming a first interlayer insulating film on the gate electrode and the dummy gate electrode; Forming a metal plug penetrating the first interlayer insulating layer to be in contact with a central portion of the dummy gate electrode; Forming a metal film pattern in contact with the metal plug to connect the dummy gate electrode to a ground; Forming a second interlayer insulating film on the metal film pattern; And Forming a flux line generation passive element on said second interlayer dielectric on said dummy gate electrode. Forming an active device region and a passive device region in the semiconductor substrate; Simultaneously forming a gate electrode of the active element in the active element region and a dummy gate electrode structure in the passive element region, wherein the dummy gate electrode structure includes a plurality of segments, each segment extending in a first direction; And a portion extending in a second direction, wherein the portion extending in the second direction extends at an angle from one end of the portion extending in the first direction, and each segment extending in the first direction is formed in the first direction. Forming a dummy gate structure in which the segments extending in the second direction in one direction extend at substantially the same angle in the second direction and are spaced apart from each other by a predetermined distance; Forming an interlayer insulating film on the gate electrode and the dummy gate electrode structure; And Producing a flux line generating passive element on said interlayer insulating film on said dummy gate electrode structure. Semiconductor substrates; A flux line generating passive element on the semiconductor substrate; And The passive element arranged around the passive element and between the passive element and the semiconductor substrate and blocking the penetration of the flux line from the passive element into the semiconductor substrate and generating the flux line from the passive element An integrated circuit device comprising a three-dimensional magnetic field shield to block penetration into the surrounding surrounding. 48. The integrated circuit device of claim 47, wherein the three-dimensional magnetic field shield includes a dummy gate structure arranged on the semiconductor substrate in the passive device subregion. 49. The integrated circuit device of claim 48, wherein the dummy gate structure includes a plurality of elongated segments. 50. The integrated circuit device of claim 49, further comprising a plurality of device isolation regions in the semiconductor substrate, wherein the dummy gate structure segments overlie the device isolation regions to define a first shield. 51. The integrated circuit device of claim 50, wherein the three-dimensional electromagnetic shield further comprises a plurality of conductive regions disposed between the device isolation regions to define a complementary second shield. 52. The integrated circuit device of claim 51, wherein the plurality of conductive regions comprises a metal silicide pattern on the semiconductor substrate. 53. The integrated circuit device of claim 52, further comprising an interlayer insulating film covering the dummy gate structure and the plurality of conductive regions and on which the passive element is placed. 54. The device of claim 53, wherein the three-dimensional magnetic field shield extends inside the interlayer insulating film around the passive element and defines a boundary surrounding the passive element, wherein a flux line generated by the passive element defines the boundary. And a conductive screen configured to limit penetration beyond. 55. The plurality of conductive columns of claim 54, wherein the conductive screen includes a plurality of conductive columns formed to extend along the boundary and spaced apart from each other within the interlayer insulating film, wherein the conductive columns are spaced apart from each other and electrically connected to each other. An integrated circuit device comprising elements. 51. The integrated circuit device of claim 50, further comprising a metal contact coupled to a dummy gate structure in a central region below the passive element to connect the dummy gate structure to ground. Semiconductor substrates; A flux line generating passive element on the semiconductor substrate; And A plurality of dummy gate structures arranged on the semiconductor substrate below the passive element, each dummy gate structure being arranged spaced apart from each other and a plurality of dummy gates blocking flux lines generated by the passive element from penetrating the semiconductor substrate An integrated circuit device comprising a gate structure. The method of claim 57, An interlayer insulating film on the plurality of dummy gate structures; A metal film connected to ground on the interlayer insulating film; And And a plurality of conductive contacts extending from the metal film to the plurality of dummy gate structures and connecting the plurality of dummy gate structures to ground through the metal film. 59. The integrated circuit device of claim 58, further comprising an interlayer insulating film covering the plurality of gate structures on the interlayer insulating films on the plurality of gate structures, on which the passive elements are placed. 60. The integrated circuit device of claim 59, further comprising a plurality of device isolation regions in the passive device subregion, wherein the dummy gate structure is disposed on the device isolation region to define a first shield. 61. The integrated circuit device of claim 60, further comprising a plurality of conductive regions formed between the plurality of device isolation regions to define a complementary second shield. 62. The method of claim 61, wherein the barrier layer extends inside the interlayer insulating layer around the passive element, defines a boundary surrounding the passive element, and flux lines generated by the passive element penetrate outside the boundary. An integrated circuit device further comprising a conductive screen configured to limit that. 64. The plurality of conductive elements of claim 62, wherein the conductive screen comprises a plurality of conductive columns formed to extend along the boundary and spaced apart from each other into the interlayer insulating film, each conductive column being spaced apart from each other and electrically connected to each other. Integrated circuit device including the. 62. The method of claim 61, wherein the plurality of dummy gates include a portion extending in a first direction and a portion extending in a second direction, wherein the portion extending in the second direction is one of the portion extending in the first direction. Each segment extending from the distal end at a predetermined angle, wherein the segments extending in the first direction, each segment extending in the first direction, extends at substantially the same angle in the second direction, and is spaced apart from each other by a predetermined distance. Integrated circuit elements arranged. 65. The integrated circuit device of claim 64, wherein the plurality of dummy gates includes a plurality of dummy gate sets arranged in a symmetrical pattern. 62. The integrated circuit device of claim 61, further comprising a metal contact coupled to the plurality of dummy gates of the passive element lower center region to connect the plurality of dummy gates to ground. Semiconductor substrates; A first interlayer insulating film on the semiconductor substrate; A second interlayer insulating film on the first interlayer insulating film; A third interlayer insulating film on the second interlayer insulating film; A flux line generating passive element on said third interlayer insulating film; A first metal conductive shield pattern on the first interlayer insulating layer in the lower region of the passive element; And And a second metal conductive shield pattern on the second interlayer insulating layer in the lower region of the passive element.

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