TWI239611B - Multi chip module with embedded package configuration and method for manufacturing the same - Google Patents

Multi chip module with embedded package configuration and method for manufacturing the same Download PDF

Info

Publication number
TWI239611B
TWI239611B TW093110865A TW93110865A TWI239611B TW I239611 B TWI239611 B TW I239611B TW 093110865 A TW093110865 A TW 093110865A TW 93110865 A TW93110865 A TW 93110865A TW I239611 B TWI239611 B TW I239611B
Authority
TW
Taiwan
Prior art keywords
package structure
substrate
embedded
chip module
patent application
Prior art date
Application number
TW093110865A
Other languages
English (en)
Other versions
TW200536078A (en
Inventor
Jung-Kun Kang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093110865A priority Critical patent/TWI239611B/zh
Priority to US11/106,554 priority patent/US7417322B2/en
Application granted granted Critical
Publication of TWI239611B publication Critical patent/TWI239611B/zh
Publication of TW200536078A publication Critical patent/TW200536078A/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1088—Arrangements to limit the height of the assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09072—Hole or recess under component or special relationship between hole and component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

1239611 五、發明說明（l) · · -- 【發明所屬之技術領域】 本發明係有關於一種多晶片模組，特別係有關於一 嵌入結合之多晶片模組。 【先前技術】 隨f微小化與高運作速度需求的增加，會將多項功能 整合於單糸統晶片（sy s tem on ch i p，SOC )或將多個封 裝構ie整合成一多晶片模組之系統封裝（sy s tem i ^ package ’ SIP)，其中系統晶片係將類比、記憶體和邏輯 電路整合為一，但卻產生了 如構成邏輯電路的電晶體微 低，但卻不易維持性能，且 雜訊比將會明顯提高，而習 專利公告第5335 61號「開口 者’其係包含一基板、至少 片、至少一第三晶片及一封 第二面及至少一穿透之開口 路佈線，以傳輸電氣信號， 之開口上方，且藉由覆晶接 外圍區域之基板第一面上的 第二晶片與上述第一晶片相 作電氣接合至基板第一面的 許多難以兩全的技術問題，例 細化時，自然會使動作電壓降 當類比電路降至2· 5V以下時， 知之多晶片模組，如中華民國 式多晶片堆疊封裝」所揭示 一第一晶片、至少一第二晶 裝體，該基板係具有第一面、 ，且該基板至少包括有二層電 該第一晶片係設於基板第一面 合技術將複數個凸塊銲於開口 電路佈線上以作電氣連接，該 疊黏合，並將第二晶片以金線 電路佈線的位置上以作電氣連 接，該第三晶片係設於該基板第二面之開口下方，其晶片 尺寸小於第一晶片，且可藉由複數個凸塊與第一晶片中心 部位銲接作電氣接合，並以填膠充填於第一晶片與第三晶
第7頁 1239611 五 發明說明（2) 片及第一晶片與該基板第一 基板第一面上方，並包覆第 者，由於该第三晶片係利用 隹于接作電氣接合，故該第一 供該第三晶片覆晶接合，設 之訊號因為必須經過該第一 雜訊，此外，由於該多晶片 二晶片與該第三晶片整合在 堆疊封裝需預燒（burr-i n) 試。 【發明内容】 面^間區域者，該封裝體係由 一曰曰片與基板接合之金線外圍 "亥些凸塊與第一晶片中心部位 晶片必須設計對應之銲墊，以 汁上較為複雜，且該第三晶片 晶片，而彼此互相影響，產生 堆疊封裝係該第一晶片、該第 门 封装構造中’如該多晶片 貝J無法針對早一晶片進行測 ^本發明之主要目的係在於提供一種嵌入結合之多晶片 模組，利用一第二封裝構造嵌入埋設於一第一封裝構造之 基板之嵌合開口，以使該嵌入結合之多晶片模組以該第一 封裝構造之複數個銲球與該第二封裝構造之複數個外終端 對外電性連接，且該些銲球與該些外終端構成同一表面接 合面（SMT surface)，使得該第一封裝構造與該第二封裝 構造能夠以同時表面接合（SMT)於外部電性裝置。 ^本發明之次一目的係在於提供一種嵌入結合之多晶片 模組，利用一第二封裝構造嵌入設於一第一封裝構造之# 板之嵌合開口’使該第二封裝構造之複數個外終端與該第 一封裝構造之複數個銲球構成同一表面接合面，以降低該 多晶片模組之高度。 本發明之再一目的係在於提供一種嵌入結合之多晶片
第8頁 1239611 五、發明說明（3) 模組，利用一第二封裝構造嵌一 板之嵌合開口，且該第-封封裝構造之基 電性連接，以避免該第—封F構造血笛 封裝構过 互相影響、產生雜訊。？構&與㈣二封裝構造電性 本發明之又一目的係在於提供一種嵌入社人 模組之製造方法’其係個別測試第— σ之夕日曰片 裝播邊，以破μ兮筮 + &構造以及第二射 裝構xe以確^忒苐一封裝構造與該第二封裝構 .品（know good package)，再將良好之第二‘，入 一封裝構造之基板之嵌合開口，以組成1良 依本發明之嵌入結合之多晶片模組，其包含一一感 =造^至少-第二封㈣造，該第—封裝構造係包含〆 品一晶片i 一封膠體及複數個銲球，該基板係具有〆 ίίΪ :::ΐ面以及至少一嵌合開口，該嵌合開口係吁 表面，該第一封裝構造之晶片係設於 i 表面並與該基板電性連接’該第一封裝構造之 體2形成，該基板之上表s，該些銲球係植接於該基 反=下面，§亥第二封裝構造係嵌入設於該第一封裝構造 之該嵌合開口，較佳地’以-黏著層將該第二封裝 構造固設於該第一封跋構造之嵌合開口中，且該第二封裝馨 構ί係不與該第一封裝構造電性連接，該第二封裝構造係 後數個外終端，其係與該第一封裝構造之銲球構成 " 接曰面，以使传s玄彼入結合之多晶片模組以該些 外終端與該些銲球對外電性連接。
第9頁 1239611
【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之一具體實施例，請參閱第1及2圖，一種嵌 入結合之多晶片模組，係包含有一第一封裝構造丨〇 〇及至 夕一第二封裝構造2 0 〇，該第一封裝構造1 ο 〇係包含一基板 11 0、一晶片120、一封膠體130及複數個銲球i 40，該基板 110之厚度係不大於〇· 5mm為佳，其係具有一上表面in、 一下表面11 2以及至少一嵌合開口 11 3，該嵌合開口 11 3係 可為貫穿或不貫穿該基板11 〇之上表面丨丨1與下表面丨12， 在本實施例中，該嵌合開口 11 3係為貫穿該基板丨丨〇之該j 表面111與該下表面112，該晶片120係可為邏輯（Logic)晶 片或特殊應用積體電路（Application Specific Integrated Circuit，ASIC)晶片，其係具有一主動面 121 與一對應之背面1 2 2，在本實施例中，該晶片丨2 〇係以主動 面121朝上方式設於該基板no之上表面丨丨1，並藉由複數 個銲線151與該基板11〇電性連接，該晶片12〇之背面122係 部分顯露於該基板11 0之嵌合開口 11 3，必要時，該晶片 1 2 0之主動面1 21係可再堆疊另一晶片1 6 〇，且該晶片！ 6 〇係 藉由複數個銲線152與該基板11〇電性連接，該封膠體丨30 係形成於3玄基板110之上表面111並覆蓋該晶片12〇之第一鲁 動面121、該晶片1 60與該些銲線151、152，該些銲球1 40 係植接於该基板11 0之下表面11 2。 該第二封裝構造200係為經預燒（burr-in)之良品 (know good package)，其係嵌入設於該第一封裝構造1〇〇
第10頁
1239611 五、發明說明（5) 之基板110之該嵌合開口 113，較佳地，以一黏著層300將 邊第二封裝構造2〇〇固設於該第一封裝構造1〇〇之嵌合開口 11 3中，在本實施例中，該第二封裝構造2〇〇係被固設於該 第一封裝構造1 〇 〇之該晶片1 2 0下，但不與該第一封裝構造 1 0 0電性連接，該第二封裝構造2 〇 〇係選自於球格陣列封裝 構造、覆晶封裝構造、晶片尺寸封裝構造與晶圓級晶片尺 寸封裝構造之其中之一，本實施例係以球格陣列封裝構造 例舉之，該第二封裝構造200係包含一基板21 〇、一晶片 220、一封膠體230及複數個外終端24〇，該些外終端24〇係 了為‘球’ a玄基板2 1 〇係具有一下表面2 1 1，較佳地，該下 表面21 1係與該第一封裝構造100之基板11()之該下表面112 共平面’该晶片22 0係為需經預燒（burr-in)之記憶體晶 片’並以複數個銲線2 5 〇與該基板21 〇電性連接，該封膠體 230係覆蓋該晶片2 20與該些銲線251，該些外終端240係形 成於该基板2 10之下表面211，且該些外終端240係與該第 一封裝構造1 0 0之該些銲球1 4 0構成同一表面接合面1 〇 ( SMT surf ace) ’使得該多晶片模組以該些外終端24〇與該些銲 球1 4 0對外電性連接，且可使得該嵌入結合之多晶片模組 之南度係不大於1.2mm。 因此本案發明係利用該第二封裝構造2〇{)嵌入設於該鲁 第一封裝構造1 0 0之基板1 1 0之嵌合開口丨丨3 ,並使該第二 封裝構造2〇〇之該些外終端240與該第一封裝構造1〇〇之該 些銲球140構成同一表面接合面丨〇，使得該第一封襞構造 1 00與該第二封裝構造2〇 〇能夠同時表面接合（SMT)於外部
第11頁 1239611 發明說明（6) 電性裝置（圖未繪出），且可將該多晶片模組之高度控制 i. 2mm以下，以降低該多晶片模組2〇 〇之高度，而由於誃 二封裝構造200係不直接與該第一封裝構造1〇〇電性連^， 玎避免該第一封裝構造1 00與該第二封裝構造2〇〇 影響、產生雜訊。 4 請參閱第3圖，其係為上述嵌入結合之多晶片模 製造方法之流程圖，首先，個別進行「提供一第一封 造」之步驟A1與「提供一第二封裝構造」之步驟Βι， 後’個別進行「測試該第一封褒構造」之步驟^與「測試 該第一封裝構造」之步驟B2，以個別確認該第一封 100與該第二封裝構造20〇是否為良品（kn〇w g〇〇d " =〇，且在「測試該第一封裝構造」之步驟A2與「測 试忒第二封裝構造」之步驟B2之中係可分別包含— (burr-irO過程，之後，再進行一「嵌設該第二封裝構^造 =忒第一封裝構造，以組成一嵌入結合之多晶片模組之 步驟c ’以使得該第一封裝構造1〇〇之該些銲球14〇與^ ά = 之該些外終端240係構成同-表面接合"面1〇 之多曰=接，Ξ佳地，可再進行一「測試該嵌入結舍 ;二=組」之步驟D’以確定出貨至客戶端之多晶片 本發明之保護範圍當視後附之申請專利範圍所 何熟知此項技藝者’在不脫離本發明之精神和範 内斤作之任何變化與修改，均屬於本發明之保護範圍。
第12頁 1239611__ 圖式簡單說明 【圖式簡單說明】 第1 圖：依據本發明之一具體實施例，一種嵌入結合之多 晶片才莫組之截面不意圖， 第2 圖：依據本發明之一具體實施例，一第二封裝構造嵌 設入一第一封裝構造之前之截面示意圖；及 第3 圖：依據本發明之一具體實施例，該嵌入結合之多晶 片模組之製造方法之流程圖。 元件符號簡單說明： A1 提供一第一封裝構造 A2 測試該第一封裝構造 B1 提供一第二封裝構造 B2 測試該第二封裝構造 110 基板 111 上表面 112 下表面 113 般合開口 120 晶片 121 主動面 122 背面 130 封膠體 140 焊球 151 銲線 152 銲線 C 嵌設該第二封裝構造於該第一封裝構造，以組成一嵌 入結合之多晶片模組 D 測試該嵌入結合之多晶片模組 10 表面接合面 1 0 0第一封裝構造
第13頁 1239611_ 圖式簡單說明 1 6 0 晶片 200 第二封裝構造 210 基板 211 下表面 2 2 0 晶片 2 3 0 封膠體 2 4 0 外終端 2 5 0 鮮線 300黏著層 IB·! 第14頁

Claims (1)

1239611 六、申請4利範圍 申請專利範圍】 、一種嵌入結合之多晶片模組，包含： 一第一封裝構造，其係包含： 基板，其係具有一上表面、一下表面以及至少 Π ; 曰曰片 其係没於或基板之上表面並與該基板電性連 一封膠體，其係形成於該基板之上表面；及 複數個銲球，其係植接於該基板之下表面；及 至少一第二封裝構造，其係包含有複數個外終端，該 第二封裝構造係嵌入設於該第一封裝構造之基板之嵌合開 口 〇 2、 如申請專利範圍第1項所述之嵌入結合之多晶片模 組’其中該些銲球與該些外終端係構成同一表面接合面 CSMT surf ace)，以作為該多晶片模組之對外電性連接。 3、 如申請專利範圍第1項所述之嵌入結合之多晶片模 組’其中該嵌入結合之多晶片模組之高度係不大於1.2mm 〇 4、 如申請專利範圍第1項所述之嵌入結合之多晶片模 ’其中該第二封装構造係不與該第一封裝構造電性連 合開 嵌 接 接 組 如申請專利範圍第1項所述之嵌入結合之多晶片模 其中該第一封裝構造之基板之厚度係不大於〇· 5mm 如申請專利範圍第1項所述之嵌入結合之多晶片模 _ 第15頁 1239611
六、申請專利範圍 組’其另包含一黏著層，以將該第二封裝構造固設於該第 一封裝構造。 7、 如申凊專利範圍第1項所述之欲入結合之多晶片模 組’其中該第一封裝構造之基板之嵌合開口係貫穿該基板 之上表面與下表面。 8、 如申請專利範圍第7項所述之彼入結合之多晶片模 組’其中該第一封裝構造之晶片係具有一背面，其係部分 顯露於該嵌合開口。 9、 如申請專利範圍第1項所述之嵌入結合之多晶片模 組’其中該第一封裝構造之晶片係為選自邏輯（Logic)晶 片與特殊應用積體電路（Application Specific Integrated Circuit，ASIC)晶片其中之一。 I 0、如申請專利範圍第1項所述之嵌入結合之多晶片模 、、且其中戎第二封製構造係包含一基板、一晶片及一封膠 體 °亥第一封跋構造之基板係具有一下表面，其係血該第 一封裝構造之基板之下表面為共平面. # II 如申清專利範圍第1項所述之彼入結合之多晶片模 組’其中該第二封裝構造係包含有需經預燒“以卜“）之 記憶體晶片。 1 2、如申請專利範圍第丨丨項所述之嵌入結合之多晶片模 組’其中該第二封裝構造係為經預燒（burr—in)之良品、 (know g0〇d package)。 1 3、如申請專利範圍第1項所述之嵌入結合之多晶片模 組，其中該第二封裝構造係選自於球格陣列封裝構造、、覆
1239611_ 六、申請專利範圍 晶封裝構造、晶片尺寸封裝構造與晶圓級晶片尺寸封裝構 造之其中之一。 1 4、一種嵌入結合之多晶片模組之製造方法，包含有： 提供一第一封裝構造，該第一封裝構造係包含： 一基板，其係具有一上表面 '一下表面以及至少一嵌 合開口； 曰曰片 其係設於該基板之上表面並與該基板電性連 接； 一封膠體，其係形成於該基板之上表面；及 複數個銲球，其係植接於該基板之下表面； k供至少一第二封裝構造，該第二封裝構造係包含有 複數個外終端； 測試該第二封裝構造，以確認該第二封裝構造是否為 良品（know good package);及 嵌設經測試過後係為良品之該第二封裝構造於該第一 封裝構造之嵌合開口，以組成一嵌入結合之多晶片模組。 1 5、如申請專利範圍第丨4項所述之嵌入結合之多晶片模組 之製造方法，其中該些銲球與該些外終端係構成同一表面 接合面（SMT surf ace)，以作為該多晶片模組之對外電性 連接。 _ 1 6、如申請專利範圍第1 4項所述之嵌入結合之多晶片模組 之製造方法，在提供該第一封裝構造之步驟之後，其另包 含一測試該第一封裝構造之步驟，以確認該第一封裝構造 疋否為良品（know good package)。
第17頁 1239611 六、申請專利範圍 1 7、如申請專利範圍第1 4項所述之後入結合之多晶片模組 之製造方法，在嵌設該第二封裝構造於該第一封褽構造之 步驟之後，其另包含一測試該多晶片模組之步驟，以碟定 該多晶片模組為良品。 1 8、如申請專利範圍第丨4項所述之嵌入結合之多晶片模組 之製造方法，其中在測試該第二封裝構造之步驟之中係包 含一預燒（burr-in)過程。 1 9、如申請專利範圍第1項所述之嵌入結合之多晶片模組 之製造方法，其中該第一封裝構造之晶片係為選自邏輯 (Logic)晶片與特殊應用積體電路（Appl icat ion Speci fi_ Integrated Circuit，ASIC)晶片其中之-。 ^ 20、如申請專利範圍第1項所述之嵌入結合之多晶片模組 之製造方法，其中該第二封裝構造係選自於球格陣列封裝 構造、覆晶封襄構造、晶片尺寸封裝構造與晶圓級晶片 寸封聢構造之其中之一。 一—如申請專利範圍第i項所述之嵌入結合之多晶片模組 f製造方法，其中該第二封裝構造係包含一基板、一晶 體該第二封裝構造之基板係具有-下表面，其 胸第-封敦構造之基板之下表面為共平面。 其
第18頁
TW093110865A 2004-04-19 2004-04-19 Multi chip module with embedded package configuration and method for manufacturing the same TWI239611B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW093110865A TWI239611B (en) 2004-04-19 2004-04-19 Multi chip module with embedded package configuration and method for manufacturing the same
US11/106,554 US7417322B2 (en) 2004-04-19 2005-04-15 Multi-chip module with embedded package and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093110865A TWI239611B (en) 2004-04-19 2004-04-19 Multi chip module with embedded package configuration and method for manufacturing the same

Publications (2)

Publication Number Publication Date
TWI239611B true TWI239611B (en) 2005-09-11
TW200536078A TW200536078A (en) 2005-11-01

Family

ID=35095437

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093110865A TWI239611B (en) 2004-04-19 2004-04-19 Multi chip module with embedded package configuration and method for manufacturing the same

Country Status (2)

Country Link
US (1) US7417322B2 (zh)
TW (1) TWI239611B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI283467B (en) * 2003-12-31 2007-07-01 Advanced Semiconductor Eng Multi-chip package structure
US7528474B2 (en) * 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US7288835B2 (en) * 2006-03-17 2007-10-30 Stats Chippac Ltd. Integrated circuit package-in-package system
TWI315574B (en) * 2006-07-28 2009-10-01 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US7723833B2 (en) * 2006-08-30 2010-05-25 United Test And Assembly Center Ltd. Stacked die packages
KR100817075B1 (ko) * 2006-11-09 2008-03-26 삼성전자주식회사 멀티스택 패키지 및 그 제조 방법
JP2008166527A (ja) * 2006-12-28 2008-07-17 Spansion Llc 半導体装置およびその製造方法
US7750451B2 (en) * 2007-02-07 2010-07-06 Stats Chippac Ltd. Multi-chip package system with multiple substrates
US9466545B1 (en) * 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US8237259B2 (en) * 2007-06-13 2012-08-07 Infineon Technologies Ag Embedded chip package
US7709944B2 (en) * 2007-12-18 2010-05-04 Stats Chippac Ltd. Integrated circuit package system with package integration
KR20090119187A (ko) * 2008-05-15 2009-11-19 삼성전자주식회사 연료전지를 포함하는 패키지, 그 제조 방법, 및 패키지를포함하는 카드 및 시스템
US8604602B2 (en) * 2009-05-15 2013-12-10 Stats Chippac Ltd. Integrated circuit packaging system with reinforced encapsulant having embedded interconnect and method of manufacture thereof
KR102191669B1 (ko) 2013-08-05 2020-12-16 삼성전자주식회사 멀티-칩 패키지
WO2017188944A1 (en) * 2016-04-27 2017-11-02 Intel Corporation High density multiple die structure
US10700011B2 (en) 2016-12-07 2020-06-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an integrated SIP module with embedded inductor or package
US10720720B2 (en) * 2018-03-19 2020-07-21 Visteon Global Technologies, Inc. System of stacking electronic modules on a base board

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69405832T2 (de) * 1993-07-28 1998-02-05 Whitaker Corp Von der Peripherie-unabhängiges präzises Positionsglied für einen Halbleiterchip und Herstellungsverfahren dafür
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
US6451626B1 (en) * 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
TW533561B (en) 2002-02-26 2003-05-21 Orient Semiconductor Elect Ltd Opening-type multi-chip stacking package
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US6713857B1 (en) * 2002-12-05 2004-03-30 Ultra Tera Corporation Low profile stacked multi-chip semiconductor package with chip carrier having opening and fabrication method of the semiconductor package
TWI225299B (en) * 2003-05-02 2004-12-11 Advanced Semiconductor Eng Stacked flip chip package

Also Published As

Publication number Publication date
US20050230799A1 (en) 2005-10-20
US7417322B2 (en) 2008-08-26
TW200536078A (en) 2005-11-01

Similar Documents

Publication Publication Date Title
TWI239611B (en) Multi chip module with embedded package configuration and method for manufacturing the same
TWI499024B (zh) 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
US7554185B2 (en) Flip chip and wire bond semiconductor package
EP2033220B1 (en) Stack die packages
TWI290365B (en) Stacked flip-chip package
TWI338941B (en) Semiconductor package structure
TWI283467B (en) Multi-chip package structure
TW557556B (en) Window-type multi-chip semiconductor package
TWI306658B (en) Leadframe on offset stacked chips package
TWI335658B (en) Stacked structure of chips and wafer structure for making same
SG130066A1 (en) Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
TWI292224B (en) Multi-chip package structure
TWI225291B (en) Multi-chips module and manufacturing method thereof
JP2007243196A (ja) 複数のチップ構成を有する集積デバイス及びその製造方法
US7235870B2 (en) Microelectronic multi-chip module
TW200807682A (en) Semiconductor package and method for manufacturing the same
US20070035006A1 (en) Stackable single package and stacked multi-chip assembly
US20040108585A1 (en) Electronic component having stacked semiconductor chips in parallel, and a method for producing the component
TW200939451A (en) Stacked semiconductor package
TW536764B (en) Method for multi-chip package and structure thereof
TWI288463B (en) Semiconductor package substrate and semiconductor package having the substrate
TW200910540A (en) Package structure and manufacturing method thereof
TW201037800A (en) Cavity chip package structure and package-on-package using the same
TWI278049B (en) Stackable back-to-back flip chip package
TW200841452A (en) Multi-chip stack structure

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent