TWI237860B - Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof - Google Patents

Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof Download PDF

Info

Publication number
TWI237860B
TWI237860B TW093103550A TW93103550A TWI237860B TW I237860 B TWI237860 B TW I237860B TW 093103550 A TW093103550 A TW 093103550A TW 93103550 A TW93103550 A TW 93103550A TW I237860 B TWI237860 B TW I237860B
Authority
TW
Taiwan
Prior art keywords
layer
wafer
flip
patent application
item
Prior art date
Application number
TW093103550A
Other languages
English (en)
Other versions
TW200527560A (en
Inventor
Mon-Chin Tsai
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093103550A priority Critical patent/TWI237860B/zh
Priority to US10/876,581 priority patent/US20050181538A1/en
Application granted granted Critical
Publication of TWI237860B publication Critical patent/TWI237860B/zh
Publication of TW200527560A publication Critical patent/TW200527560A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

1237860
(一）、【發明所屬之技術領域】 本發明係關於一種整合打線及覆晶封裝之曰 人3魂關於一種可簡化製程及減少製程材料之整 口丁、、、良及覆日日封裝之晶片結構及製程。 (二）、【先前技術】 谏辨：同ί ί訊化社會的♦曰，乡媒、體應用市不斷地急 姻=2 體電路封裝技術也隨之朝電子裝置的數位化、 路化、區域連接化以及使用人性化的趨勢發展。為達成 上述的要求’電子元件必須配合高速處理化、多功能化、 積集化、小型輕量化及低價化等多方面之要求，也因此積 體電路封裝技術也跟著朝向微型化、高密度化發展。其中 球格陣列式構裝（B a 1 1 g r i d A r r a y，B G A )，晶片尺寸構 裝（Chip-Scale package，CSP )，覆晶構裝（FUp
Chip ， F/C )，多晶片模組（Multi-Chip Module ， MCM )等 高密度積體電路封裝技術也因應而生。 其中覆晶構裝技術（Flip Chip Packaging T e c h η ο 1 o g y)主要是利用面陣列（a r e & a r r ay)的排列方式， 將多個晶片銲墊（bonding pad)配置於晶片（die)之主動表 面（active surface)，並在各個晶片銲墊上形成凸塊 (bump)，接著再將晶片翻面（fi ip)之後，利用晶片銲墊上 的凸塊分別電性（electrically)及機械（mechanically)連 接至基板（substrate)或印刷電路板（PCB)之表面所對應的 接合墊（mounting pad)。再者，由於覆晶接合技術係可應
1237860
五、發明說明（2) 用於高接腳數（High Pin Count)之晶片封裴結構，並同時 具有縮小封裝面積及縮短訊號傳輸路徑等多項優點，所^ 覆晶接合技術目前已經廣泛地應用在晶片封裝領域。然而 在多晶片封裝構造中，晶片不僅需要與另一晶片覆晶^妾 合，更需藉由打線接合之方式與基板電性連接，因此整合 打線及覆晶封裝之晶片結構及製程也當然地變成覆晶封I 技術之下一世代之發展重點。 、 而所謂的整合打線及覆晶封裝之晶片結構及製程，常 見於覆晶技術（f 1 i p ch i p )中，主要係在形成有多個晶片的 晶圓上對外的接點（通常是晶片銲墊）上形成球底金屬層 (UBM，Under Bump Metallurgy)，接著於部分之球底金屬 層上再設置另一供打金線（導電線）接合之潤濕層及阻障層 於其上。接著，接著則形成複數個凸塊或植入銲球於未設 有供打金線接合之潤濕層及阻障層之球底金屬層上以作為 後續晶片（或晶圓）與基板（substrate)覆晶接合電性導通之 連接介面。承上所述，一般而言，當晶片銲墊為鋁墊時， 球底金屬層通常依序由鋁/鎳—釩/銅金屬所組成，而上述所 提之供打金線接合之潤濕層及阻障層通常則由鎳金屬層及 金層所組成。 5月參照圖1 ’係為習知之整合打線及覆晶封裝之晶片製 程，其係包含下列步驟。首先，提供一晶片丨〇 〇，且每一晶 片^具有複數個晶片銲墊；[〇2及暴露出該等晶片銲墊1〇2之 f遵層104。接著，分別形成一球底金屬層106於每一該等 晶片銲墊102上。其中，晶片銲墊102係為鋁金屬，而球底
1237860 、發明說明（3) 金屬層106係為鋁l〇6a/鎳〜釩合金i〇6b/銅l〇6c三層金屬結 構’其係利用電鍍或濺渡等方式形成於晶圓表面，再接續 利用光阻覆蓋於球底金屬層上並利用顯影及蝕刻等方式圖 案化光阻層及球底金屬層以定義出所需之球底金屬層結 構。之後’於部分球底金屬層之銅金屬層丨〇6c上依序形成 鎳金屬層l〇6a及金層l〇6b。接著，形成一光阻層log於晶片 上，以暴露出未設置有鎳金屬層1〇6 &及金層1〇61)覆蓋之球 底金屬層106上。再者，於開口填充銲料，以形成複數個凸 塊110。最後，進行一迴銲步驟，以使凸塊11()與球底金 層1 0 6固定接合如圖2所示。 承 圖案化 金屬先 屬層上 式設置 程，故 由 球底金 不僅增 費及使 之晶片 要課題
上所逃，球底金屬層形成於晶片銲墊1〇2上可為 之球底金屬層或未經圖案化之球底金屬層，當底 經圖案化，則銲料可藉由印刷之方式設置於球底金 ;而當球底金屬未經圖案化，則銲料可藉由- 於球底金屬層上，惟此步驟係凸塊製程中% 在此不另贅述。 你千衣 :上述之整合打線及覆晶封裝之晶片構 屬上形成鎳金屬層及金層以供打金線接合 '
力:製程之步驟，且須增加鎳金屬層及金料： 用。因此，提供解決上述習知整合 枓耗 結構之缺點及其相關製程之方法，為^晶封裝 。 κ馮本發明之重
1237860 五、發明說明（4) 有鑑於上述課題，本發明之目的 打線及覆晶封裝之晶片構造及製程 種整合 nr程及減少製程材料之晶整合= 片結構及製程。 僳日日封裝之晶 緣是，&達上述目的，本發明係提出一種整 覆晶封裝之晶片製程’其係包含下列步驟。首&，：= 晶圓，該晶圓上具有複數個晶片銲墊及一使該等銲 暴露出之保護層。接著，分別形成一球底金屬層於一兮 等晶片鮮墊上，其中球底金屬層係由黏著$、阻障居及；^ 濕層所組成。再者，將部分設置於晶片銲墊上之球^屬 層上之阻障層及潤濕層移除，以暴露出黏著層作為導 接合之用。之後，於未移除阻障層及潤濕層之球底金層 上之潤濕層設置凸塊。最後，進行一迴銲步驟，以使凸塊 與球底金屬層接合。一般而言，晶片銲墊為鋁墊時，黏著 層係為鋁金屬層，阻障層係為鎳—釩層，而潤濕層為銅金屬 層。 、 再者，本發明另提出一種藉由上述整合打線及覆晶封 裝之晶片製程所形成之整合打線及覆晶封·裝之晶片锋構， 其係包含：一晶片’其係具有一主動表面、一保護層、複 數個晶片銲塾及一球底金屬層，其中該保護層及該等晶片 銲墊係形成於該主動表面上，該保護層係暴露出該等晶片 多干塾’且該球底金屬層係設置於該等晶片鲜塾上；部分之 球底金屬層上係未設置阻障層及潤、濕層以作為導電線接合 之用；另外，複數個凸塊，其係形成於每一該等晶片銲墊
第9頁 1237860
上之有阻障層及潤濕層之球底金屬層相接合。 么屈ΐ: 1斤ί，當晶片銲墊為鋁墊時，黏著層，般係由鋁 金屬J::成，故能直接作為金線之打線接合端點，故本 發明特別適用於整合打線及覆晶封裝之銘晶片結構及製 程，然而當晶片為銅墊時’仍可利用本發明所述之製程， 在部分之阻障層及潤濕層移除後’於暴露之黏著層上另形 成-鋁金屬層或其他適合作為打線接合之金屬層即可。 (四）、【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之整 合打線及覆晶封裝之晶片結構及製程。 明參考圖3 ’其顯示根據本發明之較佳實施例之整合 線及覆晶晶片結構的剖面示意圖。 先參考圖3 ’係表示晶片20 0之部分結構示意圖。晶 片2 0 0係具有晶片銲㈣2、保護層m及形成於晶片鲜塾 202上之球底金屬層2〇6。纟中，保護層2〇4係配置於晶片表 面上，用以保護晶片200表面並暴露出銲墊202 ,而部分之 球底金屬層係由黏著層20 6a、阻障層2〇6]3及潤濕層2〇吒所 組成，作為凸塊208與晶片銲墊2〇2接合之接合金屬層。另 外，部分之晶片銲墊2〇2上之球底金屬層2〇6中之潤濕層 206c及阻障層20 6b皆被移除而只暴露出黏著層2〇6a 為導電線接合之用。 值得注意的是，當晶片銲墊為鋁銲墊時，球底金屬層 206 —般係依序為鋁層/鎳—釩層/銅層，惟用以導電線接合
1237860 五、發明說明（6) "" 用之晶片銲墊上只設置有包含鋁層之球底金屬層。當晶片 銲墊為鋼銲墊時’球底金屬層2〇6 —般係依序為鈦層/鎳-飢 層/銅層，然而當晶片銲墊上方移除鎳-釩層/銅層欲作為晶 片打線接合用之端點時，除可保留鈦層作為導電線接合用 之端點外，（亦即球底金屬層上只包含有鈦金屬層）亦可於 欽層上再設置一與金線接合且與鈦層接合能力較佳之鋁金 屬層，作為導電線接合用之端點。 接著，請參考圖4至圖7，其顯示根據本發明之較佳實 施例之整合打線及覆晶封裝之晶片結構及製程的剖面示意 圖。 首先，請參照圖4，提供一晶片3 〇 〇，晶片3 〇 〇上形成有 有複數個晶片銲墊302及保護層3〇4。其中，保護層304係配 置於晶片300表面上，用以保護晶片3〇〇表面並使銲墊3〇2暴 露出。 接著’再請繼續參照圖4，形成球底金屬層3 〇 6於該晶 片+上並覆蓋晶片銲墊302。其中，球底金屬層306係包含黏 著層3 06a、阻障層3〇6b及潤濕層3〇6c。其中，球底金屬層 3 0 6可依序先形成形成黏著層、阻障層及潤濕層之金屬於晶 片上再利用光阻進行微影及|虫刻製程，以使該金屬圖案 化而使球底金屬層3 0 6只形成於晶片銲墊3 〇 2上方。接著， 請再參考圖4，形成另一光阻層3〇7於晶片3〇〇上，並暴露出 部=位於晶片銲墊302上方之球底金屬層306。接著，使用 適當的#刻液’以將部分之潤濕層3〇6c及阻障層3〇6b去 除’而使黏著層3〇6a仍留置於部分之晶片銲墊上302。接
1237860
著’將光阻層307移除’如圖5所示。 接著’如圖6所示，設置另一光阻層3 0 8於晶片3 0 0上， 並形成複數個開口以暴露出未移除阻障層3〇6b及潤濕層 3〇6c之球底金屬層。之後，將銲料填入光阻層3〇8所定義之 開口中，以形成複數個銲料凸塊3〇9。最後，將光阻層3〇8 移除並進行迴銲步驟，以使銲料凸塊3〇9與球底金屬層3〇6 固接（如圖7所示）。 承 之球底 經圖案 而當球 於球底 罩，以 墊上方 中之標 接 有複數 置於晶 露出。 上所述，球底金屬層形成於晶片銲墊上可為圖案化 金屬層或未經圖案化之球底金屬層，當球底金屬先 化’則銲料可藉由印刷之方式設置於球底金屬層上； 底金屬未經圖案化，則銲料可藉由電鍍之方式設置 金屬層上’並可接續藉由已形成之鮮料凸塊為遮 圖案化球底金屬層及移除欲作為導電線接合用之銲 之满濕層及阻障層’惟此步驟可利用凸塊電鑛製程 準步驟來實施，如圖8至圖13所示之步驟。 著，請參照圖8，提供-晶片400，晶片40 0上形成有 :二片銲墊402及保護層4〇3。其*，保護層4〇3係配 片_表面上’用以保護晶片綱表面並使銲塾憎暴 之後，再請繼續參照圖8，依成腺知# ^ ^ W序將組成黏著層404a、阻 障層404b及潤濕層404c之金屬形成
4曰執婊裟外番止/化成於晶片40 0上並覆蓋晶片 #干蟄4ϋ2。接者，設置一光阻層4f)R t ^ ^ 4心於球底金屬層上並定義 出複數個開口以暴露出部分之潤 ^ 卫·疋義 ’同，愚層4 0 4 c。之德，將锃Μ 填入光阻層4 0 5所定義之開口中， 、 以形成複數個銲料凸塊
1237860 五、發明說明（8) 4〇6。當銲料凸塊4〇β是以電 將光阻層405移除。接、著， 方式形成時，&時可先行 合之餘彡,j^ ;斗凸塊4 0 Θ為遮罩並配合適 所示），以來成岡安外+、t 序移除或同時移除（如圖9 請接;濕層40 7c及阻障層·。 10所示），並藉由微影及餘刻之於f片上（如圖 圖案化之光阻層411覆蓋於z案化光阻層41°， 墊上之黏著層404a上。之後，以圈荦化。凸塊406之晶片知 4叫如圖U及圖12所示）耆==;圖案化之黏著層 除计、隹 >、门w 土 * 敢後將圖案化光阻層4 11移 矛〇並進仃迴鲜步驟，以使銲料凸塊4〇 金 4〇7固接（如圖13所示），以完成馨人 口系化火履金屬層 製私而形成本發明之整合打線及覆晶封裝之晶片結構。 f之t t二::例I 2於本發明所述之整合打線及覆晶封 2曰曰片、.。構’不需另於球底金屬上形成供導 合用之阻障層及潤濕層（如鎳金屬層及金層），故不 化製程步驟，更可免除錄金屬層及金層之材料耗費及使0 用。因此，實為解決習知整合打線及覆晶封裝之晶片址 之缺點及其相關製程之最佳方法。 ° 於本實施例之詳細說明中所提出之具體的實施例僅為 了易於說明本發明之技術内容’而並非將本發明狹義地限 制於該實施例，因此’在不超出本發明之精神及以下申請 專利範圍之情況，可作種種變化實施。 胃
1237860 圖式簡單說明 (五）、【圖式之簡單說明】 圖1至圖2為一習知整合打線及覆晶封裝之晶片製程之 剖面示意圖。 圖3為依照本發明較佳實施例之整合打線及覆晶封裝之 晶片結構剖面不意圖。 圖4至圖8為一整合打線及覆晶封裝之晶片製程之剖面 示意圖，顯示為依照本發明較佳實施例之整合打線及覆晶 封裝之晶片結構及製程。 圖8至圖1 3為另一整合打線及覆晶封裝之晶片製程之剖 面示意圖，顯示為依照本發明較佳實施例之整合打線及覆 晶封裝之晶片結構及製程。 【元件符號說明】 100 ： 晶片 102 ： 晶片銲墊 104 ： 保護層 106 ： 球底金屬層 106a 黏著層（鋁金屬層） 106b 阻障層（鎳-飢合金） 106c 潤濕層（銅金屬層） 107a 供打線合用之潤濕層 107b 供打線合用之阻障層 109 ： 光阻層 110 ： 鲜料凸塊
1237860 圖式簡單說明 2 0 0 :晶片 2 0 2 :晶片銲墊 2 0 4 :保護層 2 0 6 :球底金屬層 2 0 6 a :黏著層 2 0 6 b :阻障層 2 0 6 c :潤濕層 2 0 8 :銲料凸塊 3 0 0 :晶片 3 0 2 :晶片銲墊 304 :保護層 3 0 6 :球底金屬層 3 0 6 a :黏著層 3 0 6 b :阻障層 3 0 6 c :潤濕層 3 0 7 :光阻層 3 0 8 :光阻層 3 0 9 :銲料凸塊 400 :晶片 402 :晶片銲墊 4 0 3 :保護層 404a :未圖案化之黏著層 4 0 4b ··未圖案化之阻障層 404c ··未圖案化之潤濕層
第15頁 1237860 圖式簡單說明 4 0 5 :光阻層 - 4 0 6 :銲料凸塊 407:圖案化球底金屬層 ’ 4 0 7a :圖案化之黏著層 4 0 7b :圖案化之阻障層 4 0 7c :圖案化之潤濕層 . 4 1 0 :光阻層 4 11 :圖案化光阻層 ”
第16頁

Claims (1)

1237860 六、申請專利範圍 1 · 一種整合打線及覆晶封裝之晶片製程，包含： 提供一晶片，該晶片上具有一保護層及複數個晶片銲墊， 且該保護層係暴露出該等晶片銲墊； 形成一圖案化球底金屬層於每一該等晶片銲墊上，其中該 圖案化球底金屬層係包含一圖案化黏著層、一圖案化阻 障層及一圖案化潤濕層； 移除設置於該等晶片銲墊之一之上方之該圖案化阻障層及 圖案化潤濕層；及 設置複數個凸塊於未移除該圖案化阻障層及該圖案化潤濕 層之球底金屬層上。 2 ·如申請專利範圍第1項所述之整合打線及覆晶封裝之晶片 製程，其中該圖案化黏著層係為一鋁金屬層。 3 ·如申請專利範圍第1項所述之整合打線及覆晶封裝之晶片 製程，其中該圖案化黏著層係為一鈦金屬層。 4. 如申請專利範圍第1項所述之整合打線及覆晶封裝之晶片 製程，其中該圖案化阻障層係為一鎳釩金屬層。 5. 如申請專利範圍第1項所述之整合打線及覆晶封裝之晶片 製程，其中該圖案化潤濕層係為一銅金屬層。 6.如申請專利範圍第1項所述之整合打線及覆晶封裝之晶片
第17頁 1237860 申請專利範圍 製程’其中該等凸塊係為銲料凸塊 :如申請專利範圍第6項所述之整合打線及覆晶封裝之晶片 製程’更包含一迴銲步驟，以使該等銲料凸塊固接於該圖 案化潤濕層上。 〆 8 ^如申請專利範圍第丨項所述之整合打線及覆晶封裝之晶片 製程’其中该保護層之材質係包含氮化物（nitric)。 9 j如申請專利範圍第1項所述之整合打線及覆晶封裝之晶片 製程’其中該保護層之材質係包含氮化矽（s i 1 i con nitride ) 〇 I 0 ·如申請專利範圍第1項所述之整合打線及覆晶封裝之晶 片製程，其中該保護層之材質係包含磷矽玻璃 (phosphosi1icate glass ， PSG )。 II ·如申請專利範圍第1項所述之整合打線及覆晶封裝之晶 片製程，其中該保護層之材質係包含氧化矽（si licori oxide ) 〇 1 2 ·如申請專利範圍第3項戶斤述之整合打線及覆晶封裝之晶 片製程，更包含設置一金廣於該圖案化黏著層上。
第18頁 1237860 六、申請專利範圍 _______ 13·如申請專利範圍第3項 — 片製程，更包含設置一 4 ’L之整合打線及覆晶封裝之晶 1呂層於該圖案化黏著層上。 14· 一種整合打線及覆晶封 提供一晶片，該晶片上具有一曰曰片製程，包含： 且該保護層係暴露出|亥等:保護層及複數個晶片銲墊， 形成一球底金屬層於每r令y銲墊； 屬層係包含-黏著層、^ =銲墊上、，其中該球底金 設置一凸塊於該等晶片銲 四及一潤濕層； 以該凸塊為遮罩移除夫妯一之上方之球底金屬層上； 形成-圖案= ;障層及潤濕層以 設置一光阻層於未被凸塊覆f曰、< 潤濕層， 之該黏著層上；及 设置於該等晶片銲墊上方 以该凸塊及5亥光阻層兔^ rgl ^ 化黏著層。 遮罩圖案化該黏著層以形成-圖案 T製如二請Λ?圍第14項所述之整合打線及覆晶封裝 片1紅更匕3 一迴銲步驟，以使該等銲料凸塊固接於今 圖案化潤濕層上。 、 1 6·如申請專利範圍第丨5項所述之整合打線及覆晶封裝之晶 片製程，於進行迴銲步驟前，更包含進行去除該光阻層之 步驟。
第19寅 1237860 六、申請專利範圍 1 7.如申請專利範圍第1 4項所述之整合打線及覆晶封装之晶 片製程，其中該圖案化黏著層係為一銘金屬層。 1 8 ·如申請專利範圍第i 4項所述之整合打線及覆晶封裝之晶 片製程’其中該圖案化黏著層係為一鈦金屬層。 1 9.如申請專利範圍第丨4項所述之整合打線及覆晶封裝 日曰 片製程，其中該圖案化阻障層係為一鎳飢金屬層。 2〇·如申請專利範圍第14項所述之整合打線及覆晶封裝之晶 片製程’其中該圖案化潤濕層係為一銅金屬層。 21·如申請專利範圍第14項所述之整合打線及覆晶封裝之晶 片製程’其中該等凸塊係為銲料凸塊。 、曰曰 22·=申請專利範圍第14項所述之整合打線及覆晶封裴之晶 片製程，其中該保護層之材質係包含氮化物（nitride^ 。曰曰 2 3 ·=申睛專利範圍第1 4項所述之整合打線及覆晶封裝之晶 片製程’其中該保護層之材質係包含氮化矽（sUic〇i曰曰 nitride ) 〇 24·如申請專利範圍第丨4項所述之整合打線及覆晶封裝之晶 片製程’其中該保護層之材質係包含磷矽玻璃
第20頁 1237860 六、申請專利範圍 (phosphosilicate glass ’ PSG )。 2 5 ·如申請專利範圍第丨4項所述之整合打線及覆晶封裝之晶 片製程，其中該保護層之材質係包含氧化矽（s Π i c〇n oxide) 〇 2 6 ·如申請專利範圍第丨8項所述之整合打線及覆晶封裝之晶 片製程，更包含設置一金層於該圖案化黏著層上。 2 7 ·如申請專利範圍第丨8項所述之整合打線及覆晶封裝之晶 片製程，更包含設置一鋁層於該圖案化黏著層上。 2 8 · —種整合打線及覆晶封裝之晶片結構，包含： 一晶片，其係具有一主動表面、一保護層、複數個晶片銲 墊，其中該保護層及該等晶片銲墊係形成於該主動表面 上，該保護層係暴露出該等晶片銲墊； 一圖案化黏著層、一圖案化卩且障層及一圖案化潤濕層係依 序設置於該等晶片銲墊之一之上方，其-餘之該等晶片鲜 墊上係只設置有該圖案化黏著層；及 一銲料凸塊，形成於該圖案化潤濕層上。 29·如申請專利範圍第28項所述之整合打線及覆晶封裳之晶 片結構，其中該圖案化黏著層係為一鋁金屬層。 明
1237860 六、申請專利範圍 之 B曰 30.如申請專利範圍第28項所述之整合打線及覆晶封裝 片結構，其中該圖案化黏著層係為一鈦金屬層。 " 31·如申請專利範圍第28項所述之整合打線及覆晶封裝之晶 片結構’其中該圖案化阻障層係為一鎳飢金屬層。 曰曰 32·如申請專利範圍第28項所述之整合打線及覆晶封裝之 片結構，其中該圖案化潤濕層係為一銅金屬層。 33·如申請專利範圍第28項所述之整合打線及覆晶封裝之晶 片結構，其中該等凸塊係為銲料凸塊。 34.如申請專利範圍第28項所述之整合打線及覆晶封裝之 片結構’其中該保護層之材質係包含氮化物（nitride) 〇 3 5 ·如申請專利範圍第2 8項所述之整合打線及覆晶封襞之晶 片結構，其中該保護層之材質係包含氮化矽（s i 1 i c〇n n i t r i d e ) ° a曰 b曰 3 6 ·如申請專利範圍第2 8項所述之整合打線及覆晶封裝之 片結構，其中該保護層之材質係包含構石夕玻璃 (phosphosilicate glass ，pSG) ° 3 7 ·如申請專利範圍第2 8項所述之整合打線及覆晶封裝之
第22頁 1237860 六 silicon 申請專利範圍 ^ 片結構，其中該保護層之讨質係匕含氧化石夕 oxide ) 〇 3 8 ·如申請專利範圍第3 〇項所述之整合打線及覆晶封裝之晶 片結構，更包含設置一金廣於该圖案化黏著層上。 3 9如申請專利範圍第3 〇項所述之整合打線及覆晶封裝之晶 月、、々構，更包含設置一鋁層於該圖案化黏著層上。
第23頁
TW093103550A 2004-02-13 2004-02-13 Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof TWI237860B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW093103550A TWI237860B (en) 2004-02-13 2004-02-13 Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof
US10/876,581 US20050181538A1 (en) 2004-02-13 2004-06-28 Semiconductor device for wire-bonding and flip-chip bonding package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093103550A TWI237860B (en) 2004-02-13 2004-02-13 Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof

Publications (2)

Publication Number Publication Date
TWI237860B true TWI237860B (en) 2005-08-11
TW200527560A TW200527560A (en) 2005-08-16

Family

ID=34836969

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093103550A TWI237860B (en) 2004-02-13 2004-02-13 Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof

Country Status (2)

Country Link
US (1) US20050181538A1 (zh)
TW (1) TWI237860B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473181B (zh) * 2007-12-13 2015-02-11 Unimicron Technology Corp 具電性連接結構之封裝基板及其製法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101278526B1 (ko) 2007-08-30 2013-06-25 삼성전자주식회사 반도체 장치 및 그의 제조 방법, 및 이를 갖는 플립 칩패키지 및 그의 제조 방법
US8698925B2 (en) * 2010-04-21 2014-04-15 Intevac, Inc. Collimator bonding structure and method
KR101295536B1 (ko) * 2012-03-26 2013-08-12 엘지디스플레이 주식회사 터치 스크린 일체형 표시장치 및 그 제조 방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI221334B (en) * 2003-06-30 2004-09-21 Advanced Semiconductor Eng Bumping process
TWI223883B (en) * 2003-06-30 2004-11-11 Advanced Semiconductor Eng Under bump metallurgy structure
TWI221323B (en) * 2003-06-30 2004-09-21 Advanced Semiconductor Eng Bumping process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473181B (zh) * 2007-12-13 2015-02-11 Unimicron Technology Corp 具電性連接結構之封裝基板及其製法

Also Published As

Publication number Publication date
TW200527560A (en) 2005-08-16
US20050181538A1 (en) 2005-08-18

Similar Documents

Publication Publication Date Title
KR100876485B1 (ko) 주석 함량이 많은 땜납 범프의 이용을 가능하게 하는ｕｂｍ층
JP4400802B2 (ja) リードフレーム及びその製造方法並びに半導体装置
US20060094226A1 (en) Bumping process
JP2014511039A (ja) 支持端子パッドを有する半導体チップ
JP3651346B2 (ja) 半導体装置およびその製造方法
US20120326299A1 (en) Semiconductor chip with dual polymer film interconnect structures
TWI230450B (en) Under bump metallurgy structure
US7906424B2 (en) Conductor bump method and apparatus
TWI225280B (en) Bumping process
CN104584206B (zh) 用于互连附着的迹线沾焊料技术
TWI237860B (en) Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof
TW200408095A (en) Chip size semiconductor package structure
CN100350581C (zh) 整合打线及倒装封装的芯片结构及工艺
US6858475B2 (en) Method of forming an integrated circuit substrate
US20070080453A1 (en) Semiconductor chip having a bump with conductive particles and method of manufacturing the same
TWI223883B (en) Under bump metallurgy structure
JP3424164B2 (ja) 半導体装置の製造方法
JP2004072043A (ja) 半導体ウェハ及び半導体チップ並びに半導体装置とその製造方法
CN101442016A (zh) 晶圆凸块结构及制造方法
TWI221323B (en) Bumping process
KR20000019151A (ko) 솔더 범프를 갖는 반도체 칩과 그 제조방법
TWI262567B (en) Bumped wafer structure
TWI252548B (en) Bumped wafer structure
TWI238507B (en) Integrated circuit package substrate with presolder structure and method for fabricating the same
KR100523298B1 (ko) 금 범프가 형성된 반도체 칩과 그 제조방법

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent