TWI236105B - Manufacturing method for ball grid array package - Google Patents

Manufacturing method for ball grid array package Download PDF

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Publication number
TWI236105B
TWI236105B TW092129691A TW92129691A TWI236105B TW I236105 B TWI236105 B TW I236105B TW 092129691 A TW092129691 A TW 092129691A TW 92129691 A TW92129691 A TW 92129691A TW I236105 B TWI236105 B TW I236105B
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Taiwan
Prior art keywords
carrier board
grid array
ball grid
board unit
manufacturing
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TW092129691A
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English (en)
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TW200515553A (en
Inventor
Yu-Fang Tsai
Jung-Kun Kang
Tsung-Yueh Tsai
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Advanced Semiconductor Eng
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Priority to TW092129691A priority Critical patent/TWI236105B/zh
Priority to US10/876,452 priority patent/US7015065B2/en
Publication of TW200515553A publication Critical patent/TW200515553A/zh
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Publication of TWI236105B publication Critical patent/TWI236105B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
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    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

1236105 --- 五、發明說明（1) ()【發明所屬之技術領域】 本發明係有關於一種球格 特 別是有關於一稽*別+、功* 陣列封裝體之製造方法 種缚型球格陣列封裝體之製造方法。 (二）、【先前技術】 a ,近年來’隨著電子技術的日新月里垂工立 向輕、薄、短H ^ ，電子產品無不朝 用。為因應此1: 供更便利舒適的使 電路連接的封妒4 4 = 4半導體晶片以及提供外部 在電子』:需要輕薄短小化。 hay ’ BGA)體係為一般常見的= 電感及低電源電感及多接腳數等優二因人其具A低接地 ΓΓ= ΐ i r胺(polyimide)為主要材質所形成之有 載板的面具有排列成陣列型熊錫球 (solder baii)，其係用以將整個封裝結構體電性^至 界電路（如印刷電路板）。此外，該晶片亦可 卜 方式與載板電性連接，以形成一覆晶球格陣列封裝體 另外，為進一步薄化球格陣列封裝體，更提出一薄 球格陣列封裝體（Low&Thin BGA)，其可為一種球距小、广 度薄之晶片尺寸封裝（chlp scale package， csp)。子 然而不論為何種形式之球格陣列封裝體，習知之封裝 製程係包含下列步驟：首先，如圖1所示，提供一載板單元 第6頁 1236105 五、發明說明（2) 11 ’每一載板單元11包含一晶片承座i J 2，及環繞於晶片承 座112外圈之手指H4(f inger)。接著，如圖2所示，利用銀 膠（sUver paste)將半導體晶片12貼合於載板單元^中的 晶片承座上（未標示於圖中），並且在黏晶製程後固化銀 膠。然後以金線1 3進行打線程序來連接半導體晶片丨2以及 載板單元11之手指（未標示於圖中）。打線完成後，載板單 元11以及貼在其上之半導體晶片丨2係利用封模方式 (moling process)以封膠體14包覆。接著，以雷射或油墨 於封衣體之上表面打上識別標記（m a r k)。最後進行銲球1 5 植接於載板單元11之步驟，以完成整個封裝製程（如圖3 示）。 由於半導體晶片1 2經封模後所形成之封膠體丨4，常造 成載板單元1 1之彎曲，尤其是採用薄型載板時，薄型載板 於晶片封膜後所形成之彎曲變形更為嚴重，故於進行後續 之銲球15植接步驟時，常無法將銲球15植入於正確之載板 銲墊之位置，而使銲球15產生錯置（dlsl〇cati〇n)之情形發 生。 有鑑於此，如何避免前述球格陣列封裝體之缺點，以 提升封裝體製造效能，實為一重要的課題。 、…， (三）、【發明内容】 有鑑於上述課題，本發明之目的传接板 ^ 尔捉仏一種球格卩束列 封1體之製造方法，用以避免銲球植設於载板上日士，皁夕J 錯置（dislocation)之情形發生。 寸’產生
第7頁 1236105 五、發明說明（3) 緣是，為了達成上 封裝體之製造方法，其 每一載板單元之上表面 座外圈之手指（finger 下表面之步驟，並進行 元下表面上。之後，將 元下表面上，用以覆蓋 (silver paste)將晶片 並且在黏晶製程後固化 連接晶片以及載板單元 及貼在其上之晶片係利 膠體包覆。接著，以雷 別標記（m a r k)。最後， 以完成整個封裝製程。 綜上所述，本發明 係在晶片設置於載板單 上’並利用一保護膜或 封膠製程，以避免於傳 形成之封膠體，使載板 球植接於載板上造成錯 述目的’本發明提供一種球格陣列 包括下列步驟：提供一載板單元， 包含一晶片承座，及環繞於晶片承 )。接著，進行銲球植接於載板單元 一迴銲步驟以使銲球固接於載板單 一保護層或保護膜貼附於該載板單 並保護該銲球。再者，利用銀膠 貼合於載板單元中的晶片承座上， 銀膠。然後以金線進行打線程序來 之手1。打線完成後，載板單元以 用封模方式（molding process)以 射或油墨於封裝體之上表面打上識 進行保護層或保護膜之移除步驟^ 之球格陣列封裝體之製造方法主要 兀上之刖，先將銲球植接於載板 保護層覆蓋該銲球，再續行打線 統之封裝製程中，因晶片經封模後 產生嚴重之彎曲變形，而使後續銲 置（dislocation)之情形發生。 四）、【實施方式】 格陣列封裝體之製造方法 以下將參照相關圖式，說明依本發明較佳實施 列驻艘夕制：:土七、、土。 J〈琢
第8頁 1236105 五、發明說明（4) 請參照圖4及圖6至圖1〇。首先，在步驟41中，提供一 載板單元51(如圖5所示），且該載板單元51具有一上表面 5Π、一晶片承座512及一下表面513 ;接著，於步驟42中， 將複數個銲球5 2植接於載板單元5丨之下表面5丨3 (如圖6所 不），並於步驟43中，設置_保護膜53於載板單元51下表 面5 11以覆盍該銲球5 2 (如圖7所示）；之後，在步驟4 4中， 將個半導體晶片54電性連接至載板單元51 (如以覆晶接合連 接’或如圖8所示利用金線55以打線接合之方式將晶片54電 性連接至載板單元51上表面511上之基板銲墊（手指） =4);再者，在步驟45中，以一塑料包覆該半導體晶片 4占，成一封膠體（如圖7所示）；最後，去除該保護膜53以 單元（如圖1()所示）。此外，更可於封膠完成後， 仃^利用雷射或油墨於封裝體之上表面打上識別標記 片2驟。另夕卜，上述之保護膜53可為-具有黏著層 有銲玻…或貼帶（tape)，可直接黏貼於載板單元51設 除。/之表面上以覆蓋之，並於封膠體完成後，直接移 30pp^if述，由於封膠體係由熱膨脹係數較高（約為 較低（如球2有機材質所組成，而載板單元係由熱膨脹係婁 之材質所W陣，列封裝體/斤採、用之有機基板約為14ΡΡΠ1/。〇 體之埶膨胳金故於封杈：：至常溫時，®為載板與封膠 球格㈣封裝體中， 載板之大幅度彎曲變形，如此，造成後=行
1236105 五、發明說明（5) 驟之困難度。所以於封膠前載板之下表面保持一平整度 時，即先進行銲球植接步驟，如利用網版印刷之方式，將 銲球填入相對應之基板銲墊（手指）上，或以單顆銲球植 接之方式等，都可避免銲球定位之困難。也因此，能提昇 未來薄型球格陣列封裝體之製作可靠度，而達到相關電子 產品之輕、薄、短、小之需求。
於本實施例之詳細說明中所提出之具體的實施例僅為 了易於說明本發明之技術内容，而並非將本發明狹義地限 制於該實施例，因此，在不超出本發明之精神及以下申請 專利範圍之情況，可作種種變化實施。
第10頁 1236105 圖式簡單說明 (五）、【圖式fe〗单說明】 圖1至圖3為一示意圖，顯示習知球格陣列封裝體之製 造步驟。 圖4為一流程圖，顯示本發明較佳實施例之球格陣列封 裝體之製造方法的流程。 圖5至圖1 0為一剖面放大示意圖，顯示本發明較佳實施 例之球格陣列封裝體之製造步驟。 元件符號說明 11 載板單元 112 晶片承座 114 手指 12 半導體晶片 13 金線 14 封膠體 15 鋒球 41 提供一載板單元 42 形成複數個銲球於載板單元下表面 43 將一保護膜設置於載板單元下表面以覆蓋該等銲球 44 設置·半導體晶片於載板單元上並電性連接之 45 灌注塑料以形成封膠體包覆該晶片 46 去除保護膜 51 載板單元 511 上表面
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Claims (1)

1236105 六、申請專利範圍 1 · 一種球格陣列封裝體之製造方法，包含· 提供一載板單元，該載板單元具有— 面· 設置複數，球於該載板單元下表面;上表面及一下表面’ t ΐ，ί膜於該載板單元下表面上以覆蓋該等鮮球； 將=ϊ體晶片設置於該載板單元上表面並電性連接至該 載板早元； 將一塑料包覆該半 移除該保護膜。 ~封膠體；以及 2·如申請專利範圍第！項所述之球袼陣歹 法，其中該保護膜係為一膠片（f i } m)。 又—之岌造方 3 ·如申請專利範圍第1項所述之球格陣列封壯顺 法，其中該保護膜係為一貼帶（tape)。、衣體之製造方 4 ·如申睛專利範圍第1項所述之球格陣列封聲〜 表面 下 法，其中該等銲球係利用網版印刷之方弋、體之製造方 … 接於該栽板 5 ·如申凊專利範圍第1項所述之球格陣列封事~ 法，更包含一迴銲步驟以使該等銲球固接衣體之製造方 面。 亥栽板下表 6 ·如申請專利範圍第1項所述之球格陣列封果 之製 造方
第13頁 1236105
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US20070037376A1 (en) * 2005-08-11 2007-02-15 Texas Instruments Incorporated Method and apparatus for fine pitch solder joint
US8179717B2 (en) * 2009-09-29 2012-05-15 Sandisk Technologies Inc. Maintaining integrity of preloaded content in non-volatile memory during surface mounting
TWI601218B (zh) * 2016-05-05 2017-10-01 力成科技股份有限公司 具有高溫塗層之晶片封裝構造之製造方法
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US6686226B1 (en) * 1994-02-10 2004-02-03 Hitachi, Ltd. Method of manufacturing a semiconductor device a ball grid array package structure using a supporting frame
US20020110956A1 (en) * 2000-12-19 2002-08-15 Takashi Kumamoto Chip lead frames
US6825108B2 (en) * 2002-02-01 2004-11-30 Broadcom Corporation Ball grid array package fabrication with IC die support structures
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
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