TW488046B - A process for packaging a window BGA to improve the efficiency of forming solder balls - Google Patents
A process for packaging a window BGA to improve the efficiency of forming solder balls Download PDFInfo
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- TW488046B TW488046B TW090113425A TW90113425A TW488046B TW 488046 B TW488046 B TW 488046B TW 090113425 A TW090113425 A TW 090113425A TW 90113425 A TW90113425 A TW 90113425A TW 488046 B TW488046 B TW 488046B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
488046 五、發明說明(1) 【發明領域】 寇有關於一種增進植球良率之窗口脱封裝過 J程特別係有關於一種包含壓模灌膠步驟之窗口 B G Α封裝 【先前技術】 在美國專利第6, 1 90, 943號「晶片尺寸封裝方法」 t ’ 揭示一種窗口BGA 封裝〔wind〇w baU grid a^」488046 V. Description of the invention (1) [Field of the invention] Kou has a window decapsulation process to improve the yield of ball implantation. In particular, it relates to a window BG Α package that includes a mold filling step. [Previous technology] In the United States Patent No. 6, 1 90, 943 "Chip Size Packaging Method" t 'Reveals a window BGA package [wind〇w baU grid a ^ "
Package〕型態之半導體封裝件及其封裝方法,如第3圖所 不,該半導體封裝件20主要包含有一基板22、一晶片24、 複數個金屬導線32、複數個焊球44及一密封金屬導線32之 保護朦42,其令基板22具有一非導電性之上表面3〇、一具 V電線路之下表面38及一通孔34〔即窗口〕,晶片24係黏 固於基板22之上表面30並使在晶片24活性表面26之焊墊36 裸露於窗口34,以供金屬導線32之連接,而焊球44則接合 於基板22之下表面38,使得半導體封裝件2〇具有窗口BGA 封裝〔或稱為『晶片上基板封裝』·〔〇n Chip〕〕之型態。 如第4圖所示,依該半導體封裝件2〇之封裝方法,首 先提供一基板22,之後在基板22之上表面3〇以網版印刷塗 %—熱塑性黏膠28 ’接著放置一晶片24於基板22之上表面 30,施壓加熱以使晶片24與基板22黏合,再以打線形成金 屬導線32 ’以連接晶片24與基板22,之後形成該保護膠 42,最後再接植焊球44,由於在形成該保護膠42之過程, 特別是以壓模〔molding〕方式形成時,保護膠42會污染Package] type semiconductor package and its packaging method. As shown in FIG. 3, the semiconductor package 20 mainly includes a substrate 22, a wafer 24, a plurality of metal wires 32, a plurality of solder balls 44, and a sealing metal. The protective layer 42 of the wire 32 causes the substrate 22 to have a non-conductive upper surface 30, a lower surface 38 having a V electrical circuit, and a through hole 34 (ie, a window). The chip 24 is fixed on the substrate 22 The surface 30 exposes the pads 36 on the active surface 26 of the wafer 24 to the window 34 for connection of the metal wires 32, and the solder balls 44 are bonded to the lower surface 38 of the substrate 22, so that the semiconductor package 20 has a window BGA Package [or "on-chip package" · [On Chip] type. As shown in FIG. 4, according to the packaging method of the semiconductor package 20, a substrate 22 is first provided, and then the upper surface 30 of the substrate 22 is coated with screen printing—% thermoplastic adhesive 28 ′ and then a wafer 24 is placed. On the upper surface 30 of the substrate 22, heat is applied to make the wafer 24 adhere to the substrate 22, and then a metal wire 32 'is formed by wire bonding to connect the wafer 24 and the substrate 22, and then the protective glue 42 is formed, and finally, a solder ball 44 is connected. As the protective glue 42 is formed in the process of forming the protective glue 42, especially when the protective glue 42 is formed, the protective glue 42 may be contaminated.
第5頁 488046Page 5 488046
基板22之下表面38,影響植球品質,導致焊球44之結合力 不足或電性斷線,因此,如第丨圖所示,在該半導體封裝 件20中,其晶片24之背面〔對應於活性表面26之另一表 、面:〕必須裸露,以供上模具之直接壓迫’否則易產生溢膠 ^染基板22之下表面38之現象,然而卻降低對晶片24之保 【發明目的及概要】 本發明之主要目的在於提供一種窗口 BGA封裝過程, 利用在壓模灌膠之前先將複數個焊球形成於電路基板之下 表面,以達到增進植球良率之功效。 依本發明之增進植球良率之窗口 BGA封裝過程,其包 含之步驟依序有: a) 提供一電路基板,該電路基板具有一上表面、一下 表面及至少一窗口; b) 黏固至少一晶片於電路基板之上表面,每一晶片具 有一積體電路形成面以及位在積體電路形成面之複 數個焊塾’當晶片之積體電路形成面朝向電路基板 並黏合時’該複數個焊墊係裸露於上述電路基板之 窗口; c) 透過該窗口電性連接晶片與電路基板; d) 形成複數個焊球於電路基板之下表面;及 e) 形成一絕緣膠體於電路基板之窗口。 【發明詳細說明】 ”月參閱所附圖式,本發明將列舉以下之實施例說明··The lower surface 38 of the substrate 22 affects the quality of the ball implantation, resulting in insufficient bonding force of the solder ball 44 or electrical disconnection. Therefore, as shown in FIG. 丨, in the semiconductor package 20, the back surface of the wafer 24 [corresponds to On the other surface and surface of the active surface 26:] It must be exposed for direct compression of the upper mold. Otherwise, the phenomenon of overflowing and staining the lower surface 38 of the substrate 22 is easy to occur, but the protection of the wafer 24 is reduced. And summary] The main purpose of the present invention is to provide a window BGA packaging process, in which a plurality of solder balls are formed on the lower surface of the circuit substrate before the die is filled with the glue, so as to achieve the effect of improving the yield of the ball. According to the present invention, the window BGA packaging process for improving the yield of ball implantation includes the following steps: a) providing a circuit substrate having an upper surface, a lower surface and at least one window; b) fixing at least A wafer is on the upper surface of the circuit substrate, and each wafer has an integrated circuit formation surface and a plurality of solder pads located on the integrated circuit formation surface. When the integrated circuit formation surface of the wafer faces the circuit substrate and is bonded, the plurality Each pad is exposed on the window of the circuit substrate; c) the chip and the circuit substrate are electrically connected through the window; d) a plurality of solder balls are formed on the lower surface of the circuit substrate; and e) an insulating gel is formed on the circuit substrate window. [Detailed description of the invention] With reference to the attached drawings, the present invention will enumerate the following embodiment descriptions ...
Hi齡,Hi age,
第6頁 488046 五、發明說明(3)Page 6 488046 V. Description of the invention (3)
第1圖為以本發明之窗口 BG A封裝過程製得之半導體封 裝截面圖’而第2圖為依本發明之窗口BGa封裝過程之方塊 流程圖。 如第1圖所示,由本發明製備之窗口 BGA封裝件工〇 .〔window Ball Grid Array package〕係主要包含有一晶Fig. 1 is a cross-sectional view of a semiconductor package made by the window BG A packaging process of the present invention 'and Fig. 2 is a block flow chart of the window BGa packaging process according to the present invention. As shown in Figure 1, the window BGA package manufactured by the present invention. [Window Ball Grid Array package] mainly contains a crystal
片11、一基板12、複數個金屬導線i3、一絕緣膠體15及複 數個焊球14,其中晶片丨丨具有一形成有積體電路元件之表 面’並在該表面形成複數個焊墊丨π ;而基板12係為一印 刷電路板或陶瓷電路板並呈現有單層或多層之電路圖案, 該基板12包含有一上表面121、一下表面122及一貫通上卡 表面之窗口17,上表面121係可供黏膠16黏固晶片u,而 晶片11形成有積體電路元件之表面係朝向該上表面121黏 合而使其焊墊lu裸露於該窗口17 ;金屬導線13係内部電 性連接晶片11與基板! 2,透過窗口 1 7由晶片11焊墊1J j連 接至在基板12下表面122之連接墊;絕緣膠體15係為一種 熱固性之絕緣填充劑,以壓模〔molding〕方式形成於基 板12之窗口 17及上表面121處,以密封金屬導線13及晶片 11 ;焊球1 4係為一種鉛錫合金或其它金屬焊接材料,形成 於基板12之下表面122,並且部份之焊球14係導通至對應 晶片11之焊墊111。 . ¥上述之南口 BGA封裝件10以本發明之窗口 封裝過 程製備時,具有增進植球良率之功效,其步驟依序包含 有··Sheet 11, a substrate 12, a plurality of metal wires i3, an insulating gel 15 and a plurality of solder balls 14, wherein the wafer has a surface on which integrated circuit elements are formed, and a plurality of solder pads are formed on the surface. The substrate 12 is a printed circuit board or a ceramic circuit board and presents a single-layer or multilayer circuit pattern. The substrate 12 includes an upper surface 121, a lower surface 122, and a window 17 penetrating the upper card surface. The upper surface 121 Adhesive 16 can be used to fix the chip u, and the surface of the chip 11 on which the integrated circuit elements are formed is bonded toward the upper surface 121 so that the bonding pad lu is exposed in the window 17; the metal wire 13 is internally electrically connected to the chip 11 with substrate! 2. Through the window 17 is connected by the wafer 11 solder pad 1J j to the connection pad 122 on the lower surface 122 of the substrate 12; the insulating gel 15 is a thermosetting insulating filler, which is formed on the window of the substrate 12 by means of molding. 17 and the upper surface 121 are sealed with the metal wire 13 and the wafer 11; the solder ball 14 is a lead-tin alloy or other metal soldering material, formed on the lower surface 122 of the substrate 12, and part of the solder ball 14 is conductive To the pads 111 corresponding to the wafer 11. ¥ The above-mentioned south mouth BGA package 10 is prepared by the window packaging process of the present invention, and has the effect of improving the yield of ball implantation. The steps include:
第7頁 488046 五、發明說明(4) 路基板12具有一上表面121、一下表面122及至少一窗口 17 ; 傻’黏固晶片」5 2,係將至少一晶片11黏固於電 路基板12之上表面121,每一晶片11具有一積體電路形成 面以及位在積體電路形成面之複數個焊墊ui,當晶片u 之積體電路形成面朝向電路基板12並黏合時,該複數個焊 墊111係裸露於上述電路基板12之窗口 I?; 接著’ 「電性連接」53係先將電路基板12翻轉,透過 該固口 1 7電性連接晶片u與電路基板j 2,在本貫施例宁係 將複數個金屬導線13連接晶片丨丨之焊墊U1至電路基板12 之下表面122 ’或是以TAB引腳之熱壓合完成電性連接; 之後,「形成焊球」54係形成複數個焊球14於電路基 板1 2之下表面1 2 2 ’通常有印刷、模具對位接合等方式形 成焊球;及 然後’形成絕緣膠體」5 5係以印刷塗施或壓模灌膠 等技術形成一絕緣膠體15於電路基板12之窗口 17,以密封 金屬導線1 3 ’在本實施例中,係將電路基板1 2與晶片u之 組合構造以模具壓合灌膠而形成該絕緣膠體丨5,使該絕緣 膠體1 5密封晶片11而具有較佳之保護性,此外,在實際大 里生產時,該電路基板12係大面積地一體成型有複數個封 裝單元,以同時封裝處理多個晶片u,並在「形成絕緣膠 體」55後,加以切割成多個分離之窗口BGA封裝件1〇。 因此丄本,明之窗口 BGA封裝過程係在「形成絕緣膠 體」55之前先行「形成焊球」54,在電路基板12之下表面Page 7 488046 V. Description of the invention (4) The circuit substrate 12 has an upper surface 121, a lower surface 122, and at least one window 17; a silly 'adhesive chip' 5 2 is a circuit board 12 which is adhered to at least one chip 11 On the upper surface 121, each wafer 11 has an integrated circuit formation surface and a plurality of pads ui located on the integrated circuit formation surface. When the integrated circuit formation surface of the wafer u faces the circuit substrate 12 and is bonded, the plurality of The individual pads 111 are exposed in the window I of the circuit board 12 above; then, "electrical connection" 53 first turns the circuit board 12 over, and electrically connects the chip u and the circuit board j 2 through the solid opening 17, in In the present embodiment, the plurality of metal wires 13 are connected to the bonding pad U1 of the wafer 丨 to the lower surface 122 of the circuit substrate 12 or the electrical connection is completed by thermocompression bonding of the TAB pin; after that, "form a solder ball "54 is to form a plurality of solder balls 14 on the lower surface of the circuit board 1 2 1 2 2 'Usually printing, mold alignment bonding and other methods to form solder balls; and then' form insulation colloids' 5 5 is to apply by printing or Forming an insulating gel 15 The window 17 of the substrate 12 is sealed with a metal wire 1 3 ′. In this embodiment, the combined structure of the circuit substrate 12 and the wafer u is formed by a mold compression molding to form the insulating gel 丨 5, so that the insulating gel 1 5 The sealed wafer 11 has better protection. In addition, in actual production, the circuit substrate 12 is integrally formed with a plurality of packaging units in a large area to package and process multiple wafers u at the same time. After 55, it is cut into a plurality of separate window BGA packages 10. Therefore, the copying process of the BGA package of Mingzhi Window is "formed a solder ball" 54 before the "formation of the insulating gel" 55, on the lower surface of the circuit substrate 12.
Μ 第8頁Μ page 8
488046 五、發明說明(5) 122在尚未受到絕緣膠體15之污染前,將複數個焊球丨4形 成於電路基板12之下表面122,使得焊球η可不受絕緣膠 體15之影響而焊接於下表面122,即使後續之「形成絕緣 =體」55過程中有溢膠之現象亦不影響焊球14對電路基板 1 2之結合性,達到增進植球良率之功效。 者為ΐ本Ϊ明之保護範圍當視後附之申請專利範圍所界定 者為準,任何熟知此項技藝者, 1疋 範圍内所作之任何變化與修改 :月之精神和 圍。 7屬於本發明之保護範488046 V. Description of the invention (5) 122 Before the plurality of solder balls 丨 4 are formed on the lower surface 122 of the circuit substrate 12 before being polluted by the insulating gel 15, the solder balls η can be soldered to the insulating gel 15 without being affected by the insulating gel 15 The lower surface 122 does not affect the bonding of the solder ball 14 to the circuit substrate 12 even if there is an overflow of glue during the subsequent "formation of the insulator = body" 55, and the effect of improving the yield of the ball is achieved. This is the scope of protection of the original copy of the Ming Dynasty, which shall be determined by the scope of the attached patent application. Anyone who is familiar with this skill will make any changes and modifications within the scope: the spirit and scope of the month. 7 belongs to the protection scope of the present invention
【圖式說明】 第1圖·以本發明之窗口BGA封裝過程製得之半導體封裝 截面圖; 圖.·依本發明之窗口BGA封裝過程之方塊流程圖; 圖·以美國專利第6, 1 90, 943號「晶片尺寸封袭方 法」製得之半導體封裝截面圖;及 第4圖:美國專利第6, 1 90, 943號「晶片尺寸封裝方法 之步驟流程圖。 」 【圖號說明】 10 窗口 BGA封裝件 11 晶片 111 焊墊 12 基板 121 上表面 122 下表面 13 金屬導線 14 焊球 15 絕緣膠體 16 黏膠 17 窗口 20 半導體封裝件 22 基板 24 晶片 26 活性表面 28 熱塑性黏膠 30 上表面 32 金屬導線 34 通孔 36 焊墊 38 下表面 42 保護膠 44 焊球 51 提供電路基板 52 黏固晶片 53 電性連接 54 形成烊球 55 形成絕緣膠體[Illustration of the drawings] Figure 1 · Sectional view of a semiconductor package made by the window BGA packaging process of the present invention; Figure. · Block flow chart of the window BGA packaging process according to the present invention; Figure · U.S. Patent No. 6, 1 Cross-sectional view of a semiconductor package made by "Chip Size Packaging Method" No. 90, 943; and Fig. 4: US Patent No. 6, 1 90, 943 "Process Flow Chart of Chip Size Packaging Method." [Explanation of Drawing Number] 10 Window BGA package 11 Wafer 111 Solder pad 12 Substrate 121 Upper surface 122 Lower surface 13 Metal wire 14 Solder ball 15 Insulating gel 16 Adhesive 17 Window 20 Semiconductor package 22 Substrate 24 Wafer 26 Active surface 28 Thermoplastic adhesive 30 Upper surface 32 Metal wire 34 Through hole 36 Pad 38 Lower surface 42 Protective glue 44 Solder ball 51 Provide circuit board 52 Adhesive chip 53 Electrical connection 54 Form ball 55 Form insulating gel
第10頁Page 10
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TW090113425A TW488046B (en) | 2001-05-28 | 2001-05-28 | A process for packaging a window BGA to improve the efficiency of forming solder balls |
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TW090113425A TW488046B (en) | 2001-05-28 | 2001-05-28 | A process for packaging a window BGA to improve the efficiency of forming solder balls |
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- 2001-05-28 TW TW090113425A patent/TW488046B/en not_active IP Right Cessation
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