TWI236053B - Method of selectively etching HSG layer in deep trench capacitor fabrication - Google Patents
Method of selectively etching HSG layer in deep trench capacitor fabrication Download PDFInfo
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- TWI236053B TWI236053B TW092133002A TW92133002A TWI236053B TW I236053 B TWI236053 B TW I236053B TW 092133002 A TW092133002 A TW 092133002A TW 92133002 A TW92133002 A TW 92133002A TW I236053 B TWI236053 B TW I236053B
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- 238000000034 method Methods 0.000 title claims abstract description 76
- 239000003990 capacitor Substances 0.000 title claims abstract description 33
- 238000005530 etching Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 69
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 69
- 239000010703 silicon Substances 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004575 stone Substances 0.000 claims description 13
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims description 2
- 239000002245 particle Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims 4
- 239000012535 impurity Substances 0.000 claims 3
- 230000000873 masking effect Effects 0.000 claims 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims 1
- 241001529936 Murinae Species 0.000 claims 1
- 229910002651 NO3 Inorganic materials 0.000 claims 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 claims 1
- 241001674048 Phthiraptera Species 0.000 claims 1
- 238000012271 agricultural production Methods 0.000 claims 1
- 229910052804 chromium Inorganic materials 0.000 claims 1
- 239000011651 chromium Substances 0.000 claims 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 22
- 229910052785 arsenic Inorganic materials 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- -1 phosphorus ion Chemical class 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 241000465531 Annea Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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Description
1236053 五、發明說明(1) 【發明所屬之技術領域】 本發明是有關於一種深渠溝電容器之製法,且特別是 有關於一種選擇性去除深渠溝矽基底上之半球狀;5夕晶粒 (Hemispherical Silicon Grain; HSG)層的方法,係利用 電漿摻雜(pi asma doping)之方式將深渠溝上半部之半球 狀矽晶粒層之片電阻(sheet resistance)降低,以利於後 續進行之半球狀矽晶粒層蝕刻製程時不會傷及深渠溝之石夕 基底材質。 【先前技術】 目前廣泛使用之動態隨機存取記憶體(Dynamic Random Access Memory; DRAM)中的電容器係由兩導電層 表面(即電極板)隔著一層絕緣物質而構成,該電容器儲 存電射之月b力係由絕緣物質之厚度、電極板之表面積及絕 緣物質的電氣性質所決定。隨著近年來半導體製程設計皆 朝著縮小半導體元件尺寸以提高密度之方向發展,記憶體 中記憶胞(memory cell)的基底面積必須不斷減少使積體 電路能容納大量記憶胞而提高密度,但同時,一方記 ,電容之電極板部分必須有足夠之表面積以儲存充足的電 何,其次,更進一步配合使用高介電質介電材料(high_k dielectric materials)使記憶胞之電容量大增。然而隨 著DRAM體積的縮小化,深渠溝型(deep什⑽仏type)電容 器便被廣泛地應用在DRAM中。為達成上述足夠之表面積, 一種利用半球狀矽晶粒(H㈣ispherical SiH⑶n GFain; HSG)之可行技術即被用來廣增渠溝式(trench)電容器電極
1236053 五、發明說明(2) 板之表面積。於美國專利第6 1 77 6 9 6號、6 53787 2號及 65 5 543 0號皆曾說明了於渠溝式(trench)電容器内形成半 球狀矽晶粒(HSG )層之應用。 請參閱第1 A至1 I圖,其顯示習知之應用半球狀矽晶粒 (HSG)層製程於深渠溝電容器之應用。首先,如第丨A圖所 示’提供一半導體矽基底1〇,其包含有一墊氧化層12(pad oxide)、墊氮化層i4(pad nitride)、一深渠溝DT及一領 型介電層1 6於該深渠溝DT上半部側壁。於該深渠溝DT側壁 及底部形成一钱刻終止層(e t c h s t ο p 1 a y e r) 1 5,例如氧 化層。 其次’清參照第1 B圖,於該餘刻終止層1 5上沉積一非 晶石夕層1 7。然後,如第1 c圖所示,施以一磷離子摻雜2 〇於 適當之濃度、流量及時間於該非晶矽層1 7上形成一摻雜絕 緣層而使得該非晶矽層1 7原處(i n-s i tu)生成半球形晶粒 石夕(HSG)層22,其目的為增加深渠溝dT之表面積。 、、之後,請參照第1D圖,形成一第一光阻層26填入該深 渠溝DT,然後凹蝕該第一光阻層2 6以留下預定深度的第一 光阻層2 6在深渠溝DT下半部。接著,以凹蝕第一光阻層2 6 當作罩幕將深渠溝DT上半部之半球狀矽晶粒(HsG )層2 2蝕 刻去除。在蝕刻過程中,由於深渠溝矽基底對半球形晶粒 石夕(HSG )層之#刻選擇比很低,需要一蝕刻終止層作為緩 衝以隔絕並保護深渠溝矽基底。後續,請參照第丨E圖,再 以蝕刻方式將深渠溝上部暴露於光阻層上之蝕刻終止層i 5 去除。之後,再將第一光阻層26從深渠溝])了中去除。曰 0593-A40001TWF(N1);92069;YYHSU.ptd 第6頁 1236053 五 發明說明(3) 之後,請參照第1 F圖,沉積一砷玻璃(ASG )層2 8於該 深渠溝DT底部及側壁。之後,重複先前製程,再形成一第 一光阻層30於上述沉積於深渠溝DT底部及側壁之砷玻璃層 j上,然後進行該第二光阻層3〇凹蝕,留下預定深度的第 二光阻層30在深渠溝DT下半部。接著,請參照第“圖,以 凹蝕之第二光阻層30當作罩幕將深渠溝DT上半部之砷玻螭 層28蝕刻去除。而殘留之第二光阻層3〇也於後續去除之。 ,續,請參照第1 Η圖,於深渠溝底部及側壁上形成— 覆蓋氧化層32(cap oxide)。接著,如第π圖所示,進行 熱製私使砷玻璃層28中之砷原子擴散至深渠溝DT下方區 =,而形成一n+型擴散區34 ,以用來作為深渠溝電容器36 $埋入電極板(buried plate)34。最後,再將深渠溝Μ ?二玻Λ·及覆蓋氧化層32蚀刻去除。此即半球狀石夕 曰曰拉(HSG)層於深渠溝電容器36之習知製作。 六m ^ ^击於上述習知之半球狀矽晶粒(HSG)層深渠溝電 ==中之步驟比較繁複,不僅需用到二道(steps)J 塗佈/凹ϋ製程’亦須另加 果渠溝石夕基底與半球狀雜(HSG)。;;:= 粒⑽G)層深渠溝電容器製程之所以較冗長^ 為t免將半球狀石夕晶粒(HSG)層|接形 内側壁而接觸到深渠溝 ^ 基底之物理性質盘半=基底/其中原因係由於單曰曰“夕 上述_ |對1 # /、 矽晶粒(MO層十分相近,因此 上这一者對㈣之選擇比亦趨於—致 _ 深渠溝内側壁上部半球狀…⑽)層银刻過程時,進:
1236053 五、發明說明(4) 可避免地、,深渠溝内側壁之矽基底亦會因蝕刻而損傷,甚 或造成洙渠溝開口擴大,進而造成次臨界電壓(sub_vt)漏 損的問題。 、此問題雖如前述習知之技藝以一蝕刻終止層形成於深 渠溝側壁之矽基底與半球狀矽晶粒(HSG)層之間以其克服 上述問題。然而,此舉不僅增加製程複雜性,令人遺撼的 是f使電容器電容量下降’其因歸諸於此蝕刻終止層往往 於深渠溝下部之埋入電極板(buried plate)内形成一寄生 電,(paraSltlc capacitance)而影響了整個電容器之電 容夏。 【發明内容】 有鑑於此,本發明的目的在於提供一 器製程中,選擇性去除半球狀矽曰 .木杲溝電谷 suic〇“rain; HSG)層而完V:/r:;sphericai 矽基底的方法。 s而几正無知地保留深渠溝側壁之 此外,本發明之另一目的是提供一 狀矽晶粒層的方法,其以转立 、擇『生去除半球 述之雷將槔雜彳τ 1特思调製之酸蝕刻溶液,配合上 迷之尾水務雜(p lasma d〇Di ησ、制如 ^ , 工 晶粒(HSG)層蝕刻去除。 1耘,有效地將半球狀矽 本發明之第三目的係在提一 π 作,其在製作半球狀石夕晶粒(_/=溝電谷器之製 i_ntatlon)方式形成一埋直 oxide),以便後續形成半球狀 (collar /日日粒(H S G)層過程時,當
0593 -A40001TWF(N1);92069;YYHSU.p t d 第8頁 1236053 五、發明說明(5) 作一阻障層(barrier layer)以阻隔(bi〇ck)摻雜物 (dopant)因熱製程而擴散至深渠溝侧壁之美麻 最後,本發明因上述新穎之製程也因此^效地簡化 習知之半球狀矽晶粒(HSG)層於深渠溝電容器之製程。匕了 ^達f上述目的,本發明係提供—種選擇性去'除半球 狀矽晶粒層的方法及深渠溝電容器之製作,藉由進行—^ 漿摻雜(plasma doping)製程而將半球狀矽晶曰粒(hsg)層表 面之片電阻(sheet resistance)降低,進而使半球狀石^ : 粒(HSG)層之蝕刻率(etch rate)增加,而較深渠溝側壁: 矽基底易於蝕刻去除。本發明之方法包括下列步驟·· ^ 先,於一半導體矽基底上形成一墊氧化層、墊氮化層I 一 深渠溝。之後,形成一埋入介電層(]3Uried dieiectr^c layer)於該深渠溝上半部内側壁。形成一半球狀矽晶 (HSG)層於該深渠溝内側壁及底部以增加深渠溝之表面 積。形成一摻雜絕緣層於該深渠溝並覆蓋於該半球狀石夕晶 粒(HSG)上。之後,形成一光阻層填滿該深渠溝,凹蝕該曰曰 光阻層至深渠溝内一預定深度並去除部份暴露於光阻層/之 摻雜絕緣層。電漿摻雜於該暴露於光阻層表面之半球狀石夕 晶粒(HSG)層以形成一電漿摻雜層,隨後再蝕刻去除該電 槳摻雜層以完成選擇性去除半球狀矽晶粒層的方法。形成 一覆蓋氧化層(c a ρ ο X i d e )於該深渠溝底部及側壁。接 著,進行一熱製程以形成一深渠溝電容器的埋入電極板 (buried plate)。最後,再餘刻去除该冰渠溝表面之覆蓋 氧化層及摻雜絕緣層。
0593 -A40001TWF(N1);92069;YYHSU.p t d 第9頁 1236053 五、發明說明(6) 【實施方式】 請參閱第2A至2H圖,其顯示本發明深渠溝電容器製程 之剖面示意圖。 首先,如第2A圖所示,提供一半導體矽基底1〇〇,其 包含以加熱氧化法(t h e r m a 1 ο X i d a t i ο η)形成一例如厚度 30〜50埃之墊氧化層120(pad oxide layer)、以低壓化學 氣相沉積法(LPCVD)形成一例如厚度1 50 0〜2200埃之墊氮化 層140(pad nitride layer)及一深渠溝DT。之後,藉由離 子佈植(ion implantation)320 方式,以一例如0.5 〜2E18 佈植濃度/50〜70 Kev佈植能量之氧離子佈植(〇+ implantation) 3 2 0參數,輔以傾斜例如8〜12度(最 佳值約1 0度)之佈植角度,再加以一高溫1 〇 〇 〇〜J i / 5 0〜9 0秒熱製程’例如一熱退火(a n n e a η n g ),以形成一 例如厚度300〜40 0埃之埋入介電層(buried dielectric layer)160於該深渠溝DT内側壁上半部之矽基底上。使用 此製程之目的為:1 ·以便後續形成半球狀矽晶粒(HSG )層 過程時’當作一阻障層(barrier layer)以阻隔(block)摻 雜物(dopant)因熱製程而擴散至深渠溝側壁之矽基底内 部’以確保接合面(junction)不致發生反轉效應(adverse effect)。2·由於該埋入介電層之厚度相當薄,故於後續 之諸多熱製程中,其有較寬裕之熱預算“乜”關丨budget) 而不致使膜厚過厚而壓縮元件之空間,而該適當厚度之埋 入介電層亦可有效地壓制電容元件之漏電流(leakage current)問題 〇
0593-A40001TWF(N1);92069;YYHSU.p t d 1236053 五、發明說明(7) 接著,如第2 B圖所示,以低壓化學氣相沉積法 (LPCVD)於5 0 0〜5 5 0 °C順應性沉積一半球狀矽晶粒(HSG)層 2 2 0以覆盍该深渠溝D τ内側壁及底部,其目的為增加深渠 溝DT之表面積,以期增加後續製作之深渠溝電容器之電容 量。隨後,如第2C圖所示,以低壓化學氣相沉積法 (LPCVD)順應性沉積一例如厚度2 50〜380埃之摻雜絕緣層 (doping dielectric layer) 240,例如一砷玻璃(ASG) 層’以覆蓋該半球狀矽晶粒(HSG )層2 2 0。 之後’如第2D圖所示,以旋轉塗佈(spin-coat)方式 形成一遮蔽層(mask layer) 26 0,例如一光阻層,填滿該 深渠溝’並凹蝕該遮蔽層26〇至深渠溝DT内一預定深度以 疋義後續將形成之埋入電極板之位置。接著,以非等向性 乾姓刻法將深渠溝DT内側壁上部之未被該遮蔽層2 6 〇覆蓋 之摻雜絕緣層2 4 0去除。 接下來’請參考第2E圖,暴露於光阻層之深渠溝上半 部的半球狀矽晶粒(HSG)藉由一離子摻雜34〇,例如硼(B+) 以形成一電漿摻雜反應,以佈植例如丨E丨7〜丨E丨9 cm_3之製程 條件而形成一電漿摻雜層(plasma d〇ping layer)36〇。其 目的為利用上述製程將半球狀矽晶粒(HSG)層22〇表面之片 電阻(sheet resistance)降低,進而使其之蝕刻率提高。 此2將電漿摻雜層360與深渠溝矽基底丨〇〇對於蝕刻液之蝕 刻k擇比(etching selectivity)從原先無摻雜時之趨近 值(j : 1)拉開到摻雜後至少i : 2〇 (較佳可達1 : 3〇),而 使得電漿摻雜層36 0之蝕刻速度比深渠溝矽基底丨〇〇來得快
1236053 五、發明說明(8) 速而易於去除,且不會使深渠溝矽基底受損。 後續’請參考第2F圖,配合上述之電漿摻雜(plasma doing) 340製程,以特意調製之混酸蝕刻溶液,例如一氫 氟酸(HF) ··硝酸(HN〇3) ··醋酸(CH3C〇〇H)以卜! · 5 ·· 3 〜3· 3 ·· 8〜8 · 2 (最佳值} ·· 3 ·· 8 )之比例調配,藉由濕蝕刻方式將暴 露於光阻層2 6 0外之電漿摻雜層3 6 0 (即低阻值半球狀矽晶 粒(HSG)層))蝕刻去除。之後,再去除殘留之遮蔽層26〇。 接下來,請參考第2G圖,於深渠溝之暴露表面上以電 漿加強化學氣相沉積法(PECVD)形成一覆蓋氧化層28〇(cap oxide),例如四乙氧基矽烷(TE〇s),覆蓋於該深渠溝〇丁上 表面,底部及側壁。最後,請參考第2H圖,進行一熱製 私例如一熱退火(anneal ),俾使摻雜絕緣層24〇中之砷 t I f ί ΐ '木渠溝DT下方區域,而形成1+型擴散區30 0, 以用來作為深渠溝電容器32〇的埋入電極板(buried 形成之覆蓋氧化層280之目的係用來確 =擴=00與後續製作之埋入帶外擴散區域之間的絕 ;Γΐ。ΐ ί之;Γ向性濕㈣方式⑽F_dl P+DHF)將 I 絕緣層24°及覆蓋氧化層28°去除。至 【本=:;=】器之下電極(b。— 發明擇性去除半球狀矽晶粒層的方法而言’本 形成1 · μ於H半球狀矽晶粒層之前’以氧離子佈植方式 形成一埋入介電層以取技羽▲ ^ V丨丨但乃八 代白知之領型介電層,以便後續形 第12頁 0593-A4000lTWF(Nl);92069;YYHSU.ptd 1236053 五、發明說明(9) 成半球狀矽晶粒層過程時,去 — 熱製程而擴散至深渠溝側,:::阻障層a阻隔摻雜物因 致發生反轉效應(adv⑽二'基底内㈣確保接合面不 電層之厚度相當薄,故於後續e c )二,=卜,由於該埋八介 :之熱預算而不致使膜厚過厚’其有較寬 題。 ,政地壓制電容元件之漏電流問 2· 藉由進行一電漿摻雜制和& μ, 面之片電阻降低,進而使半球半/之^曰^層表 而較深渠溝側壁之矽基底易 "蝕」革乓加, 去除半球狀矽晶粒層而完整盔損1 。疋為一種選擇性 底的方法。 凡整無知地保留深渠溝側壁之矽基 3以特意調製之酸蝕刻溶液’配合上述之電漿 製釭,有,地將半球狀矽晶粒層蝕刻去除。 ” 4.習知之半球狀矽晶粒(HSG)層深渠溝電容器製 =驟比較繁複,不僅需用到二道(steps)之光阻塗f佈= ^ ’亦須另加一道蝕刻終止層製程來隔絕深渠溝矽基 氐^球狀矽B曰粒(Η%)。而本發明只需一道光阻塗佈/凹 钱製私且不需任何餘刻終止層。 —雖然本發明已以較佳實施例揭露如上,然其並非用以 限^本务明,任何熟習此技藝者,在不脫離本發明之精神 和耗圍内,當可作些許之更動與潤 範圍當視後附之申請專利範圍所界定者為準。 保濃 第13頁
0593-A40001TWF(Nl);92069;YYHSU 1236053 圖式簡單說明 為使本發明之上述目的、特徵和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 圖示說明: 第1 A- 1 I圖為習知之半球狀石夕晶粒層於深渠溝電容器 之製作剖面圖。 第2 A-2H圖為本發明之半球狀矽晶粒層於深渠溝電容 器之製作剖面圖。 【符號說明】 習知技術: 矽基底〜1 0 ; 深渠溝〜DT ; 墊氧化層〜1 2 ; 塾氮化層〜1 4 ; 非晶石夕層〜1 7 ; 領型介電層〜1 6 ; I虫刻終止層〜1 5 ; 第一光阻層〜26 ; 第二光阻層〜30 ; 離子摻雜〜2 0 ; 半球形晶粒矽(HSG)層〜22 ; 砷玻璃(ASG)層〜28 ; 覆蓋氧化層〜32 ; n+型擴散區、埋入電極板〜3 4 ;
0593 -A40001TWF(N1);92069;YYHSU.p t d 第14頁 1236053 圖式簡单說明 深渠漠電容器〜3 6。 本發明技術: 矽基底〜1 0 0 ; 深渠溝〜DT ; 塾氧化層〜120 ; 塾氮化層1 4 0 ; 埋入介電層〜160 ; 氧離子佈植〜3 2 0 ; 半球形晶粒矽(HSG)層〜2 2 0 ; 摻雜絕緣層〜2 4 0 ; 遮蔽層〜2 60 ; 離子摻雜〜3 40 ; 電漿摻雜層〜3 6 0 ; 覆蓋氧化層〜280 ; n+型擴散區、埋入電極板〜3 0 0 ; 深渠溝電容器〜3 2 0。
0593 -A40001TWF(N1);92069;YYHSU.p t d 第15頁
Claims (1)
- I236053步 案號921330⑽ 申請專利範圍 1. 一種選擇性去除半球狀 驟: 日日粒層的方法,包括下列 提供一半導體矽基底,其包 泪 形成一埋入介電層於$ m 木溝, 电尽於孩渠溝側壁上部· 順應性沉積一半球狀矽晶粒 順應性沉積-摻雜絕緣層於;半;;=側壁及底部; 形成-遮蔽層填入該渠=該=夕晶粒層上; 定深度,m出部份該掺雜絕緣声._該錢層至一預 球狀ΐ = ί被遮蔽層覆蓋之推雜絕緣層,露出部分該半 離子摻雜露出之該半球狀矽θ 雜層於該深渠溝頂部及上,以形成-電漿摻 之敍半球狀石夕晶粒層對渠溝石夕基底以大U 雜層“k#比,蝕刻去除該於渠溝頂部及上侧壁之電漿摻 申請專利範圍第1項所述之選擇性去除半球狀石夕 曰曰粒層的方法,其中該埋入介電層為一氧化層。 曰、,3.如申請專利範圍第2項所述之選擇性去曰除半球狀矽 :粒層的方法,其中該埋入介電層係以氧離子佈植方式形 成。 4 ·如申請專利範圍第1項所述之選擇性去 晶粒層的方法,其中該電漿摻雜層係以硼離子佈植方式形 成。 5 ·如申明專利範圍苐1項所述之選擇性去除半球狀石夕1236053 _ 案號 92133002 六、申請專利範圍 晶粒層的方法,其中形成該電漿摻雜層之佈植條件為 1E17〜1E1 9cm-3。 曰6·如申請專利範圍第1項所述之選擇性去除半球狀矽 晶粒層的方法,其中去除該深渠溝頂部及上 雜層的方法為一濕蝕刻法。 之電水摻 7·如申請專利範圍第6項所述之選擇性去除半球狀矽 ::粒層的方法,其中該濕蝕刻法之蝕刻液為氫氟酸:硝 酉夂·醋酸以1〜1 · 5 : 3〜3 · 3 : 8〜8 · 2混合。 8·· -種選擇性去除半球狀石夕晶粒層的方法,包括下列 提供一基底,其包括有一渠溝; 形成一埋入介電層於該渠溝側壁上部; 形成一半球狀;5夕晶粒層於該渠溝側壁及底部; 形成一摻雜絕緣層於該半球狀矽晶粒層上· ”層填入該渠溝内,並回“遮蔽層至一預 疋冰度,鉻出部份該摻雜絕緣層; 去除該未被遮蔽層覆蓋之摻雜絕緣層,露出 球狀矽晶粒層; θ路出。(W刀5亥+ 離子摻雜露出之該半球狀矽晶粒層, 雜層於該渠溝頂部及上侧壁;以及 形成一電水摻 去除該電漿摻雜層。 9.如申請專利範圍第8項所述之 入介電層為-氧化層。 1 〇 ·如申睛專利範圍第9項所述 只π k之選擇性去除半球狀矽第17頁 1236053_案號 92]πηη9 六、申請專利範圍 晶粒層的方法,其中該埋入 成。 ;丨電層係以虱離子佈植方式形 11 ·如申請專利節圍箆R 晶粒層的方法,並中兮電將^所述之選擇性去除半球狀矽 成。 八^電水推雜層係以硼離子佈植方式形 1 2 .如申請專利範圍第J J 矽晶粒層的方法,1中形成,員二'之選擇性去除半球狀 1E17〜1E19cm-3。 ” 成μ電水掺雜層之佈植條件為 曰二3.Λ申:專圍第8項所述之選擇性絲^ Ζ粒層的方法,其中去除該電漿摻雜層的方法為—濕敍刻 14.如申請專利範圍第13項所述之選擇性去除半 碎晶粒層的方法,並φ續笼A k 农狀 产Τ θ扪力凌具f該4向性之濕蝕刻法之蝕刻液為ft 鼠酸:硝酸:醋酸以卜1.5 ·· 3〜3·3 : 8〜8·2混合。為虱 1 5 · —種渠溝電容器之製法,包括下列步驟: 提供一基底,其包括有一渠溝; 形成一埋入介電層於該渠溝側壁上部; 形成一半球狀矽晶粒層於該渠溝侧壁及底部; 形成一摻雜絕緣層於該半球狀;^夕晶粒層上; 形成一遮蔽層填入該渠溝内,並回蝕該遮蔽層至一 定深度,露出部份該摻雜絕緣層; 去除該未被遮蔽層覆蓋之摻雜絕緣層,露出部分該 球狀矽晶粒層; 〜 離子摻雜露出之該半球狀矽晶粒層,以形成一電聚換〇593-A40〇〇lTWFl(Nl);92069;YYHSU.ptc 1236053 ^^ 92133002 曰 修正 六、申請專利範圍 雜層於該渠溝頂部及上側壁; 去除該渠溝頂部及上側壁之電漿摻雜層,以及去除該 殘留之遮蔽層; 形成一覆蓋氧化層於該渠溝底部及側壁;以及 施行一熱製程於該基底,以形成一電容器埋入電極 板 法 法 法 法 法 1 6 ·如申請專利範圍第1 5項所述之渠溝電容器之製 其中該埋入介電層為一氧化層。 1 7 ·如申請專利範圍第丨6項所述之渠溝電容器之製 其中該埋入介電層係以氧離子佈植方式形成。 1 8 ·如申請專利範圍第1 5項所述之渠溝電容器之製 其中該電漿摻雜層係以硼離子佈植方式形成。 1 9.如申請專利範圍第丨8項所述之渠溝電容器之製 其中形成該電漿摻雜層之佈植條件為1E17〜lE19cnr3。 20 ·如申請專利範圍第丨5項所述之渠溝電容器之製 其中去除該深渠溝頂部及上側壁之電漿摻雜層的方法 為一濕餘刻法。 2 1 ·如申請專利範圍第2 〇項所述之渠溝電容器之製 法,其中該濕蝕刻法之蝕刻液為氫氟酸:硝酸:醋酸以 1〜1·5 ·3〜3·3 ·8〜8·2混合。0593-A40001TWFl(Nl);92069;YYHSU.ptc 第19頁
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US7427545B2 (en) * | 2005-11-21 | 2008-09-23 | International Business Machines Corporation | Trench memory cells with buried isolation collars, and methods of fabricating same |
US7294554B2 (en) * | 2006-02-10 | 2007-11-13 | International Business Machines Corporation | Method to eliminate arsenic contamination in trench capacitors |
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US8021945B2 (en) * | 2009-04-14 | 2011-09-20 | International Business Machines Corporation | Bottle-shaped trench capacitor with enhanced capacitance |
US8450807B2 (en) | 2010-03-09 | 2013-05-28 | International Business Machines Corporation | MOSFETs with reduced contact resistance |
US8227311B2 (en) | 2010-10-07 | 2012-07-24 | International Business Machines Corporation | Method of forming enhanced capacitance trench capacitor |
TW201222778A (en) * | 2010-11-18 | 2012-06-01 | Ind Tech Res Inst | Trench capacitor structures and method of manufacturing the same |
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