TWI288411B - Memory device with vertical transistor and trench capacitor memory cells and method of fabrication - Google Patents

Abstract

Memory device with vertical transistor and trench capacitor memory cells and method of fabrication. A substrate having a trench is provided with a trench capacitor in the low portion, the trench capacitor comprising a top electrode and a buried strap surrounding the top electrode. Next, a sacrificial layer is formed on a portion of sidewall of the trench, exposing the sidewall between the sacrificial layer and the buried strap. A top dielectric layer is blanketly formed in the trench to isolate a gate conductive layer of the vertical transistor and the trench capacitor. The vertical transistor contacts the substrate through a buried strap conductive layer diffused to the trench sidewall. Finally, the sacrificial layer and a portion of the top dielectric layer are removed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory device having a vertical transistor and a trench capacitor. [Prior Art] With the widespread use of integrated circuits, various types of semiconductor components that are more efficient and cheaper in response to different use purposes have been produced in succession, in which dynamic random access memory (DRAM) Today's information electronics industry has an indispensable position. Most of today's DRAM cells are made up of a transistor and a capacitor. Since the memory capacity of DRAM has reached 64 million bits or even 256 million bits or more, the size of the memory unit and the transistor needs to be greatly reduced in the case where the component integration requirement is higher and higher, and it is possible to manufacture DRAM with higher memory capacity and faster processing speed. The process technology of the three-dimensional capacitor can greatly reduce the area occupied by the capacitor on the semiconductor substrate. Therefore, the three-dimensional capacitor is used in the process of DRAM, for example, the trench type electric grid device is widely used in the hundred. More than 10,000 yuan. Compared with the surface area of the traditional horizontal crystal (II) body, it can not meet the current needs of high integration. Therefore, the shortcomings of the conventional semiconductor memory unit can be greatly improved, and the Φ 夕 彳 彳 彳 , , , *, and the rut is a section of the 'space honey set body' will become the current semiconductor system of the husband and wife

0548-A502867¥f(5.0) ; 92277 ; Wayne.ptd Page 7 1288411 V. Inventive Note (2) The main trend is that in the above, the top of the e-reporting element has a vertical electric body and The trench capacitor vapor deposition method HDPCVD method, 1) is to use high-density plasma chemistry to easily control the top dielectric layer (10) <thickness is lacking: the other known technology has no Uef_ation due to the deformation of the trench) or ^ The top dielectric layer of the meeting (A = etry) caused the problem of electrical connection between the vertical and the G. According to the above problems, it is an object of the present invention to provide a memory device having a vertical transistor and a trench capacitor and a manufacturing method thereof, which can solve the asymmetry phenomenon of the prior art. And the thickness of the top dielectric layer can be more accurately approved to meet the needs of next generation technology. In order to achieve the above object, the present invention provides a method of manufacturing a memory element comprising a vertical transistor and a trench capacitor of the following steps. The first /, &amp; is provided with a trenched substrate, and the trench capacitor is disposed under the trench. The trench capacitor includes an upper electrode and a buried region surrounding the upper electrode. Thereafter, a sacrificial layer is formed on a portion of the trench sidewalls to expose the sacrificial layer and the buried trench sidewalls. Next, a top dielectric layer is formed in the trench, and the top dielectric layer is a gate conductive layer and a trench gate for isolating the vertical transistor.

0548-A50286TWf(5.0) 92277 &gt; Wayne.ptd Page 8 1288411

Used by the device. The vertical electro-crystalline system is in contact with the substrate. Finally, the dielectric layer. Removing the sacrificial layer through the diffusion of the buried region conductor layer to the sidewall of the trench, and simultaneously removing the top portion to achieve the above object, the memory element of the trench cell of the present invention, including the trench capacitor of the lower half of the trench, The body and the separation trench capacitor and the vertical electric portion dielectric layer include a ruthenium oxide layer and a surrounding layer. [Embodiment] Provided is a vertical transistor and a substrate having a groove, and is disposed in a vertical direction of the groove in the upper half of the groove The top dielectric layer of the electromorphic crystal, wherein the tantalum nitride layer of the top oxide layer. Referring to FIGS. 1A to 1D, the ία~iD diagram only shows a schematic diagram of a process for forming a memory element having a vertical transistor and a trench capacitor as known to the inventors to reveal the problems discovered by the inventors, but It is not a publicly known technique. First, as shown in FIG. 1A, a tantalum oxide layer 20 and a pad nitride layer 30' are formed on a substrate 1 and are defined by a pad oxide and a nitrogen oxide layer 30. The mask screen etches a plurality of trenches in the substrate (for simplicity of description, only one trench 1 0 1 is shown here). Thereafter, a lower electrode 110 is formed in the substrate 100 in the lower half of the trench 丨〇 i, and a capacitor dielectric layer 108 is formed on the sidewall of the lower half of the trench. Next, a collar dielectric layer 1 1 2 is formed on a sidewall of a portion of the trench above the capacitor dielectric layer 1〇8, and a polysilicon germanium conductive layer is filled in the trench.

0548-A50286TWf(5.0) ; 92277 ; Wayne.ptd Page 9 1288411 V. INSTRUCTION DESCRIPTION (4) 1 In 〇1, used as the trench 1 in the lower half of the trench capacitor on the trench 1 13. Next, as shown in Fig. 1B, the collar-shaped dielectric layer surrounding the upper electrode 133 is etched by selective etching, and a gap is formed between the upper electrode 117 and the substrate 10000. Next, a barrier layer 11 5 is deposited in the trench 110 and compliant with the gap between the electrode layer 11 3 and the sidewall of the trench 101, and in the next step, the deposition of compliance is performed. The conductive layer 120 is doped on the barrier layer 11 5 and fills the gap described above. Thereafter, as shown in FIG. 1C, the doped conductive layer is etched back to form a buried region conductive layer 116 in the gap between the upper electrode 113 and the sidewall of the trench 110, and the upper electrode 113 is removed. The barrier layer 115 above. Next, as shown in Fig. 1D, a top dielectric layer 122 (ττ〇) is formed on the upper electrode 113 by a high-density plasma chemical vapor deposition method HDpcvD. The top dielectric layer 122 formed by the above method is easily deformed by the deformation or process of the trench 丨〇1, so that the formed top dielectric layer lj2 is asymmetrical (in the 1D diagram). In the middle, it is depicted by a top dielectric layer having a crotch portion and a lower portion. Next, a thermal oxidation method is applied to the asymmetric top dielectric layer 122 = 1 曰: wall V gate dielectric layer 124. Subsequently, the steps of forming the gate dielectric layer 122 and the gate electric θ 126 in the trench 101 by the isoelectric layer 126 are all high temperature.

1288411 V. INSTRUCTION DESCRIPTION (5) 近: Conductive layer: The dopant in 16 will be thermally diffused to its m-series to electrically connect the control layer of the buried diffusion dielectric layer 122: Electricity and:: container. The importance of the item memory component is ^^ $ 直 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日The problem. &amp; 笙 笙 :: 2A~2H shows an embodiment of the invention for forming a memory device having φ, a straight transistor and a trench capacitor. The first and the third do not form a pad oxide layer 202 S 〇4 on the substrate 2〇0, and the pad oxide layer 202 and the pad nitride layer L are used as masks to etch a plurality of layers in the substrate. The trench (for simplicity of description, it is only represented by - trench 20 6). Thereafter, a lower electrode 208 is formed in the base of the lower half of the trench 2{)6, and is formed on the lower half side layer 21 of the trench 2〇6. . Next, a portion above the capacitor dielectric layer 21 is formed into a collar dielectric layer 212, and a polysilicon germanium conductive layer is filled in the trench 2〇6 to serve as a trench in the lower half of the trench. Slot capacitor upper electrode 214 〇

Next, as shown in Fig. 2B, the collar dielectric layer 212 surrounding the upper electrode 214 is etched by a selective etching method, and a gap is formed between the upper electrode 214 and the substrate 200. Next, a barrier layer 2 16 , such as a tantalum nitride layer, is deposited in the trench 20 6 and filled between the upper electrode 2丨4 and the sidewall of the trench.

0548-A50286TWf(5.0); 92277 ; Wayne.ptd Page u 1288411 V. INSTRUCTIONS (6) $ ϋ ' : Deposition of a doped conductive layer 218, such as a doped 曰曰矽 layer, The barrier layer 216 is over and filled with the gap described above. Thereafter, as shown in FIG. 2C, the conductive layer is doped back to the gap 2 between the upper electrode 214 and the sidewall of the trench 206, and the barrier layer above the upper electrode 214 is removed. 21 to 6, for example, the fabrication of a buried area 222 that is wound around the upper portion of the electrode. Here, the buried region 222 includes a buried region conductive layer 22 and a barrier layer 216. Next, as shown in FIG. 2D, a sacrificial layer 224 is accumulated on the sidewalls of the trench 206 and the upper electrode 214 by, for example, a low-pressure chemical vapor deposition method. For example, TEOS is a ruthenium oxide layer formed by a ruthenium source. Thereafter, the second layer 224 is sacrificed by, for example, low pressure chemical vapor deposition LPCVD compliance. The conductive layer 226 is preferably a dream conductive layer, an electric/good 22-series 6-201 polysilicon layer, and preferably has a thickness of 15 Å to 2 Å to etch the sacrificial layer 224 subsequently. A sufficient etch barrier can be provided in the step. Thereafter, a conductive layer 226 adjacent the upper electrode 214 is removed by an anisotropic etch to expose the bottom portion of the sacrificial layer 224.曰 Next, as shown in FIG. 2E, the conductive layer 226 is used as an etching mask, and an isotropic etching method, such as a wet etching method including fluoride ions, removes a portion of the sacrificial layer 224 above the upper electrode 214. It is used to expose a portion of the trench 20 6 sidewall above the buried region 222. Thereafter, as shown in FIG. 2F, the 沟槽s SG (In Situ Steam Generation) oxidation technique or a conventional thermal oxidation method is applied to the exposed trench 2 〇 6 sidewall, the upper electrode 21 4, and the buried region conductive layer. 0548-A50286TWf(5.0) ; 92277 ; Wayne.ptd Page 12 1288411__ V. Invention Description (7) &quot; -------- 2 2 0 Form a repair dielectric layer 2 2 8 for repair The trench sidewalls 214 and the buried region conductive layer 220 are destroyed by the above-described etching step to achieve the effect of reducing leakage current. The repair dielectric layer 2 2 § can be b 9 straw, fossil layer, and the thickness does not need to be too thick, the thickness can be between 3 〇 〜 oxygen, followed by, for example, low pressure chemical vapor deposition compliant ^ dielectric Layer 230 is on repair dielectric layer 228 and sacrificial layer 224. The dielectric material 1 material and the sacrificial layer 224 have a certain etching selectivity, and the selection ratio of the ^23 0 is greater than 10, so as to more accurately define the top layer to the electric layer in the subsequent steps. Electrical layer 230 can be comprised of, for example, a nitride layer. After the portion is overcoated, an inner top, eight layers 232 are deposited on the dielectric layer 230 by, for example, high density plasma chemical vapor deposition. Here, the high-density plasma chemical vapor deposition method is used to form a thin film having a thick bottom and a thin sidewall, and is used to form a top dielectric layer 232 which is lower than the surface of the substrate 200. The material of the inner top dielectric layer 232 also needs to have a certain etch selectivity with the dielectric layer 23, and the preferred ratio is greater than 10 for accurately etching the dielectric layer 230 in the subsequent etching step. Here, the inner top dielectric layer 232 may be composed of, for example, TE〇s as an oxide layer of Shi Xiyuan. Please refer to FIG. 2F. Since the above chemical vapor deposition method or the thermal oxidation method is a high temperature process, the impurities in the buried region conductive layer 220 are diffused by high temperature to the substrate adjacent to the sidewall of the trench. The middle 'forms a ring-shaped buried diffusion region 234 for connecting the trench capacitor and the vertical transistor formed by the subsequent steps. Next, as shown in Fig. 2G, a selective etching method is used, for example, to soak the dielectric layer between the top dielectric layer 23 2 and the sacrificial layer 224 in the phosphoric acid

0548-A50286TWf(5.0); 92277; Wayne.ptd Page 13 1288411 V. Description of the Invention (8) 230, the surface of the dielectric layer 230 is slightly lower than the inner top dielectric layer 2 32 for use in subsequent steps The height of the inner top dielectric layer 232 is defined. , as used in Figure 2H - (d) method, such as immersion of uranium hydrofluoric acid UCHF3S# engraved body dry silver engraving method, and dielectric layer 23 〇 as an etch barrier, etching sacrificial layer 224 and inner top dielectric The layer 232 is such that the surface of the inner top layer 232 is slightly lower than the surface of the dielectric layer 230 for completing the fabrication of the dielectric layer 236. Thus, the top dielectric layer (10) of the present embodiment includes a repair dielectric layer 228, a dielectric layer 305, and an inner top dielectric layer 23 2 .

Next, as shown in FIG. 21, a gate dielectric layer 238 is formed on the sidewall of the trench above the top electrode layer 23 6 by, for example, thermal oxidation, which can be a hafnium oxide layer for use as a vertical transistor. The gate oxide layer. 'The most is deposited by a blanket deposition of a gate conductive reed' 240, such as a polycrystalline germanium layer, in a trench on the top dielectric layer 236, as a gate electrode of a vertical transistor. X. Referring also to Figure 2, there is shown a cross-sectional view of a vertical transistor and trench capacitor memory device implemented in accordance with the present invention. Here, the gentleman includes: a substrate 200 having a trench 206, a half-sand capacitor disposed under the trench 2〇6, a vertical transistor disposed in the upper half of the trench, and a &lt; The dielectric layer 236, which can be used to separate the trench capacitor and the vertical transistor top dielectric layer 236, includes a first tantalum oxide layer 232, a tantalum nitride layer 230 surrounding the first gas layer 232, and a surrounding tantalum nitride layer 230. The second oxidation is 9 2M. 7 layers

1288411

The buried capacitor includes an upper electrode 214, an upper electrode 2 and a lower electrode 208 disposed in the substrate 200. Vertical lightning = the upper half of the sidewall of the dummy dielectric layer 238... The top conductive layer 240. The top dielectric layer formed by the present invention is formed by LPVCD as a part of the dielectric layer formed by the LPCD. It can provide more precise control. This: the edge of the layer can be controlled by the money to sacrifice a sacrificial layer to control the top Sdr not = phenomenon 'and can be more precise &quot; electrically increased thickness to meet the next generation technology The present invention has been disclosed in the preferred embodiments as described above, but it is not intended to be invented, and any person skilled in the art can make some changes without departing from the spirit of the present invention. And the retouching, therefore, the warranty of the present invention is subject to the definition of the patent application scope attached 。.

1288411_ BRIEF DESCRIPTION OF THE DRAWINGS The 1A to 1D drawings show a process diagram for forming a memory element having a vertical transistor and a trench capacitor. 2A through 21 are schematic views showing a process for forming a memory element having a vertical transistor and a trench capacitor in accordance with an embodiment of the present invention. [Main component symbol description] 2 0~ pad oxide layer; 3 0~ pad nitride layer; 1 0 0~矽 substrate; I 0 1~ trench; _ 108~ capacitor dielectric layer; II 0~lower electrode; 2~ collar dielectric layer; 11 3~ upper electrode, 11 5~ barrier layer; 116~ buried layer conductive layer; 120~ doped conductive layer; 1 2 2~ top dielectric layer; 1 2 4~ gate Dielectric layer; • 1 2 6~ gate conductive layer; 1 2 8~ buried diffusion region; 20 0~ substrate; 2 0 2~ pad oxide layer; 2 0 4~ pad nitride layer;

0548-A50286TWf(5.0) ; 92277 ; Wayne.ptd Page 16 1288411 Schematic description 20 6~ 20 8~ 21 0~ 212~ 214~ 21 6~ 218~ 22 0~ 22 2~ 22 4~ ' 22 6 ~ 22 8~ 23 0~ 23 2~ 234~ 23 6~ 23 8~ 24 0~ trench; lower electrode; capacitor dielectric layer; collar dielectric layer; upper electrode; barrier layer; doped conductive layer; Buried area conductive layer buried area sacrificial layer conductive layer repair dielectric layer; dielectric layer; inner top dielectric layer buried diffusion region top dielectric layer gate dielectric layer gate conductive layer

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Claims (1)

^288411 ___ __ ...&gt;, Patent Application No. 1 · A method of manufacturing a memory device having a vertical transistor and a trench capacitor, comprising the steps of: providing a substrate having a trench, wherein a trench capacitor is disposed a trench capacitor, the trench capacitor includes an upper electrode and a buried region surrounding the upper power and the upper portion; the compliant layer forms a sacrificial layer on the upper electrode, the buried region and the trench sidewall Compliance forming a conductive layer on the sacrificial layer; etching back the conductive layer to remove the bottom of the conductive layer; % using the conductive layer as a mask to partially engrave the sacrificial layer to expose the upper electrode Part of the trench sidewall; removing the conductive layer; compliant forming a dielectric layer on the sacrificial layer and over the upper electrode, blanket forming an inner top dielectric layer on the dielectric layer, The surface of the inner top dielectric layer is lower than the surface of the substrate; ' ^ etch back the dielectric layer such that the surface of the dielectric layer is lower than the surface of the inner layer, and the dielectric 4 is dielectrically blocked by the dielectric layer. Touch back The sacrificial layer. An electrical layer and a method of fabricating a memory device having a vertical cell capacitor as described in claim i, wherein the sacrificial layer and the dielectric layer of the trench, and an etching option of the dielectric layer The ratio is greater than 丨〇. (9) The method of manufacturing a memory device having a vertical electric capacitor according to the first aspect of the invention, wherein the sacrificial body and the trench and the inner top 0548-A50286TWf(5.0) ; 92277 ; Wayne.ptd Page 18 1288411 ----- VI. Patent scope The dielectric layer is the crystal layer of the capacitor. 5. The dream layer of the capacitor. 6. If the capacitor of the slot is made by a high-density capacitor, such as the slot capacitor, and the trench side of the buried region, the dielectric layer is deposited in the dielectric layer. TEOS is the patent patent memory component, please patent the memory component, please patent the memory component, the plasma plasma, the patent memory component, a thermal oxidation, to form the wall, the supernatant patent memory component = the yttrium oxide layer formed by the source . The vertical manufacturing method according to Item 1, wherein the electric conductor and the electric layer of the gully are a vertical manufacturing method according to the one item of the first one, wherein the medium and the sulphide layer are The method for manufacturing a vertical lightning rod according to the first aspect, wherein the inner top 曰曰8 body and the ditch vapor deposition HDPCVD form a W layer having a vertical Thunder as described in item 1. . The manufacturing method comprises the step of forming the trench sidewall of the dielectric body and the trench oxidized exposure, and the upper electrode of the repair dielectric layer composed of the upper and the first oxide, and the buried region. The method for manufacturing a vertical transistor and the method of the invention according to the first aspect of the present invention includes forming a gate dielectric layer by a thermal oxidation, a trench sidewall, and a low gate conductive layer. A method of fabricating a memory device having a vertical transistor and a trench capacitor, comprising the steps of: providing a substrate having a trench, and a trench capacitor is disposed in the trench a lower half of the trench, the trench capacitor includes an upper electrode and a surrounding power 0548-A50286TWf(5.0) i 92277 » Wayne.ptd Page 19 • 1288411 Six patent application scope __ ____ extremely Tibetan area; a sacrificial layer forming a trench sidewall in part of the buried section; 4 slot sidewall Exposing the sacrificial layer and forming a top dielectric layer in the sacrificial layer and the buried region trench, wherein the top dielectric layer is in contact; and &quot;9 the exposed trench sidewall and The substrate removes the sacrificial layer and 10 removes a portion of the top dielectric layer as in the patent application. The method of manufacturing a memory device of a slot capacitor, the method of generating a ruthenium oxide layer formed by a vertical transistor and a trench Φ, wherein the sacrificial layer is TEOS 11. The capacitor of the ninth slot is as claimed in the patent application. The memory element is sheared, Α = having a vertical transistor and a trench-method-oxidation layer, wherein the top dielectric layer comprises a tantalum nitride layer surrounding the second tantalum layer of the tantalum nitride layer and - 1 2 · Manufacturing of memory elements of a two-slot capacitor as claimed in the patent; m: vertical transistor and trenching and a trench dielectric forming a gate dielectric screen...&quot;, :: pre-oxygen phase deposition Method of deposition - the top of the gate::, and in the lower groove. Above the top dielectric layer &gt; 13. The method of manufacturing a memory element having a right-handed slot capacitor as described in claim 9 of the patent application, which has a straight transistor and a trench sidewall, including The following steps: 'forming the sacrificial layer to form the sacrificial layer on the upper electrode and the sidewall in the compliant portion; 〇548-A50286TWf(5.〇); 92277 ; Wayne.ptd Page 20 1288411 —------ 6. Compliance with the patent application scope forms a conductive layer on the sacrificial layer; To remove the conductive reed L'i ^ ^ &lt; the track; the conductive layer is a portion of the trench sidewall on the sacrificial electrode of the mask; the layer 1 is exposed to remove the conductive layer . 14. A device having a vertical transistor and a trench capacitor includes: a sub-layer; a substrate having a trench; a trench capacitor disposed in the lower half of the trench; φ a vertical a transistor disposed on the upper half of the trench; and a top dielectric layer separating the trench capacitor and the vertical transistor, wherein the top dielectric layer comprises a hafnium oxide layer and a nitride surrounding the oxidized cucurbit矽 layer. 9. The memory device having a vertical transistor and a trench capacitor as described in claim 14 wherein the trench capacitor comprises an upper electrode and a buried region surrounding the upper electrode. 1 6 - The memory device having a vertical transistor and a trench capacitor as described in claim 4, wherein the vertical transistor comprises a gate dielectric layer disposed on a trench side above the top dielectric layer A wall and a gate conductive layer are disposed in the trench above the top dielectric layer. The memory element having a vertical transistor and a trench capacitor as described in claim 14 wherein the top dielectric layer further comprises a repair dielectric layer composed of ruthenium oxide surrounding the tantalum nitride layer. . 0548-A50286TWf(5.0) ; 92277 ; Wayne.ptd Page 21