TW200632906A - Memory device with vertical transistor and trench capacitor memory cells and method of fabrication - Google Patents

Memory device with vertical transistor and trench capacitor memory cells and method of fabrication

Info

Publication number
TW200632906A
TW200632906A TW094107094A TW94107094A TW200632906A TW 200632906 A TW200632906 A TW 200632906A TW 094107094 A TW094107094 A TW 094107094A TW 94107094 A TW94107094 A TW 94107094A TW 200632906 A TW200632906 A TW 200632906A
Authority
TW
Taiwan
Prior art keywords
trench
vertical transistor
trench capacitor
fabrication
memory device
Prior art date
Application number
TW094107094A
Other languages
Chinese (zh)
Other versions
TWI288411B (en
Inventor
Neng-Tai Shih
Chien-Chang Huang
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Priority to TW94107094A priority Critical patent/TWI288411B/en
Publication of TW200632906A publication Critical patent/TW200632906A/en
Application granted granted Critical
Publication of TWI288411B publication Critical patent/TWI288411B/en

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  • Semiconductor Memories (AREA)

Abstract

Memory device with vertical transistor and trench capacitor memory cells and method of fabrication. A substrate having a trench is provided with a trench capacitor in the low portion, the trench capacitor comprising a top electrode and a buried strap surrounding the top electrode. Next, a sacrificial layer is formed on a portion of sidewall of the trench, exposing the sidewall between the sacrificial layer and the buried strap. A top dielectric layer is blanketly formed in the trench to isolate a gate conductive layer of the vertical transistor and the trench capacitor. The vertical transistor contacts the substrate through a buried strap conductive layer diffused to the trench sidewall. Finally, the sacrificial layer and a portion of the top dielectric layer are removed.
TW94107094A 2005-03-09 2005-03-09 Memory device with vertical transistor and trench capacitor memory cells and method of fabrication TWI288411B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94107094A TWI288411B (en) 2005-03-09 2005-03-09 Memory device with vertical transistor and trench capacitor memory cells and method of fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94107094A TWI288411B (en) 2005-03-09 2005-03-09 Memory device with vertical transistor and trench capacitor memory cells and method of fabrication

Publications (2)

Publication Number Publication Date
TW200632906A true TW200632906A (en) 2006-09-16
TWI288411B TWI288411B (en) 2007-10-11

Family

ID=39203013

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94107094A TWI288411B (en) 2005-03-09 2005-03-09 Memory device with vertical transistor and trench capacitor memory cells and method of fabrication

Country Status (1)

Country Link
TW (1) TWI288411B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI497649B (en) * 2013-04-01 2015-08-21 Inotera Memories Inc Semiconductor structure with buried word line and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI497649B (en) * 2013-04-01 2015-08-21 Inotera Memories Inc Semiconductor structure with buried word line and manufacturing method therefor

Also Published As

Publication number Publication date
TWI288411B (en) 2007-10-11

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