TW529166B - Method for forming an array of DRAM cells with buried trench capacitors - Google Patents

Abstract

A method for forming an array of DRAM cells with buried trench capacitors is provided. The present method utilizes a photolithography and etching process to laterally remove away the parts of a collar oxide layer around the inner sidewalls of buried trench capacitors neighboring with each other in a pair of neighboring buried trench capacitors before a dielectric layer of the capacitor is formed. By way of replacing the removed parts of the collar oxide layer with a silicon nitride/silicon dioxide (NO) composite layer and using a strip type pattern along the pattern of the buried trench capacitors to define active areas for source/drain regions of access transistors over the buried trench capacitors, additional capacitance is occurred in the peripheral area of the neighboring buried trench capacitors which are not used by a conventional buried trench capacitor. As a result, the capacitance of the buried trench capacitor is increased without either increasing the depth of the buried trench capacitor or thinning down the effective insulator's thickness of the buried trench capacitor.

Description

529166 V. Description of the invention (1) 5-1 Field of the invention: The present invention is related to the μ _ method; in particular, it is related to the method of making memory elements by making machine access to memory elements; and the dynamic randomness of trench capacitors. Memory 5-2 Background of the Invention: Dynamic memory random access memory (DRAM) instrument unloading —ynamiC random access (-rging state): Number: 2 :: The state of charge of the capacitor of the two cells. A dynamic random access $ 5 tiger's volatile memory (_ss transistQmmt-an access transistor caDacii ^ H. Six n two storage capacitors (storage storage electrode, such as 1 electrode crystal :: connected to the storage capacitor -Voltage. Between the upper and lower electrodes Π,; ::: The electrode system is connected to the heart of a positive-access random-access memory cell. When the electric valley σσ stores more electricity, the ancient φφ and the鄕 L 7 Xin Xi ° Implification gain, I pL, which is noisy when reading data, and soft false records (S〇ft err〇rs) produced by α particles will be significantly lower, which can be further reduced " refill " (refresMng, called Mη "). When a dynamic random access memory cell capacitor requires only a small amount of 2 charge storage capacitors, two-dimensional or planar capacitors can be fabricated on integrated circuits. However, The planar capacitor occupies a considerable surface of the semiconductor substrate. Page 6 529166 V. Description of the invention (2) -------- The product is not suitable for dynamic random access memory elements with a high accumulation degree. A three-dimensional capacitor, such as a so-called stacked or trencher, Improve the accumulation of dynamic random access memory devices. Figures -A to -L of the Valley of Power Valley are cross-sectional schematic diagrams of various process steps of a traditional trench type DRAM ceU with trench capacitors. As shown in Figure A and Figure A, Figure 2A is a schematic plan view of the subsequent process steps, and Figure 1A is a cross-sectional view of Figure 2A along the line 丨 _ t. A pad oxidation The layer ii and a silicon nitride layer are sequentially formed on a P-type silicon substrate OO. After that, the silicon nitride layer i 〇2 and the pad oxidation sound are etched by a conventional lithography and etching process pattern to form The plurality of rows of trenches 〇3 are on the P-type silicon substrate 2 〇◦. As shown in Figure 2A, each row of trenches 1 q φ Taiwan 4, and 1 U d includes a number of pairs of adjacent trenches 103. And a pair of adjacent grooves 1 nq and #, _ J / Zaimu 103 are separated from each other by a predetermined distance (conf〇rmal sU.con nitride layer) 1 0 4 ^ 04i: ;; two one sacrifices The layer 105 is formed on the conformal gasified fossil layer 4. The picture of Cangzhi, Brother C, Qian Kebu / Bacongji " the ancient sacrifice layer 105 and the Ui wounded sacrifice layer 1 〇 5, with the groove 10 1 ϋ Γ oxide layer 10 1 under #, and the part covered by the sacrifice layer 105 of the nitride stone V? / Conform to the layer 104. After that, the remaining sacrifice is removed.

529166

JU teq ^ ^ ^ ^ 1 〇 3 ^ 1 0 6 on the inner side wall. After that, the 104 covering layer 1.4 was removed with a hot phosphoric acid solution. Referring to FIG. -F, a p-type stone substrate 1 around a trench of -N-type nitrided silicon nitride is formed around the N-type nitride stone, and the n-type impurity gas is used as a doping source in the vicinity of the n-type impurity. The p-type stone substrate base / de-doping doping region 10 adjacent to the trench 103 can be used as a buried trench to be formed later. N-type diffuser. The trench 103 is covered by a ring-shaped oxide layer 丄 0 and 6: the second-bottom region 100 is not doped with an N-type dopant. The reference of P! Shi Xi substrate refers to "Nitride stone" nitride / sillc〇n dl〇xide c⑽p〇si (NO c〇mp〇Slte layer) i ◦ 8 in each: The inner peripheral wall covered by the dagger-shaped oxide layer 106 (1_r is not soiled area) for use as a dielectric layer for buried trench capacitors. Fig. "Figure, depositing an N-type doped polycrystalline silicon layer 〇9 shot-type stone γ, the first Η to fill each trench 〇3, and for the buried trench type = top electrode. After that, the N-type doped polycrystalline silicon layer was etched to expose the trench. Part of the ring oxide layer 丄 06 in 103. Refer to the 'aa diagram, etching the bad-shaped oxide layer] _〇6 exposed part up to the surface of the N silicon layer 109. H 4 7 529166 Description of the invention (4) Referring to the first figure J, next, Shen Yi 100, and the remaining part of the amorphous stone layered in order to multiply the layer; in order to form a buried in the Shi Xi basement channel 103 Jing Ershi's amorphous ... 1 1 D. Using handymanship from V DUriea S1 1 icon strap) Π method to mix N-type metamorphisms into the embedded Shi Xi guide belt 丄 丄 U and order a tempering step to implant the embedded silicon Conduction band] The 1 n-type dopant diffuses outward into the adjacent P 1 0 2 \ -doped embedded stone slab "Η η Λ 'substrate 1 Q., so that the N-type dopant ^ ^, x 7 vf 1 1 〇 A source of an access transistor / 〇σ that is sexually connected to the buried trench-type thundercry and later formed on the p-type stone 々 || η Hekoukou pole, and the pole region τ, 〇〇 16. According to the above process steps, the production of buried t, and d trench capacitors can be completed. I ″ built into the buried trench / ..., Figure K and Figure B, where the second β picture is the subsequent potential steps The top view is 筮. M ^ τ Silly, I walk privately-Takaoka you = circle and 苐 a κ diagram is the second β diagram cross section along the IIMI line without thinking i uses an island pattern (L) ] _ 丄 Forming the source of the access transistor of the t '? M machine to access the memory cell, the active area of the drain i region 11 ?. The result is that a trench barrier " is formed in a ρ silicon substrate 100 between a pair of adjacent buried trench capacitors and passes through the individual buried silicon conduction bands n R * Dan Geoelectrical junction ν 1 1 0 and some individual buried trench-type capacitors 0; · ', a dedicated L-picture and a second C-picture, where the second picture is the top view of the subsequent process steps and the first [picture The second C diagram is a section 7 " thinking diagram along the III-III line. Deposition-oxide layer on P-type silicon substrate 100 to fill

Page 9 529166 V. Description of the invention (5) The polishing step forms a gate oxide by a buried trench formed from the silicon oxide layer 10 on the silicon substrate 100 to form an N-type incision to form a zigzag line. However, the dynamics of the type 1 1 capacitor in the drain / drain region is t °. This type of capacitive layer is doped with the gate layer, and then the random trench isolation area is 6 °. Then, it is chemically and mechanically planarized. At the same time, Removal of the nitrided stone layer 102 and ion implantation method to form an N-well 1 1 3 and a p-type N-well 1 1 3 are electrically coupled to a positive voltage by the N-type diffusion region 107. Thermal oxidation 1 1 4 was used on a P-type silicon substrate 100. After that, the polycrystalline silicon layer and a tungsten silicide layer are pattern-etched 1 15 for the dynamic random access memory cell cell ion implantation method to form the source of the access transistor. The above process steps can be completed. The buried trench accesses the memory cell array. However, according to the small size of the main channel capacitor when the size is reduced, the capacitor rat io is increased. On the other hand, due to the thickness of the dielectric layer of the container that can withstand high temperatures, it is urgent to mention the point of accessing the memory cell and improve the capacitor. This is the traditional process and the limiting factor of the trench capacitor. In order to keep the capacitance unchanged, :: The piece size is etched deeper to compensate for the loss of the trench area e due to the horizontal squareness. When the aspect ratio of the trench is reduced, the process of etching is more difficult and the type capacitor is limited in other components. The high dielectric material is limited, so it seems difficult to increase the unit capacitance. Type power supply with a buried trench capacitor = process' It can overcome the above tradition to:

529166 V. Description of the invention (6) 5-3 Purpose and summary of the invention: The main purpose of the present invention is to provide a method for manufacturing a dynamic random access memory cell array with a buried trench capacitor, which can be used without additional embedding. Trench capacitors increase capacitance without thinning the thickness of their dielectric layers. Another object of the present invention is to provide a method for manufacturing a dynamic random access memory cell array with a buried trench capacitor, which uses a strip type pattern instead of an island pattern along a traditional process. In the direction of the pattern of the buried trench capacitor, an active area for the source / dead end of the access transistor is defined on the semiconductor substrate. Therefore, the process window for linear pattern transfer can be greatly improved. Another object of the present invention is to provide a method for manufacturing a dynamic random access memory cell array with a buried trench capacitor, which uses a strip type pattern instead of an island pattern along a traditional process. In the direction of the pattern of the buried trench capacitor, an active region for a source / drain of an access transistor is defined on a semiconductor substrate. Therefore, the contact resistance of a buried conductive band (buried CondUctlVe strap) electrically coupled to a top electrode of a buried trench capacitor and a source / drain of an access transistor can be reduced.

529166 V. Description of the invention (7) and one of the well-controlled memory crystals. The connection (buried channel) includes a plurality of i eectr i-shaped dielectric layers and a dielectric layer. Then, the dynamic random access method of the capacitor according to the above-mentioned purpose is to provide a first-conductor-dielectric Layer on the semiconductor substrate to form a plurality of rows of buried trenches, wherein each row of buried trenches and each pair of adjacent buried trench-shaped dielectric layers (conformal d.) Form a sacrificial layer so that the height of the sacrificial layer is located at A part of the conformal dielectric layer covered by the first layer provides a manufacturing method of an embedded trench-type cell array. The semiconductor substrate of the present invention is formed with a pattern of a dielectric layer (trench) on the semiconductor substrate. The adjacent buried trenches are separated by a predetermined distance to form a total c layer) on these buried trenches. Remove part of the sacrificial layer below the surface. The unsacrificed layer is removed, and the remaining portion of the sacrificial layer is removed. A ring oxide layer is formed on the inner sidewall of the trench that is not covered by the remaining portion of the conformal dielectric layer. Bury the rest of the dielectric layer. Formed with electrical properties opposite to the second = showing conformal two-conductivity—diffusion regions in each—the buried trenches are not oxidized ^: in the semiconductor substrate in the surrounding part of the first, where this layer covers + of the trench capacitor Electrode ... Micro 2 :: Embedded-Remove each layer from the inner side of adjacent buried trenches adjacent to each other. W 4 h mounting oxidation 529166

529166 V. Description of the invention (9) The oxide layer on the adjacent inner side wall of a pair of adjacent buried trench capacitors. Next, replace a part of the removed ring oxide layer with a second dielectric layer such as a silicon nitride / two ^% shaped layer and use a line pattern =, the pattern of the buried trench capacitor is oriented toward the buried trench capacitor Upper ^ = Active area for source / drain region, to generate additional capacitance in the surrounding area of each buried trench container, this surrounding area is:: Not used in buried trench capacitors. Therefore, the method of the present invention can increase the depth of the buried trench capacitor and increase the capacitance without thinning the dielectric layer thickness T. The following is a detailed description of the case 5-4. The invention has a high-accumulation dynamic random access memory (DRAM) cell structure with a buried trench capacitor and a manufacturing method thereof. f is described in detail below. According to the present invention, a preferred embodiment, the dynamic and random access memory cell system uses a -N channel field effect transistor (N :: hannel; eld e feCt tranS1St〇r) located on a buried semiconductor substrate. Recess transistor as an access transistor of each memory cell. Therefore, when the area of the memory cell is reduced, the space below the device area can be used to manufacture a buried capacitor with increased capacitance. With additional process steps, other types of devices can also be formed on the dynamic random access memory device chip. E.g? By forming a well in a p-type semiconductor substrate, a complementary metal-oxide semiconductor can be fabricated on the wafer at the same time.

Page 14 529166 V. Description of the invention (ίο) Field-effect electric circuit (complemeritai'y me t a bu oxide-semiconductor) (CM〇s) circuit. The oxygen half field effect transistor circuit can be used as a dynamic random access memory / golden circuit. The perimeter of the heart basket is shown in Figures 3A to 3M, and Figures 4A, 4B, 4C, 41) mp According to the preferred embodiment of the present invention and Figure 4E, random access to the seal said, ^ Set the kinetic energy of the Tochigi electric valley device: Take 5 already [thinking about the various processes of the cell array. Referring to FIG. 3A and FIG. 4A, where = the following details the example of the initial process steps ^ ^ ^ The preferred implementation of the IV-IV transfer / Pinelli diagram 'and Figure 3A is Figure 4A along V ,. 'Spring cross section does not think. The inventor of the present invention is an electrical semiconductor substrate 300. The ic tool—brother—conductivity—from t on to—brother—conductivity can be N-type or p-type. Stone = any-the 'however' semiconductor substrate is 3 〇 than the silicon substrate. -Oxygen for silicon dioxide: U soil is -P type. Bottom] η η d U 1 is formed in P. chinensis, for example, by thermal oxidation. Next, one is formed: a body base layer 302 is formed on a pad of oxidized aluminum alloy 11_ ^ Γ to form a dielectric swelling 3 a == 3 〇1, which is preferably SiH2Cl and a reaction gas, and a low pressure chemical And a silicon layer. &Amp; Nitride formed by the deposition method using a lithographic method. The lithography process is engraved with a lithography and surname process pattern to bury a trench 30 in the center of the first dielectric bank 3 in the semiconductor core. Neighboring buried trenches: Columns of buried trenches 3 03 include a plurality of pairs spaced apart from each other 2 :: For adjacent buried trenches 3 " is a pre-distance. Comment ... is using a photoresist coating step and the 15th Page 529166 V. Description of the invention (11) In the embodiment where the non-isotropic plasma is used as the buried trench, a dielectric layer 3 0 is fluorine), plasma), and the etching channel 3 0 3 is continued. The trench 3 0 3 is formed. The etching process type capacitor contains HI insects such as C F4, machine or reaction 2 and pad oxygen engraving process. Here the shape is used to include the capacitor engraved under the element area to be formed later. Ditch area. This is a preferred embodiment of a high-density plasma (an etchant containing In a density ion etching machine, the first chemical layer 3 1 formed of silicon nitride is anisotropically plasma-etched into a semiconductor substrate 300 to form an anode electrode embedded in a trench. Chlorine (C 込) gas is etched by an anisotropic plasma. Referring to FIG. 3B, the photoresist is removed and formed—a semiconductor substrate 300 in the conformal dielectric layer. 0 4 can be formed using SiH2Cl2 and 叩 3 as the base ^ this /, y ^ ^ gaseous fossil layer formed by chemical vapor deposition method ^ reaction gas, a low-pressure Sacrlflcial layer) 3 〇5 formed on it Then, a sacrificial layer (above, to fill the buried trench 3 03. The sacrificial layer 丨 electrical layer 3 0 ′ silicon layer, for example, phosphosilicate glass (PSG) / 5 can be a one-oxide and spin-on glass (S0G). Refer to Figure 3C: Silicon glass (BpsG) 3 05, so that the height of the sacrificial layer 3 05, remove part of the surface of the sacrificial layer. It is preferred to remove the second brother by dry etching method— The dielectric layer 3 0 2 is, for example, a sacrificial layer 3 using a fluorine-containing etching gas with an anisotropic lightning = 3, a sacrificial layer 3 of the dioxide, and water. Removing part of the law

Page 16 529166 V. Description of the invention (12) The remainder, so that the remaining portion of the conformal dielectric layer 3 0 4: The remaining portion of the layer 3 0 5 is exposed. Referring to FIG. 3D, after that, the conformal dielectric layer 3 04 which is not covered by the sacrificial layer 3 05 is removed, preferably using an anisotropic dry etching method. For example, a fluorine-containing gas may be used to anisotropically The plasma etching method removes the conformal dielectric layer 304 formed from silicon nitride. Afterwards, the sacrificial sacrifice is removed by a dry etching method. Referring to FIG. 3E, a ring-shaped oxide layer (c0ilar oxide laye = 6 is formed on the non-conformal dielectric layer 3 04; the remaining portion = the oxide layer 3 06) ： The remaining part of oxygen. For example, after using # 敎 =, the solution of the conformal dielectric layer 3 0 4 is removed), and the acid solution (hot H3P〇4 aqUeous) is removed. Phase = the -conductivity-the second conductive semiconductor substrate 3 〇f :::: buried trench 3 0 3 around, outside the periphery = = = = = = the first υ buried capacitor In the preferred embodiment, a pair of adjacent buried, fq 1 is formed later. In the preferred embodiment, the diffusion zone 3 007 is: 'around the individual buried trench 3 0 3 type dopant gas. : The scattered area 3 0 7 is preferably formed by incorporating the semiconductor substrate embedded in the trench 3 0 3 529 166 5. Description of the invention (13) = 2 0 0 surface. However, the ring dielectric The surface layer of the semiconductor substrate is continued from 306 to 306, and the surface area of the semiconductor substrate provided with the ugly 302 is not a type of impurity. The unloading domain will not be incorporated into this. Figure and Figure 4b, i # -t fi ^ ^ rt ^ ^ tw A ^ β ^ ^ ^. Ο? Ϊ́; micro f and ㈣ processes to remove each-pair of adjacent: parts of the ring oxide layer 3 〇 6. For the purpose of 壁 =: coating on the semiconductor substrate 300 on the wall, and shifting f. 8 part of the ring-shaped oxide layer 3 0 6. After :: = = = 8 covering 0 〇 Then, Reference is made to the third H and the fourth C diagrams, wherein the plan view of the process steps shows the subsequent cross-sectional schematic diagrams: ;; Figure 2 and Figure 4 along the remaining layers of the chemical layer 3 0 6 ^ # 二 Λ · 糸 is formed on the peripheral wall r Γ that is not placed in the trench 3 0 3: The trench quasi-type electricity is provided for the buried insulation layer that is completed later. The second dielectric layer 3 ◦ 9 is preferably di ox疋 λ silicon oxide composite layer (si 1 icon ni tride / si 1 icon ^ layer) (NO composite layer). This 3:; the formation step of the silicon dioxide composite layer is a low-pressure chemical vapor nitride nitride layer On the inner peripheral wall of the buried trench 3 0 3 which is not covered by the remainder of the ring-shaped oxide layer 3 0 6, and then on the _ le ^ omposite layer) (NO composite layer). People both i… ,, 丄— ..

529166 V. Description of the invention (14) Under the thermal oxidation method, a part of the silicon nitride layer is oxidized into a silicon dioxide layer. Due to the influence of the formation mechanism of the silicon nitride / silicon dioxide composite layer (N0 composlte 丨 ee n =), it will be near the nitride nitride / dioxide 0 9 3 W and the semiconducting f substrate 3 0 0 such as P-type stone. The nitrogen at the substrate interface generates a positive charge on an emulsified silicon bonding layer 3 09. The interface of these positively conductive substrates 300 is, for example, a silicon interface induced reversal 3; semi-inversion layer 3 3 0. This anti-brother Huang Q. It is adjacent to 1 3 0 7 and can be used as buried trench and diffusion area electrode at the same time. It should be noted that, when the nitrided stone eve / dioxin # 化: 1 the first-electric

composi te layer) 3 0 9 The formation of the 稷 σ layer (NO) does not produce the above-mentioned inverse: Next, referring to the third Z diagram, * 1 1 is formed on the semiconductor substrate 3 〇i-conductive A conductive layer 3 channel 3 03. This conductive layer 3 1 1 is supplied by the supplier to fill each of the two electrodes of the buried trench. The conductive layer 3 1 1 is preferably “M” for buried trench capacitors. As a reactive gas, when the polycrystalline silicon layer is doped with a polycrystalline silicon layer, AsH3 is used as a doping = chemical vapor deposition method (situ doping), and phosphorus is doped in situ doping (,, It is better to use the removal-part of the "ring oxide layer 3 :: isotropic dry etching method, with 12) etching gas, and come out in an anisotropic way. You can use doped doped for many days" Even formation Part of the conductive layer is removed by engraving method; ^ 529166 V. Description of the invention (15) Next, the oxide layer is 30 degrees south and the method is removed. conductive layer 3 1. A step of external diffusion is performed to form the second electrode. Of the device. With reference to No. 6, it is exposed. On the strap 1, the conductive belt adjacent to the fire step is charged and buried. According to the above figure, the remaining ring road part in the buried trench 3 03 is removed until it is connected to the conductive layer. 3 丄 丄 Use fluorine-containing etching gas to anisotropic plasma etching f according to the third K picture, a buried conductive strip (buriedx j 3 1 2 is formed in the buried trench 3 03 and implanted with ions An N-type dopant is implanted in the implantation method so that the N-type dopant in the buried conductive tape 3 1 2 is inserted into the half-body substrate 3 0 0 (see the third [picture] 3 1 2 can be electrically connected to A source / drain region of a dynamic random access crystal 3 1 8 (formed by a conductive layer 3 1 1 in a subsequent trench capacitor is described in the following process steps, and the buried trench capacitor can be embedded. The second L Figure 4 and Figure 4d, where Figure 4d is a schematic plan view of the subsequent process steps and Figure 3D is a diagram showing the wearing of a fourth D figure along the line v II-v II. A linear pattern (strip type pattern) 3 1 3 along these rows of buried trenches 3 0 3 pattern direction, define the access transistor for the dynamic random access memory cell array The active region of the source / drain region 3 1 8 of the body. As shown in the third L diagram, a plurality of trench isolation regions 3 1 4 are semiconductor substrates formed over the conductive layer 3 1 2 3 0 〇. Each trench isolation area 3 1 4 is aligned with a buried trench capacitor located below it, and will form the access transistor and buried trench above the trench isolation area 3 1 4 afterwards.

529166

V. Description of the invention (16) The channel capacitors are separated by referring to the third M diagram and the fourth E diagram, in which the Fth, first, and fourth drawings are the top schematic diagrams of the subsequent process steps and the third M diagram is the fourth. The e graph is along the line v τ τ τ v τ τ τ τ a η / viii-v III

Schematic cross-section. An oxide layer is formed on the semiconductor substrate 300 to fill the trench isolation areas 3 1 4, and the oxide layer is planarized by a chemical mechanical polishing method, and the pad oxide layer 3 and the first dielectric are removed at the same time. The electrical layer 3 02, so that the trench isolation area 3 14 can be completed; Thereafter, a doped well region 3 15 having a second conductivity, preferably an N-well, is formed in the semiconductor substrate 300 by an ion implantation method. The doped well region 3 1 5 electrically couples the diffusion regions 3 0 7 serving as the first electrode of the buried trench capacitor to a positive voltage. Next, the fabrication of an access transistor is completed. A free oxide layer 3 16 is formed on the semiconductor substrate 300 above the trench isolation region 3 1 4 by a thermal oxidation method. Thereafter, a conductive gate layer 3 1 7 is formed on the gate oxide layer 3 1 β by a deposition and lithography method. The conductive gate layer 3 1 7 includes a plurality of strip-type conductive gates, and each strip-shaped conductive gate is used as a word line of a dynamic random access memory device. Better here

In a specific embodiment, the conductive gate layer 3 1 7 is formed in such a manner that two pairs of adjacent buried trench capacitors form two shared source / drain regions 3 1 8 (formed in subsequent steps). Access the transistor, see the third μ figure. The conductive gate layer 3 1 7 may include an N-type doped polycrystalline silicon layer and a lithographic crane layer. Then, the source /; is formed by the ion implantation method: and the electrode region ^ 166 ^ 166 V. Description of the invention (17) The source / drain region of the mff transistor is embedded 3 1 8 2Electrical distance J 丄 8 is connected through an electrode, and the two stored thunders are connected to the first connection of the trench capacitor. 5 The source / impulse area shared by the current storage body 3 1 »to Bit-bit line of tragic random access memory elements. :: 8 unit cell array. Where cost · memory with embedded trench-type capacitors-week: = as shown in the figure, the surrounding area of each buried trench-type capacitor can generate additional capacitance, while the traditional buried ones do not use this surrounding area . Therefore, the method of the present invention can reduce the capacitance of the valley device without increasing the buried depth or thinning its dielectric layer. In addition, since the silicon oxide / silicon dioxide composite '' '3 0 9 is used to replace part of the ring-shaped oxide layer 3 6 and a line graph ^ 3 is used to define the active area, there are more conductive layers 3 1 1 and buried ^ conductive. The band 3 1 2 will remain. Therefore, the overall contact resistance of the buried conductive band 3 1 2 can be reduced and well controlled. On the other hand, each side of each buried trench capacitor has a reverse Transfer layer 3 1 7. The reverse layer 3 1 7 can shield the electric field from the second electrode (top electrode) of the buried trench capacitor, so adjacent dynamic random access memory cell cells will not interfere with each other. '' In summary, the method of the present invention has the following advantages over traditional processes: 1 Without increasing the depth of the buried trench capacitor and without thinning its dielectric layer, the capacitance of the buried trench capacitor can be increased. ,

Page 22 529166 V. Description of the invention (18) 2. Since the active area is defined using a linear pattern, the process window of the active area of the pattern I can be greatly improved. 3. The contact resistance of the embedded conductive tape can be reduced and well controlled. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of patent applications.

529166 on page 23 is a diagram that briefly illustrates the first steps A through L, which are cross-sectional schematic diagrams of various steps in the conventional process of a dynamic random access memory cell array with embedded trench capacitors; the second A is the first A Figure B is a schematic top view; Figure B is a schematic top view of Figure K; Figure C is a schematic top view of Figure L; Figures A through M are drawings of a preferred embodiment of the present invention. Sectional schematic diagrams of various process steps; The fourth A diagram is a top schematic diagram of the third A diagram; the fourth B diagram is a top schematic diagram of the third G diagram; the fourth C diagram is a top schematic diagram of the third diagram; the fourth D diagram is The third schematic diagram L is a plan view; and the fourth E diagram is a schematic plan view of a third M diagram. The main part of the symbol: 10 0 P type silicon substrate

Page 24 529166 Brief description of the drawing 1 〇1 Oxide pad 1 0 2 Silicon nitride layer 1 0 3 Ditch 1 0 4 Conformal silicon nitride layer 1 0 5 Sacrificial layer 1 〇6 Ring oxide layer 1 0 7 N-type Diffusion region 1 0 8 Silicon nitride / silicon dioxide composite layer 1 0 9 N-type doped polycrystalline silicon layer 1 1 0 Buried silicon conduction band 1 1 1 Island pattern 1 1 2 Trench isolation area 1 1 3 N well 1 1 4 gate oxide layer 1 1 5 gate layer 1 1 6 source / drain region 3 0 0 semiconductor substrate 3 0 1 pad oxide layer 3 0 2 first dielectric layer 3 0 3 buried trench 3 〇4 conformal Dielectric layer 3 0 5 sacrificial layer 3 0 6 ring oxide layer 3 0 7 diffusion region Φ

529166 Brief description of the drawing 3 0 8 Photoresist layer 3 0 9 Second dielectric layer 3 1 0 Inversion layer 3 1 1 Conductive layer 3 1 2 Buried conductive strip 3 1 3 Linear pattern 3 1 4 Trench isolation area 3 1 5 doped well region 3 1 6 gate oxide layer 3 1 7 conductive gate layer 3 1 8 source / > and electrode region

Page 26

Claims (1)

529166 VI. Scope of patent application1. A manufacturing method with buried trench capacitors, which includes: "The 5th memory cell array provides a first-conductivity-semiconductor substrate; forming a first dielectric An electrical layer on the semiconductor substrate; pattern etching the first dielectric layer to form a plurality of rows of buried trenches on the semiconductor substrate, wherein each row of buried trenches includes a plurality of pairs of adjacent buried trenches Placing trenches, each two pairs of adjacent buried trenches are separated from each other by a predetermined distance; _ forming a conformal dielectric layer in the buried trenches; forming a sacrificial layer in the common trenches Removing a portion of the sacrificial layer so that the height of the first layer is below the surface of the first dielectric layer; removing a portion of the conformal dielectric layer not covered by the sacrificial layer; Remove the remaining portion of the sacrificial layer; a form a ring oxide layer (collar oxide iayer) on each buried trench not covered by the remaining portion of the conformal dielectric layer on the sidewall; remove the conformal The remainder of the dielectric layer; complex π A diffusion region having electrical conductivity opposite to one of the first conductivity and second conductivity is formed in the semiconductor substrate of each of the surrounding portions of the buried trench not covered by the annular oxide layer. It is used as a first electrode of a buried trench capacitor; a part of the ring-shaped oxide layer on the inner side wall of each pair of adjacent buried trenches adjacent to each other is removed by a stacking process and a # engraving process. Page 27 529166 6. The scope of the patent application forms a second dielectric layer on the inner peripheral wall of each buried trench that is not covered by the annular oxide layer. The forming step includes an oxidation reaction to induce the second dielectric layer. An interface between the layer and the semiconductor substrate generates an inversion layer (inversi ο η 1 ayer) adjacent to the diffusion region, and the second dielectric layer is used as an insulation layer of the buried trench capacitor; A conductive layer having the second conductivity is filled on the semiconductor substrate to fill each of the buried trenches, and the conductive layer is used as a second electrode of the buried trench-type capacitor; the conductive layer is removed to the top Part of the ring-shaped oxide layer is exposed; removing the exposed ring-shaped oxide layer; forming a buried conductive strap with the second conductivity in the first conductive layer in each of the buried trenches Top; using a linear pattern (striptypepa 11 er η) along the direction of the buried trench patterns to define a plurality of active areas on the semiconductor substrate; forming an oxide layer on the semiconductor substrate The conductive substrate is filled with the buried trenches. The oxide layer is planarized to form a trench isolation region on each of the buried trench-type capacitors. A well region having the second conductivity is formed in the semiconductor substrate. The well region is electrically connected to the diffusion regions; a gate oxide layer is formed on the semiconductor substrate; a conductive gate layer is formed on the gate oxide layer, and the conductive gate is formed mmi Page 28 529166 6. The patent application layer includes a plurality of strip-shaped conductive gates, each of which is used as a word line of a dynamic random access memory cell array; and forms a pair The source / drain regions having the second conductivity are respectively in the semiconductor substrate on each side of the strip-shaped conductive gate, and one of the source / drain regions is electrically connected to the buried conductive strip. And another source / drain is used as a bit line of the dynamic random access memory cell. 2. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, wherein the first conductivity is N-type conductivity and P-type conductivity. Either. 3. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, wherein the semiconductor substrate described above includes a P-type chipped substrate. 4. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, further comprising forming a pad oxide layer before the formation of the first dielectric layer. 5. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, wherein the first dielectric layer includes a silicon nitride layer. 6.Motion with buried trench capacitor as described in item 1 of the scope of patent application Page 29 529166 VI. Scope of patent application Manufacturing method of a state random access memory cell array, wherein the above-mentioned conformal dielectric layer includes a silicon nitride layer. -7. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 6 of the scope of the patent application, wherein the above silicon nitride layer uses a mixed gas of SiH2Cl2 & NH3 as a reaction The gas is formed by a low pressure chemical vapor deposition method. 8. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, wherein the sacrificial layer includes a oxide layer. 9. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, wherein the sacrificial layer is removed by an anisotropic dry etching method. 10. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 8 of the scope of the patent application, wherein the above silicon oxide layer uses a fluorine-based etchant (fluorine-based etchant). ) Remove by plasma etching. jp 1 1. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, wherein the conformal dielectric layer not covered by the sacrificial layer is formed by Anisotropic dry etching method is removed. Page 30 529166 VI. Application scope of patent = · As mentioned in the patent application ^ Patent scope item 6 with embedded trench-type capacitors 2 P! Take the memory daily cell array manufacturing method, where the above is not The silicon nitride layer of the sacrificial f 1 / I disk is removed by a plasma etching method using a fluorine-containing etching gas (inebasedetcha η ΐ). As described in item 1 of the scope of the patent application, the method of manufacturing a buried trench capacitor I = 稗 access memory cell array manufacturing method, wherein the aforementioned ring-shaped oxygen transport is formed by a thermal oxidation method in an oxygen-containing environment. 4 The method for manufacturing a mobile Ik-type memory cell array with a buried trench capacitor described in item 1 of the scope of the patent application, wherein the remaining part of the conformal interlayer is immersed in wet etching Method (dip we t etching) removed. &Amp; A method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 6 of the scope of the patent application, wherein the remainder of the above silicon nitride layer is immersed using a phosphoric acid solution Wet etching method (dip wet etching) removed. · The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, wherein the above-mentioned diffusion region uses a thermal diffusion method to provide the first Two conductive dopant gases are formed by doping the semiconductor substrate. Page 31 529166 VI. Scope of patent application 1 7. The method for manufacturing a dynamic-state random access memory cell array with a buried trench capacitor as described in item 1 of the scope of patent application, wherein each of the above is removed The lithography and etching process of a portion of the annular oxide layer on the adjacent inner sidewall of an adjacent buried trench includes forming a photoresist layer on the semiconductor substrate, and etching a portion not covered by the photoresist layer. Part of the annular oxide layer. 1 8. The method for manufacturing a dynamic state memory cell array with a buried trench capacitor according to item 1 of the scope of the patent application, wherein the second dielectric layer includes a nitride / Fabrication of SiO 2 composite layer (N 0 c 0m ρ 〇site · layer) o 1 9. Manufacturing of a dynamic random access memory cell array with a buried trench capacitor as described in item 18 of the scope of patent application A method, wherein the step of forming the silicon nitride / silicon dioxide composite layer includes depositing a silicon nitride layer on a peripheral wall of each buried trench not covered by the annular oxide layer by a low-pressure chemical vapor deposition method, and The silicon nitride layer is partially oxidized into an oxide layer by thermal oxidation in an oxygen-containing environment. 20. The method for manufacturing a dynamic random access memory cell array with a buried trench capacitor as described in item 1 of the scope of the patent application, wherein the aforementioned conductive layer comprises a doped polycrystalline silicon having one of the second conductivity properties. Floor. 2 1. The capacitors with buried trench capacitors as described in item 20 of the scope of patent application Page 32 529166 6. Scope of patent application = manufacturing method of machine-access memory cell array, the above-mentioned doped outer day sand layer is formed by in-situ doping (i n-s i t u dop i ng) polycrystalline silicon deposition method. '= .. The method of manufacturing a mobile random access memory cell array with a buried trench capacitor as described in item 1 of the patent scope, wherein the conductive layer is made of an anisotropic material & Removed dry engraving method. The method for manufacturing a machine-access memory cell array with a buried trench capacitor described in item 20 of the scope of the patent application, wherein the above-mentioned doped polycrystalline silicon layer uses an etchant containing chl (Hne speceies) was removed by plasma etching. = · The operation of the buried trench capacitor described in item 1 of the scope of the patent application is based on the manufacturing method of the memory cell array, in which the exposed ^% oxide layer is fluorinated etching gas to electrically Removed by slurry etching method. The method for manufacturing an embedded memory cell according to item 1 of the patent application No. 1 in the scope of patent application, wherein the power-supply belt system includes an erbium-doped layer. tv A method for manufacturing a dynamic random access memory cell array as described in item 25 of the patent application scope: > Medium? The formation steps of the second stone layer include the use of M as the reaction gas 2 = page 529166. 6. Application for a patent scope. A vapor deposition method is used to deposit a non-^^ layer and doping the amorphous layer by ion implantation. Shi Xi layer, this non-two state 7 · As described in the item Λ, the scope of the patent, the method of making a memory cell array with embedded trenches, A, the active state of the active state Including the doped polycrystalline method in which the above-mentioned two pieces of conductivity 8., which include a dynamic random access memory element including a buried trench capacitor, tth-conductive-semiconductor substrate; substrate i (acc One-to-one in the semiconductor-second conductor: sexually charged in contrast to the first-conductive :: connected to a bit line and-the drain;? Connected to a sub-line,-the source is connected to a plurality of substrates, The trench isolation zone sharing a buried trench adjacent to the trench isolation zone is located at the buried trench-capacitive buried guide pair of adjacent trenches and a pair of phases. The second conductive system is located at both. The access transistor is placed between the trench-type electricity, and each of the buried one is in the buried one. Access the two of the source; each adjacent pair of channel capacitors is aligned with the _ electric band (bUri conductive band and >) and the electric semiconductor is connected to the semiconductor under the buried trench transistor The transistor system is located under two trench isolation areas of the buried trench, and each of the trench isolation areas and an ed conductive strap share the two connections of the source, where the pair of adjacent buried trench capacitors Including the 529166 VI. Application for the scope of patent application: embedded lightning guides,-oxidation: the buried trench; the inner side wall is opposite to each other; the trench capacitor is not the oxygen core-conductive layer Filling capacity: the first electrode with a conductive tape and the dielectric layer at a degree of 2 °, and passing through the drain electrode of the 2 transistor, is formed at the angle of each of the buried trench capacitors. In a semiconductor substrate, the pair of the different diffusion regions are connected to each other, and a layer) is formed on the dielectric layer and the adjacent to the diffusion region, the second electrode of the channel capacitor of the diffusion region; and A pair of 0-channel-type electrical trenches in the well with the second conductivity, an inner peripheral layer of the dielectric layer cap of the capacitor in the container is interposed between each, and the second conductivity The buried trench-type transfer layer adjacent to the oxide layer (an transfer layer between the substrates is provided for the embedding to be used as the conductive band and an anti-semiconductor and the upper part of the opposite sidewall has the oxygen formed in On each wall, a trench-type capacitor with the trench-type capacitor is electrically coupled to the diffusion region. The inversion interface of the surrounding capacitor of the cap is electrically connected to each of the diffused trenches. The dynamic randomness of the embedded trench-type capacitors as described in item 28 of the patent application scope is random. Access memory element, wherein the first conductivity is any of N-type and P-type conductivity. 30. Dynamic random access with embedded trench capacitor as described in item 28 of the scope of patent application The memory device, wherein the above-mentioned semiconductor substrate system includes a Shi Xi substrate. Page 35 529166 VI. Scope of patent application 3 1. The dynamic random access memory device with buried trench capacitor as described in item 28 of the scope of patent application, wherein the above-mentioned dielectric layer includes a nitride stone / dioxide stone Evening composite layer (NO composite layer). 3 2. The dynamic random access memory device with a buried trench capacitor as described in item 28 of the scope of the patent application, wherein the above-mentioned embedded conductive tape includes a doped amorphous silicon layer. 3 3. The dynamic random access memory device with a buried trench capacitor as described in item 28 of the scope of the patent application, wherein the conductive layer includes a doped polycrystalline silicon layer. Page 36