JP2012054454A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can form a thick silicide layer while inhibiting occurrence of short circuits between gate electrodes and a semiconductor substrate caused by silicide layer growth.SOLUTION: The semiconductor manufacturing method comprises the steps of forming gate electrodes 51, 52 on a side face of a pillar 26 via a gate insulator 27, forming an upper impurity diffusion region 36 on a top edge of the pillar 26, forming a cylinder hole 71 penetrating interlayer insulators 39, 68 formed on the upper impurity diffusion region 36 and exposing a top face of the upper impurity diffusion region 36, forming a silicon film 42 at the bottom part of the cylinder hole 71 to cover the top face of the upper impurity diffusion region 36 and fill a part of the cylinder hole 71, and forming a lower electrode 57 so as to cover a top face of the silicon film 42 and an inner surface of the cylinder hole 71 above the silicon film 42 while forming a silicide layer 43 by reacting Si contained in the silicon film 42 with a metal contained in the lower electrode 57 by use of heat generated in forming the lower electrode 57.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, semiconductor devices (specifically, semiconductor elements) have been miniaturized. Therefore, when a DRAM (Dynamic Random Access Memory) is used as a semiconductor device and a DRAM memory cell is miniaturized, a selection transistor and a capacitor constituting the memory cell are reduced, so that a sufficient capacity of the capacitor is ensured. Has become difficult.

  In order to solve this problem, the capacitor is three-dimensionalized to increase the surface area of the electrodes constituting the capacitor, and the structure of the capacitor may be shifted from a MIS (Metal Insulator Semiconductor) structure to a MIM (Metal Insulation Metal) structure. It is done.

  In Patent Document 1, in order to reduce the resistance between an MIM capacitor composed of a lower electrode, a capacitive insulating film, and an upper electrode, and a capacitive contact plug to which the MIM capacitor is connected, a lower electrode and a capacitive contact plug are provided. It is disclosed to form a silicide layer therebetween.

Here, the method for forming the MIM capacitor and the silicide layer described in Patent Document 1 will be briefly described.
First, a capacitive contact plug made of an impurity-containing polycrystalline silicon film is formed which is electrically connected to an impurity diffusion region (source region) constituting the transistor.
Next, an interlayer insulating film is formed on the capacitor contact plug. Next, a cylinder hole reaching the upper surface of the capacitor contact plug is formed in the interlayer insulating film by anisotropic etching.

Next, a titanium (Ti) film covering the upper end surface of the capacitor contact plug exposed from the cylinder hole and the inner peripheral surface of the cylinder hole, and a titanium nitride (TiN) film covering the surface of the titanium (Ti) film are sequentially stacked. Thus, the lower electrode is formed.
At this time, Ti contained in the titanium (Ti) film constituting the lower electrode reacts with silicon contained in the capacitor contact plug to form a silicide layer on the capacitor contact plug.
Thereafter, a MIM capacitor is formed by sequentially forming a capacitive insulating film covering the lower electrode and an upper electrode covering the capacitive insulating film.

Patent Documents 2 and 3 disclose three-dimensional transistors in which transistors are formed in pillars extending perpendicularly to the main surface of a semiconductor substrate as techniques for miniaturizing DRAM memory cells.
The three-dimensional transistor described in Patent Document 3 is formed by etching a silicon substrate and functions as a channel, an upper impurity diffusion region (source region) formed at the upper end of the pillar, and between pillars and between pillars. A gate insulating film formed on the side surface of the gate insulating film, a gate electrode formed on the gate insulating film, a lower impurity diffusion region (drain region) formed in a silicon substrate located below the gate electrode, and an upper impurity diffusion region A titanium silicide layer formed thereon; and a contact plug formed on the titanium silicide layer.

Although not described in Patent Document 3, generally, the contact plug described in Patent Document 3 is connected to the MIM capacitor disclosed in Patent Document 1 or Patent Document 2.
The three-dimensional transistor having the above-described configuration has an advantage that a large drain current can be obtained due to a small occupied area and complete depletion, and a close-packed layout of 4F ² (F is the minimum processing dimension) can be realized. Is possible.

JP 2008-192650 A JP 2008-288391 A JP 2010-80756 A

By the way, when a memory cell including a three-dimensional transistor is configured with a 4F ² type close-packed layout, a bit line and a word line (including a gate electrode) are embedded between pillars (in a semiconductor substrate). Without providing a contact plug, a silicide layer is formed on the upper impurity diffusion region made of silicon, and the upper impurity diffusion region and the lower electrode of the MIM capacitor are electrically connected through the silicide layer.

  By the way, when the semiconductor device is further miniaturized, the diameter of the cylinder hole is further reduced, and the contact resistance between the capacitor and the upper impurity diffusion region is increased. Therefore, the thickness of the silicide layer is made thicker than before. There is a need.

  However, since the aspect ratio of the cylinder hole (= cylinder hole depth / cylinder hole diameter) is higher than that of the conventional cylinder hole, titanium (Ti) formed on the upper impurity diffusion region exposed from the bottom surface of the cylinder hole ) The thickness variation of the film becomes large, and it becomes difficult to make the thickness of the silicide layer formed on the plurality of pillars uniform.

  Therefore, when the growth of the silicide layer is promoted in order to increase the thickness of the silicide layer, in the pillar in which the silicide layer is formed thicker than other pillars, the distance between the gate electrode and the silicide layer is too close. Then, the silicide layer reaches the gate insulating film formed on the side surface of the pillar, the gate insulating film is eroded and destroyed, and the gate electrode and the semiconductor substrate are short-circuited.

  According to one aspect of the present invention, a step of forming a pillar by partially etching a main surface of a semiconductor substrate, a step of forming a gate electrode on a side surface of the pillar via a gate insulating film, Forming an upper impurity diffusion region on an upper end of the pillar; forming an interlayer insulating film on the upper impurity diffusion region; and exposing the upper surface of the upper impurity diffusion region through the interlayer insulating film. Forming a cylinder hole; forming a silicon film covering the upper surface of the upper impurity diffusion region and burying a part of the cylinder hole at a bottom of the cylinder hole; and an upper surface of the silicon film; A lower electrode serving as a capacitor is formed so as to cover an inner surface of the cylinder hole located above the silicon film, and heat generated when the lower electrode is formed, The method of manufacturing a semiconductor device including a step of forming a silicide layer by reacting the metal contained in the Si and the bottom electrode included in the silicon film is provided.

  According to the method of manufacturing a semiconductor device of the present invention, the cylinder hole penetrating the interlayer insulating film formed on the upper impurity diffusion region and exposing the upper surface of the upper impurity diffusion region is formed, and then the bottom of the cylinder hole And forming a silicon film that covers the upper surface of the upper impurity diffusion region and burying a part of the cylinder hole, and then covering the upper surface of the silicon film and the inner surface of the cylinder hole located above the silicon film, A silicide electrode is formed by reacting Si contained in the silicon film with a metal contained in the lower electrode by forming a lower electrode serving as a capacitor and by heat generated when the lower electrode is formed. A sufficient distance from the gate electrode can be secured.

  This prevents the silicide layer from reaching the gate insulating film in contact with the gate electrode even when the silicide layer is thickened (in other words, the portion of the gate insulating film in contact with the gate electrode is eroded and destroyed by the silicide layer). Therefore, the occurrence of a short circuit between the gate electrode and the semiconductor substrate can be suppressed.

1 is a plan view schematically showing a memory cell array provided in a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the memory cell array shown in FIG. 1 in the AA line direction. FIG. 2 is a cross-sectional view of the memory cell array shown in FIG. 1 in the BB line direction. FIG. 3B is a diagram (part 1) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and a sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 4B is a diagram (part 1) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and a sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2B; FIG. 3B is a diagram (part 2) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and a sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 8B is a diagram (part 2) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and a sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2B; FIG. 3D is a diagram (part 3) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 8B is a diagram (No. 3) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 4B is a diagram (part 4) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, and is a cross-sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 4D is a diagram (part 4) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2B; FIG. 8B is a diagram (part 5) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the present invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array illustrated in FIG. 2A; FIG. 6B is a view (No. 5) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 6D is a diagram (No. 6) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 6D is a view (No. 6) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 7B is a view (No. 7) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 8B is a view (No. 7) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 8B is a view (No. 8) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 8B is a view (No. 8) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 9B is a diagram (No. 9) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 9D is a diagram (No. 9) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 10B is a view (No. 10) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 10B is a view (No. 10) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B; FIG. 11B is a view (No. 11) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, which is a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2A; FIG. 12B is a view (No. 11) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment of the invention, and a cross-sectional view corresponding to a cut surface of the memory cell array shown in FIG. 2B;

  Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. Note that the drawings used in the following description are for explaining the configuration of the embodiment of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationship of an actual semiconductor device. There is.

(Embodiment)
FIG. 1 is a plan view schematically showing a memory cell array provided in a semiconductor device according to an embodiment of the present invention. 2A is a cross-sectional view of the memory cell array shown in FIG. 1 in the AA line direction, and FIG. 2B is a cross-sectional view of the memory cell array shown in FIG. 1 in the BB line direction.
In FIG. 1, the X direction indicates the extending direction of the word line 29, and the Y direction indicates the extending direction of the bit line 21 that intersects the word line 29. For convenience of explanation, FIG. 1 shows only the bit line 21, the word line 29, the silicide layer 43, and the capacitor 45 among the components of the memory cell array 11 shown in FIGS. 2A and 2B.
2A and 2B, the same components as those of the memory cell array 11 shown in FIG. 1, 2 </ b> A, and 2 </ b> B, a DRAM (Dynamic Random Access Memory) is taken as an example of the semiconductor device of this embodiment, and the following description is given.

  The semiconductor device 10 of this embodiment includes a memory cell region in which the memory cell array 11 shown in FIGS. 1, 2A, and 2B is formed, and a peripheral circuit (not shown) arranged around the memory cell region. And a peripheral circuit region to be formed. In the peripheral circuit region, peripheral circuit transistors (for example, planar transistors) (not shown) are formed.

Next, the configuration of the memory cell array 11 will be described with reference to FIGS. 1, 2A, and 2B.
The memory cell array 11 includes a semiconductor substrate 13, an element isolation region (not shown), a bit line forming groove 15, insulating films 16 and 23, a bit contact 18, a lower impurity diffusion region 19, and a bit line 21. A word line forming groove 25, a pillar 26, a gate insulating film 27, a word line 29, buried insulating films 31, 35, a groove 32, a liner film 33, an upper impurity diffusion region 36, 1 etching stopper film 38, first interlayer insulating film 39, second etching stopper film 41, silicon film 42, silicide layer 43, support film 44, capacitor 45, and third interlayer insulating film. A film 46, a wiring 47, and a fourth interlayer insulating film 48 are included.

2A and 2B, the semiconductor substrate 13 is a substrate containing an impurity having a predetermined concentration. As the semiconductor substrate, for example, a p-type silicon substrate can be used. Hereinafter, a case where a p-type silicon substrate is used as the semiconductor substrate 13 will be described as an example.
The semiconductor substrate 13 includes an element isolation region (not shown) constituted by an element isolation groove (not shown) and an element isolation insulating film (not shown) that fills the element isolation groove, and the element isolation. And an element forming region formed inside the region and having a rectangular shape.
A silicon oxide film (SiO ₂ film) is used as the element isolation insulating film. The structure of the element isolation region is called STI (Shallow Trench Isolation). The element formation region is an active region that is insulated and isolated by an element isolation region.

Referring to FIG. 2A, the bit line forming groove 15 is formed in the semiconductor substrate 13. A plurality of bit line forming grooves 15 are arranged in the X direction so as to extend in the Y direction. A bit line 21 is formed at the bottom of the bit line forming groove 15.
The insulating film 16 is provided on the inner surface of the bit line formation groove 15 corresponding to the formation region of the bit line 21 (specifically, a part of the side surface and the bottom surface of the bit line formation groove 15). Yes. The insulating film 16 has an opening 16A in which the bit contact 18 is formed. The opening 16A is formed so as to expose a part of the side surface of the pillar 26. As the insulating film 16, a silicon oxide film (SiO ₂ film) can be used.

The bit contact 18 is provided so as to fill the opening 16 </ b> A formed in the insulating film 16. As a material of the bit contact 18, for example, a polycrystalline silicon film containing an n-type impurity (for example, arsenic (As)) can be used.
The lower impurity diffusion region 19 is an impurity diffusion region containing an n-type impurity (for example, arsenic (As)), and functions as a drain region. The lower impurity diffusion region 19 is formed in a portion of the pillar 26 that is in contact with the bit contact 18.

The bit line 21 (buried bit line) is formed at the bottom of the bit line forming groove 15 with the insulating film 16 interposed therebetween. The upper surface 21a of the bit line 21 is a flat surface. The bit lines 21 extend in the Y direction, and a plurality of bit lines 21 are arranged in the X direction (see FIG. 1). The bit line 21 is in contact with the bit contact 18 and is electrically connected to the lower impurity diffusion region 19 through the bit contact 18.
The bit line 21 is composed of a conductive film. As the conductive film constituting the bit line 21, for example, a laminated film in which a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film are sequentially laminated can be used.

Referring to FIG. 2A, the insulating film 23 is formed so as to cover the upper surface 21 a of the bit line 21 and the side surface of the bit line forming groove 15 positioned above the bit line 21. As the insulating film 23, for example, a SiON film can be used.
2A and 2B, the word line forming groove 25 is formed in the semiconductor substrate 13 so as to intersect the bit line forming groove 15. The word line forming grooves 25 are formed to extend in the X direction, and a plurality of word line forming grooves 25 are arranged in the Y direction.

2A and 2B, the pillar 26 is surrounded by the bit line forming groove 15 and the word line forming groove 25, and has a columnar shape. The pillar 26 uses the semiconductor substrate 13 as a base material, and is formed by partially etching the main surface 13a of the semiconductor substrate 13 to process the bit line forming groove 15 and the word line forming groove 25.
An upper impurity diffusion region 36 is formed at the upper end of the pillar 26. A portion of the pillar 26 located between the upper impurity diffusion region 36 and the lower impurity diffusion region 19 functions as a channel.

A lower impurity diffusion region 19, an upper impurity diffusion region 36, a gate insulating film 27, and a pair of gate electrodes 51 and 52, which will be described later, are formed in the pillar 26, so that a vertical MOS (Metal Oxide) that is a three-dimensional transistor is formed. A semiconductor transistor 50 is formed. That is, in the memory cell array 11, a plurality of vertical MOS transistors 50 are formed in a matrix.
The vertical MOS transistor 50 has the advantage that the occupied area is small and a large drain current can be obtained by complete depletion. Therefore, in the memory cell array 11, by providing a plurality of the vertical MOS transistors 50, a close-packed layout of 4F ² (F is the minimum processing dimension) can be realized.

Referring to FIG. 2B, the gate insulating film 27 includes side surfaces 26a and 26b (including side surfaces of the upper impurity diffusion region 36) of the plurality of pillars 26 arranged in the X direction, and a bottom surface 25a of the word line forming trench 25. It is formed so as to cover. Examples of the gate insulating film 27 include a single-layer silicon oxide film (SiO ₂ film), a film obtained by nitriding a silicon oxide film (SiON film), a stacked silicon oxide film (SiO ₂ film), and a silicon oxide film (SiO ₂ ). A laminated film in which a silicon nitride film (SiN film) is laminated on ( _two films) can be used.

Referring to FIG. 1, the word line 29 includes a pair of gate electrodes 51 and 52, an electrode end connection portion 53, and a connection portion 55.
Referring to FIGS. 1 and 2B, the gate electrode 51 extends in the X direction and is provided on the side surfaces 26 a of the plurality of pillars 26 via the gate insulating film 27. The gate electrode 52 extends in the X direction, and is provided on the side surfaces 26 b of the plurality of pillars 26 via the gate insulating film 27. The gate electrode 52 is disposed to face the gate electrode 51 through the gate insulating film 27 and the plurality of pillars 26.
Referring to FIG. 1, the electrode end connection portions 53 are provided at both ends of the gate electrodes 51 and 52, respectively, and are configured integrally with the ends of the gate electrodes 51 and 52.

Referring to FIGS. 1 and 2A, the connecting portion 55 is provided in the bit line forming groove 15 located between the gate electrodes 51 and 52 via the insulating film 23. One end of the connecting portion 55 is configured integrally with the gate electrode 51, and the other end of the connecting portion 55 is configured integrally with the gate electrode 52. The connection portion 55 is a member for reducing the difference in electrical resistance of the word line 29 in the X direction.
The word line 29 configured as described above can be formed of a conductive film. As the conductive film constituting the word line 29, for example, a stacked film in which a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film are sequentially stacked can be used.

Referring to FIG. 2A, the buried insulating film 31 is provided so as to fill the bit line forming groove 15 located on the connecting portion 55. The upper surface 31 a of the buried insulating film 31 is a flat surface and is flush with the main surface 13 a of the semiconductor substrate 13. As the buried insulating film 31, for example, an insulating film having excellent filling characteristics and a dense film quality may be used. Specifically, as the buried insulating film 31, for example, a silicon oxide film (SiO ₂ film) formed by HDP (High Density Plasma) method may be used.

  Referring to FIG. 2B, the groove 32 extends in the X direction and is formed in the word line forming groove 25. The width of the groove 32 in the Y direction is narrower than the width of the word line forming groove 25 in the Y direction. The trench 32 is embedded in the word line formation trench 25, and a conductive film (not shown) which is a base material of the word line 29 is separated into two, thereby forming a pair of gate electrodes 51 and 52. This is a separation groove. Therefore, the depth of the groove 32 is configured to be deeper than the depth of the word line forming groove 25 so that the conductive film as the base material of the word line 29 can be reliably separated into two.

Referring to FIG. 2B, the liner film 33 is provided in the word line forming groove 25 and formed in a sidewall shape on the gate electrodes 51 and 52. The liner film 33 is an insulating film. As the liner film 33, for example, a SiON film can be used. The upper surface of the liner film 33 is a flat surface and is flush with the main surface 13 a of the semiconductor substrate 13.
Referring to FIG. 2B, the buried insulating film 35 is provided so as to fill the trench 32. The upper surface of the buried insulating film 35 is a flat surface and is flush with the main surface 13 a of the semiconductor substrate 13.

2A and 2B, the upper impurity diffusion region 36 is formed on the upper end of the pillar 26 (the main surface 13a of the semiconductor substrate 13). An upper surface 36 a of the upper impurity diffusion region 36 corresponds to the main surface 13 a of the semiconductor substrate 13.
The upper impurity diffusion region 36 is an impurity diffusion region containing an n-type impurity (for example, arsenic (As)), and functions as a source region. The upper surface 36 a of the upper impurity diffusion region 36 is disposed above the upper surface of the word line 29.

2A and 2B, the first etching stopper film 38 includes a main surface 13a of the semiconductor substrate 13 where the upper impurity diffusion region 36 is not formed, an upper surface of the liner film 33, and buried insulating films 31 and 35. Is provided so as to cover the upper surface. A silicon nitride film (SiN film) is used as the first etching stopper film 38. In this case, the thickness of the first etching stopper film 38 can be set to, for example, 50 nm.
The first interlayer insulating film 39 is provided on the first etching stopper film 38. As the first interlayer insulating film 39, a silicon oxide film (SiO ₂ film) is used. In this case, the thickness of the first interlayer insulating film 39 can be set to 400 nm, for example.

The second etching stopper film 41 is provided on the first interlayer insulating film 39. A silicon nitride film (SiN film) is used as the second etching stopper film 41. In this case, the thickness of the second etching stopper film 41 can be set to, for example, 50 nm.
The silicon film 42 is provided on the upper impurity diffusion region 36. The silicon film 42 is a film having conductivity, and is a film on which the silicide layer 43 is formed. As the silicon film 42, for example, a polycrystalline silicon film containing impurities can be used. Specifically, as the silicon film 42, for example, a polycrystalline silicon film containing about 22E19 (/ cm ³ ) of phosphorus (P) which is an n-type impurity can be used.
When the thickness of the first etching stopper film 38 is 50 nm, the thickness of the first interlayer insulating film 39 is 400 nm, and the thickness of the second etching stopper film 41 is 50 nm, before the silicide layer 43 is formed. The thickness of the silicon film 42 can be, for example, not less than 100 nm and less than 500 nm.

The silicide layer 43 is formed on the silicon film 42 and on a part of the bottom of the lower electrode 57 constituting the capacitor 45. When the lower electrode 57 is a laminated film in which a titanium (Ti) layer 63, a titanium nitride (TiN) layer, and 64 are sequentially laminated, a titanium silicide layer is formed as the silicide layer 43.
The titanium silicide layer is included in the Ti and silicon films 42 included in the titanium (Ti) layer 63 by forming a titanium (Ti) layer 63 constituting the lower electrode 57 by CVD (Chemical Vapor Deposition). It is formed by reacting with Si.

At this time, the silicide layer 43 grows downward (in the direction toward the upper impurity diffusion region 36). The silicide layer 43 is a layer for reducing the contact resistance between the capacitor 45 and the upper impurity diffusion region 36.
Further, a TiSi ₂ layer may be used as the titanium silicide layer. The TiSi ₂ layer has the lowest electrical resistance among the silicide layers, and is stable even when a natural oxide film (silicon oxide film (SiO ₂ film)) is formed on the surfaces of the polycrystalline silicon and the upper impurity diffusion region 36. This is because the solid-phase reaction proceeds (Ti reacts by reducing the silicon oxide film).

  In this way, by providing the silicon film 42 between the upper surface 36a of the upper impurity diffusion region 36 and the lower electrode 57 and forming the silicide layer 43 on the silicon film 42, the silicide layer 43 and the gate electrodes 51, 52 are formed. It is possible to ensure a sufficient distance between the two.

  Thereby, even when the thickness of the silicide layer 43 is increased (for example, 30 to 50 nm), the silicide layer 43 does not reach the gate insulating film 27 corresponding to the formation region of the gate electrodes 51 and 52 (in other words, in other words) For example, the gate insulating film 27 is not eroded and destroyed by the silicide layer 43), so that the occurrence of a short circuit between the gate electrodes 51 and 52 and the silicide layer 43 and the semiconductor substrate 13 can be suppressed.

The support film 44 is disposed above the second etching stopper film 41. As the support film 44, a silicon nitride film (SiN film) is used. The support film 44 is in contact with an outer peripheral side surface 57a on the upper end side of a plurality of lower electrodes 57 to be described later. As a result, the support film 44 connects the plurality of lower electrodes 57.
A through-hole 61 is formed in the support film 44 (see FIG. 2B). The through portion 61 is an inlet for an etching solution for removing a second interlayer insulating film 68 shown in FIGS. 9A and 9B described later by wet etching. The second interlayer insulating film 68 is formed in a peripheral circuit region (not shown).

By removing the second interlayer insulating film 68, a space 62 is formed between the second etching stopper film 41 and the support film 44. The distance between the support film 44 and the second etching stopper film 41 is equal to the thickness of the second interlayer insulating film 68 shown in FIGS. 9A and 9B, and can be, for example, 900 nm.
Further, the thickness of the support film 44 can be set to 100 μm, for example. In FIG. 2B, only one through portion 61 is illustrated, but actually, a plurality of through portions 61 are formed in the support film 44.

The capacitor 45 is an MIM capacitor and is provided on the silicide layer 43. One capacitor 45 is provided for each of the plurality of pillars 26. That is, the memory cell array 11 has a plurality of capacitors 45.
The capacitor 45 includes one lower electrode 57, a capacitor insulating film 58 (in other words, a capacitor insulating film common to the plurality of lower electrodes 57) formed so as to extend over the plurality of lower electrodes 57, and a capacitor insulating film. And an upper electrode 59 (in other words, an upper electrode common to the plurality of lower electrodes 57).
The lower electrode 57 has a crown shape. The lower electrode 57 is connected to another lower electrode 57 by the support film 51. The lower electrode 57 has a structure in which a titanium (Ti) film 63 (hereinafter simply referred to as “titanium film 63”) and a titanium nitride (TiN) film 64 (hereinafter simply referred to as “titanium nitride film 64”) are sequentially stacked. It is said that. The thickness of the titanium film 63 can be set to 10 nm, for example.

The capacitor insulating film 58 includes inner surfaces of the plurality of lower electrodes 57, outer peripheral side surfaces 57a of the plurality of lower electrodes 57 positioned between the second etching stopper film 41 and the support film 44, and upper surfaces of the second etching stopper films 41. 41 a, the upper surface 44 a and the lower surface 44 b of the support film 44, and the side surface of the support film 44 that constitutes the through portion 61.
As the capacitor insulating film 58, for example, a laminated film in which an aluminum oxide film (Al ₂ O ₃ film) and a zirconium oxide film (ZrO ₂ film) are sequentially laminated can be used.

The upper electrode 59 fills the plurality of lower electrodes 57, the through-holes 61, and the spaces 62 via the capacitive insulating film 58, and is formed on the capacitive insulating film 58 positioned on the upper surface 44 a of the support film 44. .
The upper surface 59a of the upper electrode 59 is a flat surface. As the upper electrode 59, a metal film such as a ruthenium (Ru) film, a tungsten (W) film, a titanium nitride (TiN) film, a polycrystalline silicon film, or the like can be used.

The third interlayer insulating film 46 is provided on the upper surface 59 a of the upper electrode 59. As the third interlayer insulating film 46, for example, a silicon oxide film (SiO ₂ film) can be used.
The wiring 47 is provided on the third interlayer insulating film 46. The wiring 47 is electrically connected to the upper electrode 59 disposed in the lower layer.
The fourth interlayer insulating film 48 is provided on the third interlayer insulating film 46 so as to cover the wiring 47. As the fourth interlayer insulating film 48, for example, a silicon oxide film (SiO ₂ film) can be used.

According to the semiconductor device of the present embodiment, the silicon film 42 is provided between the upper surface 36 a of the upper impurity diffusion region 36 and the lower electrode 57, and the silicide layer 43 is formed on the silicon film 42 in contact with the lower electrode 57. Thus, a sufficient distance between the silicide layer 43 and the gate electrodes 51 and 52 can be secured.
Thereby, even when the silicide layer 43 is thickened, the silicide layer 43 does not reach the gate insulating film 27 corresponding to the formation region of the gate electrodes 51 and 52 (in other words, the silicide layer 43 causes the gate insulating film 27 to be formed). Therefore, the occurrence of a short circuit between the gate electrodes 51 and 52 and the semiconductor substrate 13 can be suppressed.

  In addition, since the distance between the silicide layer 43 and the gate electrodes 51 and 52 is sufficiently secured, in order to further reduce the contact resistance between the capacitor 45 and the upper impurity diffusion region 36, Even when the growth is promoted, occurrence of a short circuit between the gate electrodes 51 and 52 and the silicide layer 43 and the semiconductor substrate 13 can be suppressed.

3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, and 11A 11B, FIG. 12A, FIG. 12B, FIG. 13A, and FIG. 13B are diagrams showing a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment of the present invention.
3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are cross-sectional views corresponding to the cut surface of the memory cell array 11 shown in FIG. 2A. It is.

3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B correspond to the cut surface of the memory cell array 11 shown in FIG. 2B. It is sectional drawing.
3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, and 11A 11B, FIG. 12A, FIG. 12B, FIG. 13A, and FIG. 13B, the same components as those in the memory cell array 11 shown in FIG. 2A and FIG.

  Next, FIGS. 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B. , FIG. 11A, FIG. 11B, FIG. 12A, FIG. 12B, FIG. 13A, and FIG. 13B, a method for manufacturing the semiconductor device 10 (specifically, the memory cell array 11) according to the embodiment of the present invention will be described. To do.

First, in the process shown in FIGS. 3A and 3B, an element isolation groove (not shown) is formed in the semiconductor substrate 13, and then an element isolation insulating film (silicon oxide film (SiO 2) embedded in the element isolation groove is formed. ₂ film)), an element isolation region (not shown) is formed. Thus, an element formation region (active region) disposed inside the element isolation region is formed.
As the semiconductor substrate 13, for example, a p-type silicon substrate can be used. In the following description, a case where a p-type silicon substrate is used as the semiconductor substrate 13 is described as an example.

Next, a hard mask (not shown) made of a silicon nitride film is formed on the main surface 13a of the semiconductor substrate 13 by photolithography and dry etching. Next, the main surface 13a of the semiconductor substrate 13 is partially etched by dry etching using the hard mask (not shown) as a mask, thereby forming a plurality of bit line forming grooves 15 extending in the Y direction. To do. Next, the insulating film 16 is formed so as to cover a portion corresponding to the formation region of the bit line 21 among the inner surfaces of the plurality of bit line forming grooves 15.
At this stage, the opening 16 A is not formed in the insulating film 16.
Next, a polycrystalline silicon film (not shown) containing arsenic (As) is formed through the insulating film 16 so as to fill the bit line forming groove 15 at a position lower than the formation region of the opening 16A. To do. Next, a portion of the insulating film 16 corresponding to the formation region of the bit contact 18 is selectively etched to form an opening 16A that exposes the semiconductor substrate 13.

Next, a plurality of bit line forming grooves are formed by growing a polycrystalline silicon film (not shown) containing arsenic (As) on a polycrystalline silicon film (not shown) containing arsenic (As). 15 is embedded.
Next, the polycrystalline silicon film (not shown) containing arsenic (As) formed in the plurality of trenches 15 for bit line formation is removed by etch back, and arsenic (As) is contained only in the opening 16A. By leaving the polycrystalline silicon film (not shown), a bit contact 18 made of a polycrystalline silicon film (not shown) containing arsenic (As) is formed in the opening 16A.

Next, a conductive film serving as a base material of the bit line 21 is formed by an CVD method in an atmosphere heated to a predetermined temperature (for example, 650 ° C.). Specifically, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film are sequentially stacked as a conductive film that becomes a base material of the bit line 21.
At this time, arsenic (As) contained in the bit contact 18 is thermally diffused into the semiconductor substrate 13 corresponding to the formation region of the pillar 26 due to heat at the time of forming the conductive film. As a result, the lower impurity diffusion region 19 is formed in a portion corresponding to the side wall of the pillar 26.
Next, the conductive film is etched back to leave the conductive film at the bottom of the bit line forming groove 15, thereby forming the bit line 21 extending in the Y direction.

Next, an insulating film 23 is formed to cover the upper surface 21 a of the bit line 21 and the side surface of the bit line forming groove 15 positioned above the bit line 21. As the insulating film 23, for example, a SiON film can be used.
Next, a coating-type silicon oxide film (SiO ₂ film) (not shown) is formed by a SOG (Spin On Glass) method in a portion of the bit line formation groove 15 corresponding to the formation region of the connection portion 55. . Then, by HDP (High Density Plasma) method, on the silicon oxide film of the coating system (SiO ₂ film), a silicon oxide film (SiO ₂ film) to embed the bit lines forming grooves 15 by forming the buried insulating A film 31 is formed.

Next, the main surface 13a of the semiconductor substrate 13 is partially etched to form a plurality of word line forming grooves 25 that intersect the bit line forming grooves 15 and extend in the Y direction. The word line forming groove 25 is formed by the same method as the bit line forming groove 15 described above. At this time, the word line forming groove 25 is formed so as to completely expose a coating type silicon oxide film (not shown) formed by the SOG method.
As a result, a plurality of pillars 26 made of the semiconductor substrate 13 and surrounded by the bit line forming grooves 15 and the word line forming grooves 25 are formed. In other words, the pillars 26 are formed by partially etching the main surface 13 a of the semiconductor substrate 13.

  Next, a silicon oxide film (not shown) of the coating system formed by the SOG method is selectively removed by wet etching. Thereafter, the inner surface of the word line formation groove 25 (specifically, the bottom surface 25a of the word line formation groove 25 and the side surfaces of the word line formation groove 25 corresponding to the side surfaces 26a and 26b of the plurality of pillars 26) is covered. A gate insulating film 27 is formed. As a result, the gate insulating film 27 is formed on the side surfaces 26 a and 26 b of the plurality of pillars 26.

Examples of the gate insulating film 27 include a single-layer silicon oxide film (SiO ₂ film), a film obtained by nitriding a silicon oxide film (SiON film), a stacked silicon oxide film (SiO ₂ film), and a silicon oxide film (SiO ₂ ). A laminated film in which a silicon nitride film (SiN film) is laminated on ( _two films) can be used.

Next, a conductive film serving as a base material of the word line 29 is formed by CVD so as to fill the bit line forming groove 15 and the word line forming groove 25 corresponding to the formation region of the connection portion 55.
Specifically, a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film are sequentially formed. As a result, a plurality of connection portions 55 made of a conductive film are formed in the bit line forming groove 15. At this time, an electrode end connection portion 53 (see FIG. 1) not shown is also formed at the same time.
Next, the conductive film formed in the word line forming groove 25 is etched back, and the thickness of the remaining conductive film is set to a predetermined thickness. The remaining conductive film serves as a base material for the pair of gate electrodes 51 and 52.

Next, a groove 32 having a width smaller than that of the word line forming groove 25 and extending in the X direction and dividing the conductive film remaining in the word line forming groove 25 into two in the word line forming groove 25. Form.
As a result, the gate electrode 51 is formed on the side surface 26 a of the plurality of pillars 26 via the gate insulating film 27, and the gate electrode 52 is formed on the side surface 26 b of the plurality of pillars 26 via the gate insulating film 27. The
That is, at this stage, the word line 29 including the electrode end connection portion 53, the connection portion 55, and the pair of gate electrodes 51 and 52 extending in the X direction is formed.

Next, a liner film 33 is formed on the gate electrodes 51 and 52 so as to be in contact with the gate insulating film 27. As the liner film 33, for example, a SiON film can be used.
Next, the word line forming trench 25 and the trench 32 are filled with a buried insulating film 35. As the buried insulating film 35, a coated silicon oxide film (SiO ₂ film) formed by the SOG method may be used.
Next, a hard mask (mask used when forming the bit line forming groove 15) (not shown) is removed. As a result, the upper surfaces of the plurality of pillars 26 (main surface 13a of the semiconductor substrate 13) are exposed.

Next, arsenic (As) is doped as an n-type impurity on the top surfaces of the plurality of pillars 26 (the main surface 13a of the semiconductor substrate 13), and then the arsenic (As) is thermally diffused, whereby the top ends of the plurality of pillars 26 are obtained. Then, an upper impurity diffusion region 36 (impurity diffusion region) is formed. Thereby, the vertical MOS transistors 50 are formed in the plurality of pillars 26.
Thereafter, the main surface 13a side of the semiconductor substrate 13 is polished to form a structure having a flattened upper surface as shown in FIGS. 3A and 3B.

4A and 4B, a planar transistor (not shown) is formed as a peripheral circuit transistor in a peripheral circuit region (not shown) by a well-known method.
Next, the first etching stopper film 38, the first interlayer insulating film 39, the second etching stopper film 41 (etching stopper film), and the second interlayer are formed on the structure shown in FIGS. 3A and 3B. An insulating film 68 and a support film 44 are sequentially formed.
Specifically, for example, a silicon nitride film (SiN film) having a thickness of 50 nm as the first etching stopper film 38, and a silicon oxide film (SiO ₂ film) having a thickness of 400 nm as the first interlayer insulating film 39, A silicon nitride film (SiN film) with a thickness of 50 nm as the second etching stopper film 41, a silicon oxide film (SiO ₂ film) with a thickness of 900 nm as the second interlayer insulating film 68, and a thickness of 100 nm as the support film 44 The silicon nitride film (SiN film) is sequentially formed.

The first etching stopper film 38 is formed by anisotropic etching (specifically, dry etching), a second etching stopper film 41, first and second interlayer insulating films 39 and 68, which are interlayer insulating films, And it functions as an etching stopper film when the cylinder hole 71 (see FIGS. 5A and 5B) penetrating the support film 44 is formed.
In addition, the second etching stopper film 41 is formed when the second interlayer insulating film 68 formed in the memory cell region is removed by wet etching in the process shown in FIGS. 10A and 10B described later. It has a function of preventing the structure disposed below the stopper film 41 from being etched. That is, the second etching stopper film 41 functions as a stopper film at the time of wet etching.

Further, the second etching stopper film 41 connects the lower portions of the plurality of lower electrodes 57, so that the second interlayer insulating film 68 formed in the memory cell region in the process shown in FIGS. 10A and 10B described later. Has a function of connecting the plurality of lower electrodes 57.
In addition, the through-hole 61 shown in FIG. 2B described above is not yet formed in the support film 44 at this stage. That is, the support film 44 shown in FIGS. 4A and 4B is an unpatterned film.

  Next, in the process shown in FIGS. 5A and 5B, the support film 44, the second interlayer insulating film 68, the second etching stopper film 41, the first etching film are anisotropically etched (specifically, dry etching). By etching the interlayer insulating film 39 and the first etching stopper film 38, a cylinder hole 71 exposing the upper surface 36a of the upper impurity diffusion region 36 is formed.

Specifically, an opening (not shown) exposing the upper surface 44a of the support film 44 corresponding to the formation region of the cylinder hole 71 on the upper surface 44a of the support film 44 shown in FIGS. 4A and 4B by photolithography. A photoresist (not shown) having is formed.
Next, as a first step, a second etching stopper film 41 made of a support film 44 and a silicon nitride film (SiN film), and first and second interlayer insulating films 39 made of a silicon oxide film (SiO ₂ film). The first and second interlayer insulating films 39, 68, the support film 44, and the second etching stopper film 41 are dry-etched using the same etching conditions. The first hole (through the first interlayer insulating film 39 and the second etching stopper film 41, and the bottom surface is located between the second etching stopper film 41 and the first etching stopper film 38 ( A plurality of (not shown) are formed. The first hole is a hole that becomes a part of the cylinder hole 71.

Next, as a second step, there is a selectivity with respect to a condition for selectively etching the first interlayer insulating film 39 made of a silicon oxide film (SiO ₂ film) (in other words, a silicon nitride film (SiN film)). The first interlayer insulating film 39 is dry etched until the upper surface of the first etching stopper film 38 is exposed.
Thereby, a formation region of a first hole (not shown) and a plurality of second holes (not shown) formed below the first hole and deeper than the first hole are formed. To do.

Next, as a third step, the first etching stopper film 38 made of a silicon nitride film (SiN film) is used to selectively etch the first impurity until the upper surface 36a of the upper impurity diffusion region 36 is exposed. The etching stopper film 38 is dry etched.
As a result, a plurality of cylinder holes 71 are formed, which are formed below the second hole (not shown) and below the second hole, and are deeper than the second hole.
The cylinder hole 71 is a hole in which the lower electrode 57 is formed, and is formed so as to expose the upper surface 36 a of the upper impurity diffusion region 36. Thereafter, the photoresist (not shown) is removed.

The thickness of the first etching stopper film 38 is 50 nm, the thickness of the first interlayer insulating film 39 is 400 nm, the thickness of the second etching stopper film 41 is 50 nm, and the thickness of the second interlayer insulating film 68 is When the thickness of the support film 44 is 900 nm and the diameter R of the cylinder hole 71 can be set to 60 nm, for example. In this case, the depth D of the cylinder hole 71 can be 1500 nm.
When the cylinder hole 71 is formed, a guard wall groove (not shown) having a ring shape surrounding the memory cell region is formed. The guard wall trench is formed so as to penetrate at least the support film 44, the second interlayer insulating film 68, and the second etching stopper film 41.

Next, in the process shown in FIGS. 6A and 6B, a silicon film 42 is formed to fill the plurality of cylinder holes 71 and cover the upper surface of the support film 44.
Specifically, the silicon film 42 is formed by a CVD method. As the silicon film 42, for example, a polycrystalline silicon film containing about 22E19 (/ cm ³ ) of phosphorus (P) which is an n-type impurity is formed.
Further, when the diameter R of the cylinder hole 71 is 60 nm, the thickness of the silicon film 42 formed on the plane can be set to 100 nm, for example.

Next, in the process shown in FIGS. 7A and 7B, the silicon film 42 shown in FIGS. 6A and 6B is entirely etched back to leave the silicon film 42 at the bottom of the cylinder hole 71. A silicon film 42 is formed.
By the way, when the upper surface 42a of the silicon film 42 after the etch back is positioned above the upper surface 41a of the second etching stopper film 41, the position of the lower electrode 57 formed on the upper surface 42a of the silicon film 42 is The second etching stopper film 41 is disposed above the upper surface 41a.
As a result, the second etching stopper film 41 and the outer peripheral surface of the lower electrode 57 are not connected, and an intrusion path for the etching solution is formed between the second etching stopper film 41 and the lower electrode 57.

For this reason, in the process shown in FIGS. 10A and 10B, which will be described later, the etching solution penetrates from between the second etching stopper film 41 and the lower electrode 57 and is formed under the second etching stopper film 41. The first interlayer insulating film 39, the silicon film 42, the vertical MOS transistor 50, etc. are etched.
Therefore, in the process shown in FIGS. 7A and 7B, the etch back is performed such that the position of the upper surface 42a of the silicon film 42 after the etch back is disposed below the position of the upper surface 41a of the second etching stopper film 41. To do.

  When the thickness of the first etching stopper film 38 is 50 nm, the thickness of the first interlayer insulating film 39 is 400 nm, and the thickness of the second etching stopper film 41 is 50 nm, the height of the silicon film 42 after the etch back is increased. The upper limit of the height H (height with respect to the upper surface 36a of the upper impurity diffusion region 36) needs to be smaller than 500 nm. In this case, the height H of the silicon film 42 is preferably 100 nm or more and less than 500 nm.

Next, in the process shown in FIGS. 8A and 8B, the upper surface 42a of the silicon film 42 shown in FIGS. 7A and 7B and the position higher than the silicon film 42 in an atmosphere heated to a predetermined temperature by the CVD method. A titanium film 63 serving as a base material of the lower electrode 57 is formed so as to cover the side surface of the cylinder hole 71 to be formed.
At this time, the titanium film 63 reacts with Ti contained in the titanium film 63 (metal contained in the lower electrode 57) and Si contained in the silicon film 42 by heat generated when the titanium film 63 is formed. A TiSi ₂ layer that is a silicide layer 43 is formed in the vicinity of the silicon film 42 (specifically, mainly the silicon film 42). At this time, the titanium film 63 is also formed on the support film 44.
The titanium film 63 is formed to have a thickness of 10 nm in an atmosphere heated to a high temperature of 650 ° C. (an example of a predetermined temperature), for example.

At this time, most of the titanium film 63 formed on the silicon film 42 is a TiSi ₂ layer. The silicide layer 43 is also formed on the silicon film 42, and the silicide layer 43 grows below the silicon film 42 by promoting the growth of the silicide layer 43.

  As described above, the silicon film 42 that covers the upper surface 36a of the upper impurity diffusion region 36 and fills a part of the cylinder hole 71 is formed at the bottom of the cylinder hole 71 exposing the upper surface 36a of the upper impurity diffusion region 36, and then The titanium film 63 to be the lower electrode 57 is formed by the CVD method so as to cover the upper surface 42a of the silicon film 42 and the side surface of the cylinder hole 71 located above the silicon film 42. The distance between the silicide layer 43 and the gate electrodes 51 and 52 is formed by reacting Si contained in the silicon film 42 with Ti contained in the titanium film 63 by heat during film formation to form the silicide layer 43. Can be secured sufficiently.

  As a result, even when the thickness of the silicide layer 43 is increased, the silicide layer 43 does not reach the gate insulating film 27 corresponding to the formation region of the gate electrodes 51 and 52 (in other words, the gate is formed by the silicide layer 43. Since the insulating film 27 is not eroded and destroyed, the occurrence of a short circuit between the gate electrodes 51 and 52 and the silicide layer 43 and the semiconductor substrate 13 can be suppressed.

Furthermore, as the silicide layer 43, a TiSi ₂ layer having a resistance lower than that of other silicide layers (for example, WSi ₂ layer) is formed, so that the contact resistance is reduced as compared with the case where other silicide layers are used. Can be lowered.

Next, a titanium nitride film 64 that covers the surface of the titanium film 63 is formed. The thickness of the titanium nitride film 64 can be set to 20 nm, for example. Further, since the N ₂ gas is supplied during the growth of the TiN film, the titanium film 63 that has not reacted with Si contained in the silicon film 42 is reduced to TiN and becomes a titanium nitride (TiN) film.

Thereafter, unnecessary titanium film 63 and titanium nitride film 64 formed on support film 44 are removed by etching, so that lower electrode 57 made of titanium film 63 and titanium nitride film 64 is formed in a plurality of cylinder holes 71. Form.
Specifically, for example, the plurality of cylinder holes in which the titanium film 63 and the titanium nitride film 64 are formed are filled with a photoresist, and then the support film 44 is formed by anisotropic etching (specifically, dry etching). A plurality of lower electrodes 57 are formed by removing the unnecessary titanium film 63 and titanium nitride film 64 formed thereon. Thereafter, the photoresist is removed.

8A and 8B, a titanium film 63 and a titanium nitride (TiN) film 64 are formed on the inner surface of the guard wall groove (not shown), and the guard wall groove (not shown). The titanium film 63 and the titanium nitride film 64 are left on the inner surface of the film. The titanium film 63 and the titanium nitride film 64 formed in the guard wall groove (not shown) function as a guard wall (not shown).
10A and 10B, which will be described later, the guard wall is formed by removing the second interlayer insulating film 68 formed in the memory cell region with an etching solution when the second interlayer insulating film 68 formed in the peripheral circuit region is removed. It has a function of preventing the etching solution from reaching the interlayer insulating film 68.

Next, in the process shown in FIGS. 9A and 9B, a through portion 61 exposing the second interlayer insulating film 68 formed below the support film 44 is formed in the support film 44 shown in FIGS. 8A and 8B. Thus, the support film 44 is formed in contact with the outer peripheral surface 57 a at the upper end of the plurality of lower electrodes 57 and connecting the plurality of lower electrodes 57.
Specifically, the through portion 61 is an opening that exposes the upper surface 44a of the support film 44 corresponding to the formation region of the through portion 61 on the upper surface 44a of the support film 44 illustrated in FIGS. 8A and 8B by photolithography. A photoresist (not shown) having (not shown) is formed, and then the upper surface of the second interlayer insulating film 68 is formed by anisotropic etching (specifically, dry etching) using the photoresist as a mask. The support film 44 is etched until it is exposed. Thereafter, the photoresist (not shown) is removed.
9A and 9B, only one penetration 61 is shown, but in the process shown in FIGS. 9A and 9B, a plurality of penetrations 61 are actually formed.

Next, in the process shown in FIG. 10A and FIG. 10B, wet capable of selectively etching the second interlayer insulating film 68 on the second interlayer insulating film 68 formed in the memory cell region via the through portion 61. By supplying the etching solution, the second interlayer insulating film 68 surrounded by the guard wall (not shown) is selectively removed. Thereby, a space 62 is formed between the second etching stopper film 41 and the support film 44.
As the wet etchant, an etchant that selectively etches the silicon oxide film (in other words, an etchant having a selectivity with respect to the second etching stopper film 41 and the support film 44) is used. Specifically, for example, hydrofluoric acid (HF) is used as the wet etching solution.

The space 62 includes an upper surface 41 a of the second etching stopper film 41, a lower surface 44 b of the support film 44, and outer peripheral side surfaces 57 a of the plurality of lower electrodes 57 positioned between the second etching stopper film 41 and the support film 44. And an inner wall (not shown) of the guard wall are exposed.
At this time, since the second etching stopper film 41 prevents the wet etching solution from penetrating into the lower layer of the memory cell region 11, the first interlayer insulating film 39, the silicide layer 43, the silicon film 42, and The already formed transistor (for example, the vertical MOS transistor 50) or the like is not damaged.

Next, in the process shown in FIGS. 11A and 11B, the space 62 is partitioned from the upper surface side of the structure shown in FIGS. 10A and 10B by the ALD (Atomic Layer Deposition) method through the penetration part 61. A capacitor insulating film 58 covering the surface to be formed is formed.
As a result, the capacitive insulating film 58 includes a plurality of upper surfaces 41 a of the second etching stopper film 41, upper and lower surfaces 44 a and 44 b of the support film 44, and a plurality of portions that are located between the second etching stopper film 41 and the support film 44. The lower electrode 57 is formed to cover the outer peripheral side surface 57a.
As the capacitor insulating film 58, for example, a laminated film made of an aluminum oxide film (Al ₂ O ₃ film) and a zirconium oxide film (ZrO ₂ film) can be used.

  Next, in the step shown in FIGS. 12A and 12B, the surface of the capacitive insulating film 58 is covered by the CVD method from the upper surface side of the structure shown in FIGS. A conductive film to be filled is formed. The conductive film is a film that becomes a base material of the upper electrode 59. For example, a metal film such as a ruthenium (Ru) film, a tungsten (W) film, a titanium nitride (TiN) film, or a polycrystalline silicon film is used. be able to.

Next, the conductive film is polished by a CMP (Chemical Mechanical Polishing) method to form an upper electrode 59 made of the conductive film and having a flat upper surface 59a.
As a result, a plurality of capacitors 45 (MIM capacitors) including the lower electrode 57, the capacitor insulating film 58, and the upper electrode 59 are formed above the upper impurity diffusion region 36.

  Further, a space exposing the upper surface 41 a of the second etching stopper film 41, the lower surface 44 b of the support film 44, and the outer peripheral side surfaces 57 a of the plurality of lower electrodes 57 between the second etching stopper film 41 and the support film 44. 62, and then a capacitor insulating film 58 is formed to cover the surface partitioning the space 62, and then an upper electrode 59 that fills the space 62 is formed on the surface of the capacitor insulating film 58. Can be increased.

13A and 13B, a third interlayer insulating film 46 is formed on the upper surface 59a of the upper electrode 59. The third interlayer insulating film 46 can be formed by a CVD method. Further, as the third interlayer insulating film 46, a silicon oxide film (SiO ₂ film) is used.
Next, a wiring 47 that is electrically connected to the upper electrode 59 is formed on the third interlayer insulating film 46 by a known method.
Next, a fourth interlayer insulating film 48 is formed on the third interlayer insulating film 46 so as to cover the wiring 47. The fourth interlayer insulating film 48 can be formed by a CVD method. As the fourth interlayer insulating film 48, a silicon oxide film (SiO ₂ film) is used. Thereby, the semiconductor device 10 of the present embodiment is manufactured.

  According to the method for manufacturing a semiconductor device of the present embodiment, the stacked first etching stopper film 38, first interlayer insulating film 39, second etching stopper film 41, second interlayer insulating film 68, and At the bottom of the cylinder hole 71 that penetrates the support film 44 and exposes the upper surface 36a of the upper impurity diffusion region 36, a silicon film 42 that covers the upper surface 36a of the upper impurity diffusion region 36 and that embeds a part of the cylinder hole 71 is formed. Then, a titanium film 63 serving as the lower electrode 57 is formed by CVD so as to cover the upper surface 42a of the silicon film 42 and the side surface of the cylinder hole 71 located above the silicon film 42, The silicide layer 43 is formed by reacting Si contained in the silicon film 42 with Ti contained in the titanium film 63 by heat at the time of forming the titanium film 63. By forming, it is possible to sufficiently ensure the distance between the silicide layer 43 and the gate electrodes 51 and 52.

  As a result, even when the thickness of the silicide layer 43 is increased, the silicide layer 43 does not reach the gate insulating film 27 corresponding to the formation region of the gate electrodes 51 and 52 (in other words, the gate is formed by the silicide layer 43. Since the insulating film 27 is not eroded and destroyed, the occurrence of a short circuit between the gate electrodes 51 and 52 and the semiconductor substrate 13 can be suppressed.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

  The present invention is applicable to a method for manufacturing a semiconductor device.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Memory cell array, 13 ... Semiconductor substrate, 13a ... Main surface, 15 ... Bit line formation groove, 16, 23 ... Insulating film, 16A ... Opening, 18 ... Bit contact, 19 ... Lower impurity diffusion Region 21... Bit line 21 a, 31 a, 36 a, 41 a, 42 a, 44 a, 59 a ... upper surface, 25 ... word line forming groove, 25 a ... bottom surface, 26 ... pillar, 27 ... gate insulating film, 29 ... word line, 31, 35 ... buried insulating film, 32 ... groove, 33 ... liner film, 36 ... upper impurity diffusion region, 38 ... first etching stopper film, 39 ... first interlayer insulating film, 41 ... second etching stopper film , 42 ... Silicon film, 43 ... Silicide layer, 44 ... Support film, 44 b ... Bottom surface, 45 ... Capacitor, 46 ... Third interlayer insulating film, 47 ... Wiring, 48 ... Fourth interlayer insulation Membrane, 51, 52 ... Gate electrode, 53 ... Electrode end connection portion, 55 ... Connection portion, 57 ... Lower electrode, 57a ... Outer peripheral surface, 58 ... Capacitance insulating film, 59 ... Upper electrode, 61 ... Through portion, 62 ... Space , 63 ... titanium (Ti) film, 64 ... titanium nitride (TiN) film, 68 ... second interlayer insulating film, 71 ... cylinder hole, D ... depth, H ... height, R ... diameter

Claims (11)

Forming a pillar by partially etching the main surface of the semiconductor substrate;
Forming a gate electrode on a side surface of the pillar via a gate insulating film;
Forming an upper impurity diffusion region at the upper end of the pillar;
Forming an interlayer insulating film on the upper impurity diffusion region;
Forming a cylinder hole penetrating the interlayer insulating film and exposing an upper surface of the upper impurity diffusion region;
Forming a silicon film at the bottom of the cylinder hole, covering the upper surface of the upper impurity diffusion region and burying a part of the cylinder hole;
A lower electrode serving as a capacitor is formed so as to cover an upper surface of the silicon film and an inner surface of the cylinder hole located above the silicon film, and the silicon film is formed by heat at the time of forming the lower electrode. Forming a silicide layer by reacting Si contained in the metal with the metal contained in the lower electrode;
A method of manufacturing a semiconductor device including: The lower electrode is formed by a CVD (Chemical Vapor Deposition) method to form a Ti film that covers an upper surface of the silicon film and an inner surface of the cylinder hole located above the silicon film, and a surface of the Ti film Forming a TiN film covering the substrate,
The method of manufacturing a semiconductor device according to claim 1, wherein a TiSi ₂ layer is formed as the silicide layer.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a polycrystalline silicon film containing impurities is formed as the silicon film. Forming a plurality of the pillars and forming the lower electrode for each of the plurality of pillars;
Forming an etching stopper film connecting the plurality of lower electrodes in the interlayer insulating film;
Forming a support film connecting upper ends of the plurality of lower electrodes on the interlayer insulating film,
4. The method of manufacturing a semiconductor device according to claim 1, wherein the cylinder hole is formed so as to penetrate the etching stopper film and the support film.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the silicon film is formed so that an upper surface of the silicon film is positioned below an upper surface of the etching stopper film.   6. The method of manufacturing a semiconductor device according to claim 4, wherein a through portion that penetrates the support film is formed after the formation of the lower electrode.   The interlayer insulating film disposed between the support film and the etching stopper film is selectively removed by introducing an etching solution having a low etching rate of the etching stopper film and the support film from the through portion. 7. The method of manufacturing a semiconductor device according to claim 6, wherein a space exposing the upper surface of the etching stopper film, the lower surface of the support film, and the outer peripheral side surfaces of the plurality of lower electrodes is formed.   The capacitor is formed so as to cover the inner surface of the lower electrode, the upper surface of the support film, the outer peripheral side surface of the lower electrode exposed by the space, the upper surface of the etching stopper film, and the lower surface of the support film. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a capacitor insulating film is formed.   9. The method of manufacturing a semiconductor device according to claim 8, wherein an upper electrode serving as the capacitor is formed so as to cover the surface of the capacitive insulating film and fill the space.   10. The method according to claim 1, further comprising: forming a bit line extending in a direction intersecting with an extending direction of the gate electrode on the semiconductor substrate positioned below the gate electrode. Among them, the manufacturing method of the semiconductor device of any one of Claims.   11. The method according to claim 1, further comprising: forming a lower impurity diffusion region electrically connected to the bit line in a portion of the pillar located below the upper impurity diffusion region. A method for manufacturing a semiconductor device according to claim 1.

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