TWI234821B - Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures - Google Patents

Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures Download PDF

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TWI234821B
TWI234821B TW092130221A TW92130221A TWI234821B TW I234821 B TWI234821 B TW I234821B TW 092130221 A TW092130221 A TW 092130221A TW 92130221 A TW92130221 A TW 92130221A TW I234821 B TWI234821 B TW I234821B
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dielectric
group
metal
cap
trench
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TW092130221A
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TW200410341A (en
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Stefanie R Chiras
Michael W Lane
Sandra G Malhotra
Fenton Read Mcfeely
Robert Rosenberg
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Ibm
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1234821 招-ΐί:之領域有關於金屬’例如_，之使用，其能展 之：散體位於半導體積體電路之線與内部互聯中時 "”電遷移（electromigration )性質，更特定难 說’關於此等材斜於卜卜莖且古 ^ 、 +麗麻 枓 專具有一介電材料與具有自行對準 金屬巾目盖層之積體電路中導體之形成。 【先前 於 (v i as 界中發 (mult 而成線 料所隔 其具有 在增進 電流的 示了污 保 (bar r 極地被 然而， 料具備 於 道是， 技術】 積體電路與半導體晶片結構中，用於 )、線與其他圖案與内聯線之内部互 展的相當的健全。在此等結構中，多 ilevel wiring patterns)被嵌埋於 圖案與中介窗被介電材料以不同介電 開。像是銅之材料一直在業界中受到 能夠藉由降低導體阻性而增進性能之 性能之慾望所驅使時之愈來愈小的尺 物理條件下，此等材料擴散與電遷移 染與漏電控制以及可靠性上難以解決 護層’通常以「襯底（liners)」、 iers)」或「帽蓋（caps)」等術語 採用以限制外向擴散（outd i f f us i 〇n 任何保護材料也必須在結構中，對於 良好之附著性。 現今的最先進技藝中，所提到的問題 藉由使·用’對於在石夕基材上之銅導體 作為中 聯技術 層成線 介電材 性質之 注目， 潛力。 寸與增 之性質 的問題 「勢壘 稱呼之 )與電 各種的 介窗 於本業 圖案 料中， 介電材 是因為然而， 加中的 ，卻顯 ’均積 遷移。 介電材 的一種解決之 線使用二氧化
4IBM0389TW-替換頁-〇12105.ptc
1234821 MM 92130^ 五、發明說明（2) 而，ί:3料’與氮化矽材料作為帽蓋材料。然 相對= ί:ΐ;::料，具有理想的高阻性質亦具有 的有效介電常數，而可以用來增加結構（Keff) .. ⑥数同時也會不利地影響層内 (intralevel )電容。 問題另：包ί ί決：案’亦針對於銅材料的擴散與電遷移 低二Ϊ二Ϊ能夠選擇藉由週遭介電材料維持理想 Ξ = ^ Ϊ材料的能力，而達成所希望的結果。此項 申請案中，並讓與本孝J讓斤人申7 μ序號09/361，573之 程序中，包括始鎢碟積於=術裡’於二步驟 蓋。所沉籍的*居帝^ )積，製造自行對準金屬帽 中達成了採相沾覆蓋與保護銅表面的頂端，因此在結構 $二】：的附著力’並扮演電遷移時的阻抗。 k )金屬門1入雷要近一步尋求的是，低介電常數（low )金屬間"電材料似乎有著更具前途之性質。 中伴二積體電路技術中有更簡單程序上的需求，其 22=導體材料而免於擴散與電遷移效應，但又 可以女置於可選擇低Keff介電結構中。 【内容】
與擴散敏 在化學 可選擇 屬之性 包圍。 中， 於一
於積體電路技術中，提供一種對 感’例如銅’金屬之導性元件與處理 機械平坦化處理過之介表面，導性元 Ke f f介電材料中。此金屬被具有抗原 質’並作為用以覆蓋此金屬之薄膜帽
4IBM0389TW-替換頁 _〇12i〇5.ptc 第9頁
1234821 修正 五、發明說明（3) 此帽蓋提供環境保護並具有用於進一步處理之催化性。本 發明的技術提供一中間導性元件產物（interfflediate conductive element product)以及在許多半導體積體結 構中可作為成線（w i r i ng )導體與内連線之製造方法。 。、導性元件由在將被化學機械平坦化處理之介表面，與 可選擇之，較佳者為（低K )介電物中，形成一安置溝渠 jaccommodating trench )所製得。此溝渠以，由一層或 材^ I ί 由金屬向較佳之（低κ)介電材料外向擴散之 科或材料群所組成之區域加以内 護帽蓋:。將夺，其於金屬上形成一自行對準之保 循環施加於内溝渠部份。將退火溫度 導性开杜ί溝 構之金屬來形成保護帽蓋。 移除任何殘餘的内襯姑粗版产亚卞一衣甶破千坦化，以 介電物種，若需要的話，；從平：士 金屬材料。 露出溝渠的底部來作為後續的接觸。h蝕掉’以暴 【實施方法】
於業界的最弁i隹A 之金屬，例如鋼，作4 ^ =以對於擴散與電遷移敏感 的主要問題導因於：ίίϊ;體與内連線來發展積體電路 電物之擴散的污¥,Μ乃二電介面由於離開金屬進入介 料之反應。木以及在金屬與下一階段介面與其他材 發明擴散-電遷移侔螬夕道 ---冤遷移保濩之導體元 第10頁 替換頁-0121〇5ptc 1234821 94 1. 21
件之剖面圖。於圖丨中，在延伸至介電物2之溝渠1中，其 =經平面化學機械平坦化處理（CMp)之表面3下方延伸， 發明擴散-電遷移保護之導體元件4位於沿著之溝渠1之 則邊與底部之襯底5中。在襯底5中之銅導體6具有與襯底5 ^外側表面8對準之帽蓋7，以及當作（CMp)平坦化加工 修正 /洗（processed flush)之表面3。於需要時之進一步使 用中，介電材料2可進一步被cmp處理，而從下方在一將被 Γ Ϊ化之表面，對暴露出之導體其以虛線所標示為9A，以 *路出導體6之底部，與對應於帽蓋7具有帽蓋之9B。
、請參閱圖2A-2G提供結構之部份產物說明，以例示形 成本發明使用金屬銅為導體之受擴散-電遷移保護之導體 製造步驟，其甲之元件符號於適當處盡量對應於先 圖中所使用者。 請參閱圖1與自圖2A開始之圖 ,. —— 介電材料2之層 11，其可為基於Si〇2、SILK、FSG、SiC0H與Si之低κ介電
物群組之成員，通常由Si、C、0、與Η所組成，並且有像 是CORAL與BUckDIAMOND或其相似之商標，係位於;象是矽 氧化物等材料之基材上，例如具有丨〇 〇 〇 —丨〇 〇 〇 〇埃之深度， y以具有大約等同於或是稍大於有待形成之導體6之設計 高度之階（order)。表面12係暴露出來。此時，介電材 料2，用於層11中，的性質在選擇上可以有彈性，而 可以選擇低K介電物。 參閱圖2B °暴露出的表面12以微影石刻式地 一 材料13 ’使得暴露出區域14以供生產操作。罩材^13 任# # A f 1 g想、的侵#操作具有抗性，例如穿透區
1234821 修正
案號 92130221 五、發明說明（5) 域1 4之化學或是反應性離子蝕刻。 、請參閱圖2C，其例示說明於介電層u中溝渠15的 成，其可由像是化學或是反應性離子蝕刻之 ^ 達_〇〇，_埃之深度形成，其具有大約等同以 稍大於有待形成之導體6之設計高度之等級（〇rder )、,疋 於圖2D中，標示為元件16之内襯區域可以以如物 目二積(PVD )’也就是濺鍍或其類似者、化學氣相沉積 JCJD)、原子層沉積（ALD)、無電極或電解沉積 桁 :積在溝，中。區域16係用來覆蓋溝渠15的侧邊與底衡 邛，起初得以覆蓋表面12。元件16可為單一或是八 的層，合金或是結構的相，可以以一/ @刀1 形成，此三元層由鎢與釕（Ru) ‘^lnary)層為例 可為TaN/Ta/Ru、TiW/Ru、TiN/Ru。區域 了 選擇的^ 合 =製造一種亦可在結構中作為催化功：之金金^ 元素加以置換。 兜錄銘、翻、銥、銀等 ^域16的功能是用來提供與容於溝紐 制外向擴散與電遷移有關的能力，並作為屬= 過：被提供之導體金屬而擴散離開區二16，：之後 斜灯對準之帽蓋。内襯區域層16可由下列選出. :化：群或其組合’而Β可選自他、錄、 群，、 釕、與銀，而Β層的厚度<100埃。 测 m 金襯裡A (B) ’前述之組成物關係成立，而 比例。之厚度在約3〇 — 1234821 修正 魅 9213Π?' 五、發明說明（6) 米。埃之範圍内，線寬度間隔（sPacing )大約為〇· 1微 *内心示填塞操作的發生。其中在溝渠15 +、^敌^域（〇Pen Portion)，使用標示為元素 積摔二二之：體金屬之沉積操作來加以填塞。此沉、 導體金屬選擇Λ4之標準技術，如電解或無電極電鍍。當 = =在活化任何電解電鑛操作時可以需 的表並有經延伸之區域在内襯16部份 以圖2F言|，進行一平坦 /冓渠15包含隨後填滿？盥矣 叫系 16。 具涡至與表面12齊平之導體材料17之内襯 參考圖2G ’說明圖2F中之锋播γ ^ 而操作以擴散一帽蓋金屬，:u、之”，、循環處理， 表面形成-= 而含於内襯1"，而* (margins)對準。帽蓋 在在晨表许面12之内襯16邊界 足以有環境保護的效果，戋：上可為大約5-50埃’便 級上之電性或無電極電鍵==一埃之數量 或經由使用帽US : = M J來作為表面12之電線， 線1 9，以虛線示之，而暴露中間產物之下方達 —；一"; ---^---另有用途之，受擴散與電遷 第13頁 4BM0389TW-替換頁-012105.ptc 1234821 94. i. 2i _案號92130221_年月曰 修正_ 五、發明說明（7) 移保護與帽蓋之線或是内連線。 所敘述者為在有自行對準之帽蓋之介電物中，提供擴 散與電遷移保護之導性元件之技術，其中在介電物中之導 體，被對外向擴散有抗性並且當成可擴散至帽蓋區域之帽 盍材料源之一材料所包圍。
4IBM0389TW-替換頁-012105.ptc 第14頁 1234821 案號 92130221 94. 1. 21 年月曰 修正 圖式簡單說明 圖1例示本發明被帽蓋以保護擴散-電遷移之導體元件 之剖面圖。 圖2A-2G例示於形成本發明被帽蓋導體元件，以數步 處理步驟所部份製得之結構。 1、1 5溝渠 3表面 5襯底 7帽蓋 9 A、9 B表面 12表面 14區域 18帽蓋 2介電物 4導體元件 6銅導體 8外側表面 11層 1 3罩材料 1 6、1 7元件 19線
4IBM0389TW-替換頁-012105.ptc 第15頁

Claims (1)

1234821 94 l. 2i _案號 92130221_年月日_______ 六、申請專利範圍 1· 一種對電遷移（electromigration)與擴散敏感金屬 之積體電路導性元件（conductive element)，該金屬被 一保護性帽蓋所覆蓋並位於一介電物之一平面中之一溝渠 中，該導性元件金屬被位於該溝渠中一材料之一内襯所包 圍，該材料係對從該電遷移與擴散敏感金屬之外向擴散 (out diffusion)有抗性，並且對於該帽蓋作為一擴散 材料源。
2 ·如申請專利範圍第1項之積體電路導性元件，其中該介 電物為至少一種得自Si02群組，基於以SiCOH或SILK材料 群而為業界所知悉之介電物為基礎之一材料。 3 ·如申請專利範圍第2項之積體電路導性元件，其中該導 性元件金屬為銅。 4 ·如申請專利範圍第3項之積體電路導性元件，其中該户 概為包含至少一來自群組A與B之成份之一合金或二襯^ ^ 疊（liner stack) ’其中A選自鎢、钽、鈦，其氮化物君 與矽化物群，而B係選自铑、釕、鈀、鉑、銀、鈷與銥。 5二如申請專利範圍第4項之積體電路導性元件，其中該中 蓋為至少铑、鈀、釕、銥、銀、鉑與鈷之群組之一成員< 6· 一種製造一經帽蓋積體電路導線與内連線成員 C 形成在一介電物之 溝渠； 法，包含之步驟為 ^ 經
平垣化表面具有侧邊與底 渠内 將一内襯材料安置於延伸 ’該内襯材料具有抵抗原 於遠侧邊與底部上方之該溝 子穿過該内襯材料而擴散之
1234821 案號 92130221 如· 1· 21
六、申請專利範圍 一性質，該内襯材料谁_丰@ + t 原子源之一性質；冑步具有作為-帽蓋材料之-擴散 將該經内觀之溝渠填滿—導體金屬； 化表：坦Γ經填滿經内襯之溝渠直至該介電物之該平坦 將位於該介電物Ψ古 s 該、、、乂填滿經内襯之溝渠以一溫度循 %退火(anneal ing )，而？丨”站私σ々A 调 为早以艰A4工 而足以擴政足夠之該帽蓋材料之 7 Λ Λ 平坦化表面在料體材料上之一層。 .!°Γ:ί利範圍第6項的方法，其中該導體金屬為鋼。 8. 如申明專利粑圍第7項的方法，其中該介電物為至少— =自二群組’基於以以⑶…旧材料群而為業界所 知心之；丨電物為基礎之一材料。 9. 如申請專利範圍第8項的方法，其中該内襯為至少一來 自群組A與B之成份所組成之一合金或一襯裡堆疊 sjack )其中A選自鶴、組 '與鈦，其氣化物 群，而B係選自錢、釕、把、翻、銀、銘與錶。、夕化物 1〇·如申請專利範圍第9項的方法，其+來自 群之該擴散原子群在-後續—⑽層之沉積中作為4化 層0 11·種在賦予環境杬性與在一介電層式積體電路導性元 件中抵抗電遷移（electr〇migrati〇n)與擴散的方法， 其包含步驟為：在位於該介電物中之一溝渠中形成該導 體與内連線成員群之金屬部份，該介電物以一襯裡内襯， 其對於穿過該襯裡之原子擴散有抗性，且該襯裡作為一帽
4IBM0389TW-替換頁-0121〇5.ptc 第17頁 1234821 911.21 案號92130221 年月日 修正
4IBM0389TW-替換頁-012105.ptc 第18頁
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