CN1295786C - 多级半导体结构中对准带帽金属线和互连的形成 - Google Patents

多级半导体结构中对准带帽金属线和互连的形成 Download PDF

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CN1295786C
CN1295786C CNB031786219A CN03178621A CN1295786C CN 1295786 C CN1295786 C CN 1295786C CN B031786219 A CNB031786219 A CN B031786219A CN 03178621 A CN03178621 A CN 03178621A CN 1295786 C CN1295786 C CN 1295786C
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S·R·彻拉斯
M·W·莱恩
S·G·玛尔霍特拉
F·R·麦克菲利
R·罗森博格
C·J·萨姆巴塞迪
P·M·怀瑞根
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GlobalFoundries Inc
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Abstract

在集成电路技术中，提供了例如铜的金属的电迁移和扩散敏感导体及其加工程序，其中在平整化的化学机械加工的界面处，在可选择的低Keff介质材料的用一种材料围绕的区中定位该导体金属。选择所述一种材料以便防止外扩散并且作为膜形成厚度帽的源，该膜形成厚度帽将形成在导体金属上和/或起到催化层的作用，用于CoWP成帽层的化学选择淀积。

Description

多级半导体结构中对准带帽 金属线和互连的形成
技术领域
本发明涉及使用会表现出扩散和电迁移性能的金属例如铜(Cu)作为半导体集成电路中线和互连中的金属导体的领域，尤其是介质材料内的这种集成电路中该材料的导体的形成，并且具有自对准金属帽层。
背景技术
本领域很好地发展了互连技术，作为集成电路和半导体芯片结构中的通路、线和其它图形以及互连之用。在这些结构中，多级布线图形埋在介质材料中，由具有不同介电性能的介质材料分隔的布线图形和通路。
例如铜(Cu)的材料在本领域正引起人们的注意，因为它具有能够通过减小导体电阻改进性能的潜在能力。然而，由增加性能的愿望驱动而导致的越来越小的尺寸和不断增加电流的物理条件下，这种材料的扩散和电迁移性能难以解决污染和泄漏控制问题和可靠性问题。
通常以术语“衬垫”、“阻挡”或者“帽”相称的保护层正在被采用，试图限制外扩散和电迁移。然而，任何保护材料还必须对结构中其它各种介质材料具有好的粘结性。
在目前的技术状态，在一个方案中，通过下列方式解决上述问题，对于硅衬底上的铜导体线来说，使用二氧化硅作为互连介质材料，氮化硅材料作为帽材料。然而，目前依赖的氮化硅材料在具有理想的高电阻率性能的同时，还具有7至8的相当高的介电常数，因此增加了结构的有效介电常数(Keff)，也不利地影响了级内电容(intralevel capacitance)。
在另一个方案中，也涉及材料Cu的扩散和电迁移问题，所实现的理想结果包括进一步能够选择保持理想的低(Keff)的帽材料，该帽材料通过环绕的介电材料建立。该技术在Hu等人于7/27/99申请的申请序列号No.09/361,573中描述了，该申请转让给了本申请的受让人。在该技术中，在包括钴钨磷(CoWP)淀积的两步工序中生成自对准金属帽。所淀积的材料覆盖和保护顶部铜表面，同时实现了结构中理想的粘结，并且起到阻抗电迁移的作用。
当在本领域寻求更大的进步时，低介电常数(低K)金属间(intermetal)的介质材料表现出更有前途的性能。
在集成电路技术中需要更简单的加工方法，其中保护导体材料例如Cu免受电迁移和扩散的影响，并且能够定位在可选择的低Keff介电结构中。
发明内容
在集成电路技术中，提供了一种电迁移和扩散敏感金属例如铜的导体元件及其加工程序，其中在平整化的化学机械加工了的界面处，导电元件的金属定位在可选择的Keff介质材料中。该金属由具有抗原子扩散出所述金属的性能并且作为膜厚度帽的源的材料环绕，该膜厚度帽将形成在该金属上。该帽提供环境保护并且提供催化有效性，用于进一步加工。本发明的技术提供一种中间导电元件产品和制造方法，该产品能够用作许多半导体集成结构中的布线导体或者互连。该导电元件通过下列方式制造：在可选择的、优选(低K)介质中，在将被化学机械加工(CMP)的界面中形成容纳沟槽。用由一种材料或者多种材料的一层或者多层构成的区作沟槽的衬垫，所述一种材料或者多种材料能够控制所述金属外扩散到优选的(低K)介质材料中，并且还能够提供扩散剂源，当通过例如退火操作扩散剂源扩散到金属表面时，形成了金属上的自对准保护帽。用金属填充衬垫内侧的沟槽部分。在形成保护帽过程中，对带衬垫的沟槽结构中的金属进行退火温度循环。然后可以沿着CMP平整表面平整化导电元件的结构，以便除去平整表面上剩余的任何衬垫材料和任何过剩的金属材料。如果需要，可以从远离平整表面的一侧腐蚀掉介质部件，以便露出沟槽的底部，用于进一步的接触。
附图简述
图1是本发明的带帽扩散-电迁移保护的导电元件的截面图。
图2A至2G表明在本发明的带帽导电元件的形成中，在几个加工步骤的部分制造的结构。
本发明的描述
在目前的技术状态，在利用扩散和电迁移敏感金属例如铜作为布线导体和互连的集成电路的发展中，问题的主要根源来自金属外扩散到介质中从而在支撑介质界面处造成污染，以及金属与下一级的界面处的跟其它材料反应。
参考图1，图1示出了本发明的扩散-迁移保护导电元件的截面图。在图1中，介质2在平面化学机械加工(CMP)的平整表面3下延伸，在延伸到介质2中的沟槽1中，沿着沟槽1的侧面和底部在衬垫5内定位本发明的扩散-电迁移保护导电元件4。衬垫5中的铜制成的导体6具有与衬垫5的外侧侧表面8对准的帽7，并且能够加工成与(CMP)平整表面3齐平。在进一步的使用中，如果需要，可以进一步从下面CMP加工介质材料2，以便在示为点划线9A和9B的将被平整化的表面中露出导体6的底部，点划线9A所示的表面用于被露出导体，点划线9B所示的表面具有与帽7对应的帽。
参考图2A-2G，在本发明的使用金属铜(Cu)作为导体的扩散-迁移保护导体元件的形成中，在说明性的制造步骤中提供了结构的部分产品图。其中适当采用了与较早的图中所用的参考标号对应的参考标号。
参考图1和2，从图2A开始，介质材料2的层11已经淀积在例如氧化硅材料的衬底上，该层11的介质材料2例如选自通常由Si、C、O和H构成、具有如CORAL和Black DIAMOND等商标的SiO2、SILK、FSG、SiCOH和Si基低k介质，其深度例如达到大约1000-10000埃，该深度大约比将形成的导体6的设计高度在同一数量级或稍大。暴露表面12。至此在用于层11的介质材料2的性能选择上存在灵活性，使得可以选择低k介质。
参考图2B，用掩模材料13平版印刷覆盖露出的表面12，使得留下暴露的区域14，以便制造加工。掩模材料13应能够抵抗通过区域14对层11的任何想要的腐蚀操作，例如化学或者反应离子蚀刻。
参考图2C，图2C示出了层11中沟槽15的形成，该沟槽通过表面12利用例如化学或者反应离子蚀刻已经形成，深度大约为1000-10000埃，该深度比将形成的导体6的设计高度在同一数量级或稍大。
在图2D中，标为部件16的衬垫区可淀积在沟槽15中，采用的淀积技术例如有物理汽相淀积(PVD)即溅射等、化学汽相淀积(CVD)、原子层淀积(ALD)、化学或者电解淀积。衬垫区16将覆盖沟槽15的侧面和底部，并且最初允许覆盖表面12。部件16可以是结构中一个或者多个单独的层、合金或者相，并且可以形成为例如由钨(W)与钌(Ru)构成的双层。或者可选择的组合可以是TaN/Ta/Ru、TiW/Ru、TiN/Ru。衬垫区16中材料的扩散源性能产生了在结构中还能够起催化作用的金属帽。该性能给予成份是Ru，它能够由如Pd、Rh、Co、Pt、Ir和Ag元素代替。
衬垫区16的作用是提供对于包含在沟槽15中的导体金属的外扩散和电迁移抑制能力，并且衬垫区16的作用还包括作为扩散剂元素源，后来该扩散剂元素穿过所述将提供的导体金属扩散出衬垫区16，然后作为其上面的自对准帽。衬垫区16具有层的形式，可以选自下面的成份：
对于叠层衬垫A/B：A可以选自W、Ta或者Ti、它们的氮化物和硅化物及其组合，B可以选自Pd、Rh、Co、Pt、Ir、Ru和Ag，B层的厚度＜100A。对于合金衬垫A(B)来说，保持上面的成份关系，且合金中B的比例＜75％。对于大约0.1微米的衬垫宽度跨距来说，总的衬垫区16的厚度在大约30-300埃范围内。
参考图2E，描述了已经进行了填充操作，其中利用标为部件17的导体材料的淀积操作填充沟槽15内衬垫区16的开放部分。淀积操作可以是本领域的标准技术，例如电解镀或者化学镀。当选择的导体金属是铜时，在活化任何电镀操作中可以需要或者不需要籽晶。导体材料17的淀积操作填充了衬了衬垫区16的沟槽15的开口，可能有延伸区延伸到衬垫区16的部分表面上。
参见图2F，已进行平整化操作，其中利用如化学-机械抛光技术的技术，除去所有的材料，直到表面12，留下包含衬垫区16、继而用导体材料17填充的沟槽15，所有都与表面12齐平。
参考图2G，对图2F所示的结构进行退火热循环操作，以便使成帽材料扩散，例如已经包含在衬垫16区中的钌穿过填充沟槽15开口的导体材料17到达表面12，由此在表面形成帽18，帽18在表面12处与衬垫区16的边缘自对准。帽18的厚度可以大约为5-50埃，对于环境保护或者作为大约50-500埃厚量级的电镀或化学镀操作的催化剂来说，上述帽18的厚度足够了。
图2G所示的中间产物可以用作表面12处的电衬垫，或者通过使用帽18作为更多帽层的籽晶或者催化剂，或者进一步通过从下面腐蚀加工该中间产物例如CMP，腐蚀到所示的点划线19，从而露出扩散和电迁移保护和带帽的线或者互连，用于其它用途。
已经描述的技术是提供在介质中具有自对准帽的一种具有的扩散和电迁移保护的导电元件，介质中的导体由抗外扩散并且作为成帽材料源的材料围绕，该成帽材料能够扩散到帽位置。

Claims (13)

1.一种电迁移和扩散敏感金属的集成电路导电元件，所述电迁移和扩散敏感金属由保护帽覆盖，并且所述电迁移和扩散敏感金属定位在延伸至介质的平整表面的沟槽中，在所述沟槽中，由抗该电迁移和扩散敏感金属的外扩散的、并且作为所述帽材料的扩散源的材料构成的衬垫环绕所述电迁移和扩散敏感金属。
2.权利要求1的集成电路导电元件，其中所述介质是从各种SiO2基介质中选取的至少一种材料。
3.权利要求2的集成电路导电元件，其中所述介质是SiCOH或SILK材料。
4.权利要求2或3的集成电路导电元件，其中所述导电元件的金属是铜。
5.权利要求4的集成电路导电元件，其中所述衬垫是由来自组A和B的至少一种成分构成的衬垫叠层或一种合金，其中A选自W、Ta、Ti、它们的氮化物和硅化物；B选自Ru、Rh、Pd、Pt、Ag、Co和Ir。
6.权利要求5的集成电路导电元件，其中所述帽是Ru、Pd、Rh、Ir、Ag、Pt和Co中的至少一个元素。
7.带帽集成电路导体线和互连部件的制造方法，包括步骤：
形成延伸至介质的平整化表面的具有侧面和底部的沟槽，
在所述沟槽中定位衬垫材料，使其位于所述侧面和底部，
所述衬垫材料具有抗原子扩散通过所述衬垫材料的性能，
所述衬垫材料还具有作为成帽材料的扩散原子源的性能，
用导体金属填充所述带衬垫的沟槽，
平整化所述经填充的带有衬垫材料的沟槽，直到所述介质的所述平整化表面，和
在以下温度循环中对所述介质中所述填充了的带衬垫的沟槽进行退火，该温度循环使所述成帽材料的原子扩散，以便在所述平整化表面处在所述导体金属上形成层。
8.权利要求7的方法，其中所述导体金属是Cu。
9.权利要求8的方法，其中所述介质是从SiO2基介质中选取的至少一种材料。
10.权利要求9的方法，其中所述介质是SiCOH或SILK材料。
11.权利要求9或10的方法，其中所述衬垫是由来自组A和B的至少一个成分构成的衬垫叠层或合金，其中A选自W、Ta、Ti、它们的氮化物和硅化物；B选自Ru、Rh、Pd、Pt、Ag、Co和Ir。
12.权利要求11的方法，其中来自所述组B的元素的扩散原子在后续的CoWP层的淀积中起到催化层的作用。
13.在介质层型集成电路导电元件中提供抗环境和抗电迁移和扩散的方法，其改进在于在所述介质中的沟槽中形成导体和互连部件的金属部分，用衬垫给所述沟槽作衬，所述衬垫抵抗原子扩散通过所述衬垫，并且所述衬垫起到成帽材料的扩散原子源的作用，对所述金属和所述衬垫施加扩散退火热循环。
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Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030190426A1 (en) * 2002-04-03 2003-10-09 Deenesh Padhi Electroless deposition method
US6821909B2 (en) * 2002-10-30 2004-11-23 Applied Materials, Inc. Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application
US20070010573A1 (en) * 2003-06-23 2007-01-11 Xianqi Kong Methods and compositions for treating amyloid-related diseases
US7064065B2 (en) * 2003-10-15 2006-06-20 Applied Materials, Inc. Silver under-layers for electroless cobalt alloys
US20050095830A1 (en) * 2003-10-17 2005-05-05 Applied Materials, Inc. Selective self-initiating electroless capping of copper with cobalt-containing alloys
TW200530427A (en) * 2003-10-17 2005-09-16 Applied Materials Inc Selective self-initiating electroless capping of copper with cobalt-containing alloys
US7205233B2 (en) * 2003-11-07 2007-04-17 Applied Materials, Inc. Method for forming CoWRe alloys by electroless deposition
US20050170650A1 (en) * 2004-01-26 2005-08-04 Hongbin Fang Electroless palladium nitrate activation prior to cobalt-alloy deposition
US20050181226A1 (en) * 2004-01-26 2005-08-18 Applied Materials, Inc. Method and apparatus for selectively changing thin film composition during electroless deposition in a single chamber
US20050161338A1 (en) * 2004-01-26 2005-07-28 Applied Materials, Inc. Electroless cobalt alloy deposition process
US20050253268A1 (en) * 2004-04-22 2005-11-17 Shao-Ta Hsu Method and structure for improving adhesion between intermetal dielectric layer and cap layer
US20060240187A1 (en) * 2005-01-27 2006-10-26 Applied Materials, Inc. Deposition of an intermediate catalytic layer on a barrier layer for copper metallization
US20070271751A1 (en) * 2005-01-27 2007-11-29 Weidman Timothy W Method of forming a reliable electrochemical capacitor
US7438949B2 (en) * 2005-01-27 2008-10-21 Applied Materials, Inc. Ruthenium containing layer deposition method
US7651934B2 (en) 2005-03-18 2010-01-26 Applied Materials, Inc. Process for electroless copper deposition
TW200707640A (en) * 2005-03-18 2007-02-16 Applied Materials Inc Contact metallization scheme using a barrier layer over a silicide layer
US20060246699A1 (en) * 2005-03-18 2006-11-02 Weidman Timothy W Process for electroless copper deposition on a ruthenium seed
WO2006102318A2 (en) * 2005-03-18 2006-09-28 Applied Materials, Inc. Electroless deposition process on a contact containing silicon or silicide
US7317253B2 (en) 2005-04-25 2008-01-08 Sony Corporation Cobalt tungsten phosphate used to fill voids arising in a copper metallization process
US20070190362A1 (en) * 2005-09-08 2007-08-16 Weidman Timothy W Patterned electroless metallization processes for large area electronics
WO2007035880A2 (en) * 2005-09-21 2007-03-29 Applied Materials, Inc. Method and apparatus for forming device features in an integrated electroless deposition system
US20070080455A1 (en) * 2005-10-11 2007-04-12 International Business Machines Corporation Semiconductors and methods of making
CN1983550A (zh) * 2005-12-14 2007-06-20 中芯国际集成电路制造(上海)有限公司 提高可靠性和成品率的消除铜位错的方法
US7863183B2 (en) 2006-01-18 2011-01-04 International Business Machines Corporation Method for fabricating last level copper-to-C4 connection with interfacial cap structure
WO2007091574A1 (ja) * 2006-02-06 2007-08-16 Nec Corporation 多層配線構造および多層配線の製造方法
CN101432908B (zh) * 2006-04-14 2011-08-17 应用材料股份有限公司 可靠的燃料电池电极设计
US8193087B2 (en) * 2006-05-18 2012-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Process for improving copper line cap formation
JP2009026989A (ja) * 2007-07-20 2009-02-05 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2011503910A (ja) * 2007-11-19 2011-01-27 アプライド マテリアルズ インコーポレイテッド パターン付きエッチング剤を用いた太陽電池コンタクト形成プロセス
WO2010009297A2 (en) * 2008-07-16 2010-01-21 Applied Materials, Inc. Hybrid heterojunction solar cell fabrication using a doping layer mask
KR20100077535A (ko) * 2008-12-29 2010-07-08 주식회사 하이닉스반도체 콘택 구조체, 그것의 제조방법, 그것을 구비한 상변화 메모리 장치 및 그 제조방법
US9209073B2 (en) * 2013-03-12 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Metal cap apparatus and method
US9142456B2 (en) * 2013-07-30 2015-09-22 Lam Research Corporation Method for capping copper interconnect lines

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457069A (en) * 1994-08-31 1995-10-10 National Science Council Process for fabricating device having titanium-tungsten barrier layer and silicide layer contacted shallow junction simultaneously formed
US5668040A (en) * 1995-03-20 1997-09-16 Lg Semicon Co., Ltd. Method for forming a semiconductor device electrode which also serves as a diffusion barrier
US5693563A (en) * 1996-07-15 1997-12-02 Chartered Semiconductor Manufacturing Pte Ltd. Etch stop for copper damascene process
US5968333A (en) * 1998-04-07 1999-10-19 Advanced Micro Devices, Inc. Method of electroplating a copper or copper alloy interconnect
US6342733B1 (en) * 1999-07-27 2002-01-29 International Business Machines Corporation Reduced electromigration and stressed induced migration of Cu wires by surface coating

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0138305B1 (ko) * 1994-11-30 1998-06-01 김광호 반도체소자 배선형성방법
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
JP3304754B2 (ja) * 1996-04-11 2002-07-22 三菱電機株式会社 集積回路の多段埋め込み配線構造
JP3285509B2 (ja) * 1997-03-18 2002-05-27 三菱電機株式会社 半導体装置
KR100404649B1 (ko) * 1998-02-23 2003-11-10 가부시끼가이샤 히다치 세이사꾸쇼 반도체장치 및 그 제조방법
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6265779B1 (en) * 1998-08-11 2001-07-24 International Business Machines Corporation Method and material for integration of fuorine-containing low-k dielectrics
US6214728B1 (en) * 1998-11-20 2001-04-10 Chartered Semiconductor Manufacturing, Ltd. Method to encapsulate copper plug for interconnect metallization
JP4221100B2 (ja) * 1999-01-13 2009-02-12 エルピーダメモリ株式会社 半導体装置
US6849923B2 (en) * 1999-03-12 2005-02-01 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of the same
US6395607B1 (en) * 1999-06-09 2002-05-28 Alliedsignal Inc. Integrated circuit fabrication method for self-aligned copper diffusion barrier
AU6531600A (en) * 1999-08-27 2001-03-26 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
US6184138B1 (en) * 1999-09-07 2001-02-06 Chartered Semiconductor Manufacturing Ltd. Method to create a controllable and reproducible dual copper damascene structure
US6251786B1 (en) * 1999-09-07 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to create a copper dual damascene structure with less dishing and erosion
US6153935A (en) * 1999-09-30 2000-11-28 International Business Machines Corporation Dual etch stop/diffusion barrier for damascene interconnects
US6815329B2 (en) * 2000-02-08 2004-11-09 International Business Machines Corporation Multilayer interconnect structure containing air gaps and method for making
JP3979791B2 (ja) * 2000-03-08 2007-09-19 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP3669681B2 (ja) * 2000-03-31 2005-07-13 株式会社東芝 半導体装置の製造方法
US7061111B2 (en) * 2000-04-11 2006-06-13 Micron Technology, Inc. Interconnect structure for use in an integrated circuit
JP4659329B2 (ja) * 2000-06-26 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US6395632B1 (en) * 2000-08-31 2002-05-28 Micron Technology, Inc. Etch stop in damascene interconnect structure and method of making
US6406996B1 (en) * 2000-09-30 2002-06-18 Advanced Micro Devices, Inc. Sub-cap and method of manufacture therefor in integrated circuit capping layers
DE10056871B4 (de) * 2000-11-16 2007-07-12 Advanced Micro Devices, Inc., Sunnyvale Feldeffekttransistor mit verbessertem Gatekontakt und Verfahren zur Herstellung desselben
US20020132471A1 (en) * 2001-03-16 2002-09-19 International Business Machines Corporation High modulus film structure for enhanced electromigration resistance
TW543093B (en) * 2001-04-12 2003-07-21 Cabot Microelectronics Corp Method of reducing in-trench smearing during polishing
US6723600B2 (en) * 2001-04-18 2004-04-20 International Business Machines Corporation Method for making a metal-insulator-metal capacitor using plate-through mask techniques
US6521523B2 (en) * 2001-06-15 2003-02-18 Silicon Integrated Systems Corp. Method for forming selective protection layers on copper interconnects
US6943451B2 (en) * 2001-07-02 2005-09-13 International Business Machines Corporation Semiconductor devices containing a discontinuous cap layer and methods for forming same
US6727177B1 (en) * 2001-10-18 2004-04-27 Lsi Logic Corporation Multi-step process for forming a barrier film for use in copper layer formation
JP2003142579A (ja) * 2001-11-07 2003-05-16 Hitachi Ltd 半導体装置の製造方法および半導体装置
US6645853B1 (en) * 2001-12-05 2003-11-11 Advanced Micro Devices, Inc. Interconnects with improved barrier layer adhesion
US20030116439A1 (en) * 2001-12-21 2003-06-26 International Business Machines Corporation Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices
US6734096B2 (en) * 2002-01-17 2004-05-11 International Business Machines Corporation Fine-pitch device lithography using a sacrificial hardmask
US6743310B1 (en) * 2002-02-22 2004-06-01 Advanced Micro Devices, Inc. Method of forming nitride capped Cu lines with improved adhesion and reduced electromigration along the Cu/nitride interface
US6764951B1 (en) * 2002-02-28 2004-07-20 Advanced Micro Devices, Inc. Method for forming nitride capped Cu lines with reduced hillock formation
US6797652B1 (en) * 2002-03-15 2004-09-28 Advanced Micro Devices, Inc. Copper damascene with low-k capping layer and improved electromigration reliability
US6723635B1 (en) * 2002-04-04 2004-04-20 Advanced Micro Devices, Inc. Protection low-k ILD during damascene processing with thin liner
US6528409B1 (en) * 2002-04-29 2003-03-04 Advanced Micro Devices, Inc. Interconnect structure formed in porous dielectric material with minimized degradation and electromigration
US6831003B1 (en) * 2002-05-31 2004-12-14 Advanced Micro Devices, Inc. Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration
US6753250B1 (en) * 2002-06-12 2004-06-22 Novellus Systems, Inc. Method of fabricating low dielectric constant dielectric films
US6790773B1 (en) * 2002-08-28 2004-09-14 Novellus Systems, Inc. Process for forming barrier/seed structures for integrated circuits
US7279423B2 (en) * 2002-10-31 2007-10-09 Intel Corporation Forming a copper diffusion barrier
US6975032B2 (en) * 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457069A (en) * 1994-08-31 1995-10-10 National Science Council Process for fabricating device having titanium-tungsten barrier layer and silicide layer contacted shallow junction simultaneously formed
US5668040A (en) * 1995-03-20 1997-09-16 Lg Semicon Co., Ltd. Method for forming a semiconductor device electrode which also serves as a diffusion barrier
US5693563A (en) * 1996-07-15 1997-12-02 Chartered Semiconductor Manufacturing Pte Ltd. Etch stop for copper damascene process
US5968333A (en) * 1998-04-07 1999-10-19 Advanced Micro Devices, Inc. Method of electroplating a copper or copper alloy interconnect
US6342733B1 (en) * 1999-07-27 2002-01-29 International Business Machines Corporation Reduced electromigration and stressed induced migration of Cu wires by surface coating

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