TWI231983B - Multi-chips stacked package - Google Patents

Multi-chips stacked package Download PDF

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Publication number
TWI231983B
TWI231983B TW092109655A TW92109655A TWI231983B TW I231983 B TWI231983 B TW I231983B TW 092109655 A TW092109655 A TW 092109655A TW 92109655 A TW92109655 A TW 92109655A TW I231983 B TWI231983 B TW I231983B
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TW
Taiwan
Prior art keywords
chip
wafer
stacked package
carrier board
patent application
Prior art date
Application number
TW092109655A
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English (en)
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TW200423355A (en
Inventor
Meng-Jen Wang
Original Assignee
Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092109655A priority Critical patent/TWI231983B/zh
Priority to US10/820,826 priority patent/US6856027B2/en
Publication of TW200423355A publication Critical patent/TW200423355A/zh
Application granted granted Critical
Publication of TWI231983B publication Critical patent/TWI231983B/zh

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

1231983 五、發明說明（1) '— -------- (一） 、【，明所屬之技術領域】 本f明是有關於一種多晶片堆疊封裝體，特別是有關 種晶片能同時與其他晶片及載板直接電性連接之多晶 疊封裝體’以增加晶片的輸入/輸出訊號密度及提升晶 片中之線路佈局設計自由度之多晶片堆疊封裝體。 (二） 、【先前技術】 隨著微小化以及高運作速度需求的增加，多晶片堆疊 封f體在許多電子裝置越來越吸引人。多晶片堆疊封裝體 I藉由將兩個或兩個以上之晶片組合在單一封裝體中，來 提升系統之運作速度。此外，多晶片堆疊封裝體可減少晶 片間連接線路之長度而降低訊號延遲以及存取時間。 最常見的多晶片堆疊封裝體為並排式（side-by-side) 多晶片堆叠封裝體，其係將兩個以上之晶片彼此並排地安 裝於一共同載板之主要安裝面。晶片與共同載板上導電線 路間之連接一般係藉由打線法（wire b〇nding)達成。然而 該並排式多晶片堆疊封裝體之缺點為封裝效率太低，因為 該共同載板之面積會隨著晶片數目的增加而增加。 因此半導體業界開發出一多晶片堆疊封裝體之設計 (參照圖1 )，其特徵在於提供一第一晶片丨丨〇覆晶接合於 一具有一開口 122之載板120上表面124，再將一第二晶片 130容置於載板120之開口122中，並與上述之第一晶片11〇 覆晶接合。一般而言，第一晶片i〇與第二晶片！ 3 〇可分別 為記憶晶片及邏輯晶片，如此可將第一晶片J i 〇與第二晶片
1231983
130之訊號於封裝體内先行整合後，再經由載板i2〇下表面 6之銲球128與外界電性連接。如此之封裝體設計不僅能 減少封裝體之厚度，更可提升晶片之運算及傳輸效能。然 7由於帛B曰片與第二晶片覆晶接合前，需先於第一晶 及第一晶片上设計覆晶銲墊及其上之球底金屬層，故增 加製程之複雜度且增加其製造成本。此外，第二晶片之訊 號只能經由第-晶片再傳導至載板上，故進行第—晶片上 =路佈局t設計常需肖第二晶片t線路佈局進行整合考 里，故降低第一晶片線路佈局之設計自由度。 有鑑於此，為避旁前沭炙θ μ仏身 ^ ~项兄月,j逃多晶片堆疊封裝體之缺點，以 提升多晶片堆疊封裝體中之晶片效能，實為一重要的課 發明内容】 有鑑於上述課題，本發 疊封裝體，用以提升晶片中 製程並降低製造成本。 緣是，為了達成上述目 堆疊封裝體’主要包含一載 片、複數個導電線與複數個 個導電凸塊覆晶接合於載板 於載板之開口中，且藉複數 合。再者’第二晶片更可藉 接合。如此，第二晶片之訊 明之目的係提供一種多晶片堆 線路佈局之設計自由度及簡化 的’本發明係提供一種多晶片 板、一第一晶片、一第二晶 導電凸塊。第一晶片係藉複數 之上表面，而第二晶片係容置 個導電線與與第一晶片打線接 複數個導電線直接與載板打線 唬不僅能經由第一晶片傳導至
第6頁 1231983 五、發明說明（3) 載板上，更可直接與載板電性導通，故進行第一晶片上線 路佈局之設計可有較高之設計自由度。 一 綜上所述’本發明之多晶片堆疊封裝體主要係利用第 二晶片能藉由複數條導電線與第一晶片及載板同時電性導 通’如此在進行第一晶片上線路佈局之設計可有較高之設 =自胃由度外，再者不需另於第一晶片及第二晶片上設計覆 晶銲墊及在其上設置球底金屬層，故可簡化製程並降低製 造成本。 (四）、【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之多 晶片堆疊封裝體。 圖2係顯示本發明第一較佳實施例之多晶片堆疊封裝 體。本發明之多晶片堆疊封裝體至少包含一第一晶片21〇、 載板2 20、一第二晶片2 3 0、複數條晶片導電線24〇與複數個 導電凸塊2 5 0。其中，第一晶片21 〇係藉複數個導電凸塊25〇 覆晶接合於載板220之上表面224，而第二晶片23〇係容置於 載板220之開口222中，並可藉由一黏著層（導熱膠）26〇設置 於第一晶片210之主動表面212上，且利用複數條晶片導電 線240與第一晶片210打線接合。再者，可於載板22〇之開口 222中填充一底膠270用以至少包覆複數個導電凸塊25〇及第 一曰曰片2 3 0與複數條晶片導電線2 4 〇，如此不僅可避免連接 載板220與第一晶片210間之導電凸塊250，因載板220與第 一晶片2 1 0之熱膨脹係數之差異而破壞。此外，更可用以保
第7頁 1231983
蔓曰曰片導電線240及第二晶片230。另外，亦可將底膠270填 充包覆載板22G與第-晶片21G間之導電凸塊250，而第二晶 1 230及晶片導電線24〇則可包覆其他封膠體以保護之，如 衣氧膠由於第二晶片230係藉晶片導電線240與第一晶片 2>1 0電/生連接，故不需另於第一晶片21〇及第二晶片“ο上設 a十，晶銲墊及在其上設置球底金屬層，故可簡化製程並降 低製造成本。此外，該載板220之下表面226可設置有複數 個銲球228，用以與外界電性導通。 值得注意的是，當填充底膠27〇包覆導電凸塊25〇、第 二晶片2 3 0與複數條導電線24〇時，若填充過量之底膠27〇， 易仏成載板下表面226之污染，而影響銲球228設置於載板 下表面22 6之可靠度。故可於載板開口 222之週邊設置一攔 壩28 0 (djm)，如一環形膠體，以避免上述之問題。 接著巧參考圖3，其係顯示本發明第二較佳實施例之 夕曰曰片堆疊封裝體。與上述不同的是，第二晶片23〇更可藉 一載板導電線2 9 0與載板220電性連接。如此，第二晶片23〇 之訊號不僅能經由第_日日日片21()傳導至載板22()上，更可直 接與載板m電性導通，故進行第―晶片川上線路佈局之 設計可有較高之設計自由度。 於本實施例之詳細說明中 了易於說明本發明之技術内容 制於該實施例，因此，在不超 專利範圍之情況，可作種種變 所提出之具體的實施例僅為 ’而並非將本發明狹義地限 出本發明之精神及以下申請 化實施。
1231983 圖式簡單說明 (五）、【圖式簡單說明】 圖1為一示意圖，顯示習知一種多晶片堆疊封裝體的剖 面示意圖。 圖2為一示意圖，顯示本發明第一較佳實施例之多晶片 堆疊封裝體之剖面示意圖。 圖3為一示意圖，顯示本發明第二較佳實施例之多晶片 堆疊封裝體之剖面示意圖。 元件符號說明：
11 0 、2 1 0 第一晶片 212 第一晶片主動表面 120 > 2 2 0 載板 1 2 2、2 2 2 開口 124、224 載板上表面 1 2 6、2 2 6 載板下表面 1 2 8、2 2 8 銲球 1 3 0 、2 3 0 第二晶片 24 0 晶片導電線
2 5 0 導電凸塊 2 6 0 黏著層（導熱膠） 2 7 0 底膠 2 8 0 攔壩 2 9 0 載板導電線
第9頁

Claims (1)

1231983 六、申請專利範圍 1. 一種多晶片堆疊封裝體，包含： 一載板，具有一上表面、一下表面及一開口； 一第一晶片，具有一主動表面，其中該第一晶片係藉複數 個導電凸塊與該載板之該上表面覆晶接合，且該第一晶 片係覆蓋該開口；以及 一第二晶片，該第二晶片係設置於該第一晶片之該主動表 面上，且藉複數條晶片導電線與該第一晶片電性連接。 2 ·如申請專利範圍第1項所述之多晶片堆疊封裝體，其中更 包含一載板導電線，該第二晶片係藉該載板導電線與該載 板電性連接。 3. 如申請專利範圍第1項所述之多晶片堆疊封裝體，其中該 載板下表面更包含一攔壩，該攔壩係設置於該開口之週 邊。 4. 如申請專利範圍第3項所述之多晶片堆疊封裝體，其中該 攔壩係為一環狀。 5. 如申請專利範圍第3項所述之多晶片堆疊封裝體，其中該 攔壩係為一膠體。 6. 如申請專利範圍第1項所述之多晶片堆疊封裝體，其中更 包含一底膠，該底膠係至少包覆該等導電凸塊。
第10頁 1231983 六、申請專利範圍 7 ·如申請專利範圍第1項所述之多晶片堆疊封裝體，其中更 包含一底膠，該底膠係至少包覆該等導電凸塊、該等晶片 導電線、該第二晶片。 8 ·如申請專利範圍第1項所述之多晶片堆疊封裝體，其中更 形成一黏著層於該第一晶片主動表面與該第二晶片之該背 面間。
第11頁
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