TWI230415B - Electrode for dry etching a semiconductor wafer - Google Patents
Electrode for dry etching a semiconductor wafer Download PDFInfo
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- TWI230415B TWI230415B TW092104346A TW92104346A TWI230415B TW I230415 B TWI230415 B TW I230415B TW 092104346 A TW092104346 A TW 092104346A TW 92104346 A TW92104346 A TW 92104346A TW I230415 B TWI230415 B TW I230415B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000001312 dry etching Methods 0.000 title claims abstract description 17
- 239000011810 insulating material Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 69
- 238000000034 method Methods 0.000 description 14
- 239000000126 substance Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 239000012495 reaction gas Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000002981 blocking agent Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000035508 accumulation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005672 electromagnetic field Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 239000003504 photosensitizing agent Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- GWFXMCXJFOEMNQ-UHFFFAOYSA-N [O].O=[N] Chemical compound [O].O=[N] GWFXMCXJFOEMNQ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 230000035922 thirst Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32541—Shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
12304151230415
【先前技術】 第5圖所示為熟悉此行 作高度集積之半導體晶片時、術之人員共知者，即：製 形成如聚…層、氮化：層=周二會 110、120。而b , ^ Λ 汉金屬層等之右干>儿積>1[Prior art] Fig. 5 shows those who are familiar with this field when working on highly integrated semiconductor wafers, that is, the formation of layers such as poly ..., nitride: layer = Tuesday, 110, 120. And b, ^ Λ Han right layer > Er product > 1
2〇〇運送）n 1 圖所不，傳送（或利用機具設備 二因二ί!晶圓10°的過程中，由於晶圓周緣之沉 而產生小顆粒進入晶片中央區域，導 致積體龟路晶片受到污損。 其人因為近來半導體晶片的閘電極材料已經從矽化 鎢改成鎢.，並且電容器的絕緣層也從原先的氧—氮—氧 (ΟΝΟ，oxide-nitride-oxide)結構改變為氧化鈕，加以又 採用一種有機基底之抗反射塗層（anti—reflective coating，以下簡稱ARC)，一種如si〇N之無機ARC層以形成(2) Conveying) n 1 As shown in the figure, during the process of conveying (or using the equipment and equipment) the wafer at 10 °, small particles generated by the sinking of the wafer periphery enter the central area of the wafer, which leads to the accumulation of turtles. The wafer was contaminated. Because the gate electrode material of semiconductor wafers has recently been changed from tungsten silicide to tungsten, and the insulating layer of the capacitor has also changed from the original oxygen-nitrogen-oxide (ONO, oxide-nitride-oxide) structure to An oxidation button, and an organic-based anti-reflective coating (ARC for short), and an inorganic ARC layer such as SiON to form
纖細的光阻圖案，以及做為一種障礙金屬層之鈦及氮化鈦 層，因此’依前法製作時這些物質也會沾污半導體晶圓。 思即’製作半導體晶圓1 〇 〇時，上述物質係扮演了一 個污損晶圓的粒子源，特別是當晶圓直徑從2 〇 〇 mm擴大為 3 0 0 mm時，由於晶圓周緣的半徑也變大，所以半導體晶圓 被粒子沾污的情況也更加嚴重。The thin photoresist pattern, and the titanium and titanium nitride layers as a barrier metal layer, so these substances will also contaminate the semiconductor wafer when made according to the previous method. The idea is that when making semiconductor wafers, the above substances acted as a source of particles that fouled the wafers, especially when the wafer diameter expanded from 2000 mm to 300 mm. The radius also becomes larger, so the contamination of semiconductor wafers by particles is also more serious.
第6頁 1230415 五、發明說明（2) 因鑒於這些蓄積在半導體晶圓1〇〇周緣的物質會 半導體晶片的產能與品質，所以有必要加以徹底清除。- 前此已有若干供以清除上述蓄積物質的傳統方法 應用。以下係以一種如第以至以圖所示包括五個步騍 消除氮化物層之濕式餘刻法為例說明之： i.利用一電漿沉積裝置在矽半導體晶圓1〇〇上之氮 物層101表面形成一層氧化物層102(第73圖）； 11.塗佈感光劑於該氧化物層1 〇 2以形成一阻光層 103，移除該阻^光層1〇3位於矽半導體晶圓1〇〇之周緣^分 以便使該處的氧化物層1 〇 2曝露於外（第7b圖）； · i i i ·利用化學溶液（NHF4+HF)以一濕式蝕刻裝置移除 曝光的氧化物層102部分（第7C圖）； iv·先以一乾式蝕刻裝置移除覆蓋在該氧化物層1〇2 上面的阻光層103，次以化學溶液（1^〇4/112〇2)利用一清洗 裝置清洗殘餘的阻光劑1〇3(第7d圖）；及 V·利用一濕式蝕刻裝置以熱濃磷酸（h3p〇4)移除位於 該半導體晶圓1〇〇周緣曝露於外之該氮化物層1〇1(第7e 圖）。 以上所述氮化物層的濕式蝕刻程序至為繁複，需要各 種不同的設備來執行多項步驟，包括：氧化物層的沉積、· 阻光劑的塗佈、移除該阻光劑的乾式蝕刻、移除該氧化物 層的濕式蚀刻、殘餘阻光劑的徹底移除、清洗步驟、以及 該氮化物層的濕式姓刻動作。 另一方面，以下再以一種如第“至以圖所示也包括五Page 6 1230415 V. Explanation of the invention (2) In view of the fact that these substances accumulated on the periphery of the semiconductor wafer 100 will have the capacity and quality of the semiconductor wafer, it is necessary to completely remove them. -Several traditional methods have previously been used to remove these accumulations. The following is a description of a wet etching method including a five-step elimination nitride layer as shown in the first to the following figures: i. Nitrogen on a silicon semiconductor wafer 100 using a plasma deposition device An oxide layer 102 is formed on the surface of the object layer 101 (FIG. 73); 11. A photosensitizer is coated on the oxide layer 102 to form a light blocking layer 103, and the light blocking layer 103 is removed from the silicon The semiconductor wafer is 100mm apart to expose the oxide layer 100 there (Figure 7b); iii. Use a chemical solution (NHF4 + HF) to remove the exposure with a wet etching device Part of the oxide layer 102 (Fig. 7C); iv. First remove the light blocking layer 103 over the oxide layer 102 with a dry etching device, and then use a chemical solution (1 ^ 〇4 / 112〇). 2) The residual photoresist 103 (FIG. 7d) is cleaned by a cleaning device; and V. A wet etching device is used to remove thermally concentrated phosphoric acid (h3p04) at the periphery of the semiconductor wafer 100. The nitride layer 101 is exposed to the outside (FIG. 7e). The wet etching process of the nitride layer described above is complicated, and requires various equipment to perform a number of steps, including: deposition of an oxide layer, coating of a light blocking agent, and dry etching to remove the light blocking agent. , Wet etching to remove the oxide layer, complete removal of residual light blocking agent, a cleaning step, and wet etching of the nitride layer. On the other hand, the following uses a
第7頁 1230415 五、發明說明（3) 個步驟用以消除聚碎化物層之乾式姓刻法為例說明之·· i ·利用一電漿沉積裝置在矽半導體晶圓丨〇〇上之聚石夕 化物層104表面形成該氧化物層1〇2(第8a圖）； i i ·塗佈感光劑於該氧化物層1 〇 2以形成一阻光層 1 0 3，移除該阻光層1 0 3位於矽半導體晶圓丨〇 〇之周緣部分 以便使該處的氧化物層1 0 2曝露於外（第μ圖）； 1 i i.利用化學溶液（NHFdHF)以一濕式蝕刻裝置移除 曝光的氧化物層102部分（第8c圖）； iv.先以一乾式蝕刻裝置移除覆蓋在該氧化物層1〇2 上面的阻光層103，次以化學溶液（Η2%4/%%)利用一清洗 裝置清洗殘餘的阻光劑1〇3 (第8d圖）；及 用緣：Ϊ:=乾式蝕刻裝置移除位在該半導體晶圓1。。 周、、彖且曝路於外之該聚矽化物層1〇4(第8e圖）。 =種聚矽化物層之乾式蝕刻作業，其程序之繁 亞於刖述氮化物層之濕式蝕刻手續，^从 備來執行多頊牛驟，勺缸·」 也而要各種不同的設 . :員步驟包括·氧化物層的沉積、阻氺劍沾涂 刻、^::阻光劑的乾式蝕刻、移除該氧化物層的渴式蝕 2 Γ以及該聚石夕化物層的乾式餘刻動： m m ^ 在利用傳統的乾式银刻裝置進行移除车道Μ曰 囫周緣的聚矽化物層時，卻 =订移除+導體晶 的聚石夕化物層能夠完全“體晶圓周緣上表面 移除或頂多僅能做到除底面或侧面的部分無法充分 再者’應用於程序中以抑#圍电Μ 、· 之不同傳統蝕列f置 ν成圖案於該半導體晶圓表面 刻裝置因只能分別使用於單一步驟，亦即，Page 7 1230415 V. Description of the invention (3) The dry type engraving method used to eliminate the polymer debris layer is taken as an example ... i. Using a plasma deposition device to gather silicon silicon wafers The oxide layer 102 is formed on the surface of the stone oxide layer 104 (FIG. 8a); ii. A photosensitizer is coated on the oxide layer 102 to form a light blocking layer 103, and the light blocking layer is removed. 103 is located at the peripheral portion of the silicon semiconductor wafer, so that the oxide layer there is exposed to the outside (Fig. Μ); 1 i i. Using a chemical solution (NHFdHF) in a wet etching device Remove the exposed portion of the oxide layer 102 (Figure 8c); iv. First remove the light-blocking layer 103 over the oxide layer 102 with a dry etching device, and then use a chemical solution (Η2% 4 / %%) using a cleaning device to clean the remaining photoresist 103 (FIG. 8d); and using the edge: Ϊ: = dry etching device to remove the semiconductor wafer 1. . The polysilicide layer 104 is exposed to the outside, the outside, and the outside (FIG. 8e). = A kind of dry etching operation of polysilicide layer. The procedure is more complicated than the wet etching procedure of the nitride layer. ^ From the preparation to perform multiple yak steps, spoon cylinder. "It also requires various settings. The steps include: the deposition of an oxide layer, the scoring of the squeegee, the dry etching of the light-blocking agent, the thirst etching to remove the oxide layer, and the dry residue of the polylithium oxide layer. Engraving: mm ^ When using a traditional dry silver engraving device to remove the polysilicide layer on the periphery of the driveway, the polysilicon layer on the + conductor crystal can be completely removed from the periphery of the bulk wafer. The removal of the surface or at most can only remove the bottom or side parts. It can not be used enough in the program. In order to suppress the different traditional etching lines, a pattern is formed on the surface of the semiconductor wafer. Devices can only be used in a single step separately, that is,
第8頁 1230415 五、發明說明（4) 母種#刻裝置僅能移除某一特定異物，所以其中任一種 餘刻裝置皆無法滿足各種物質的需要。Page 8 1230415 V. Description of the invention (4) The mother seed # carving device can only remove a specific foreign object, so any of the remaining carving devices cannot meet the needs of various substances.
如第9圖所示，一用以形成細微電路圖案於半導體晶 片上之傳統乾式蝕刻裝置係在某一反應氣體中一扁平狀第 一電極300與另一扁平狀第二電極3〇〇’之間形成一電場， 且該乾式姓刻裝置產生電漿（等離子體）進入該半導體晶圓 100之上表面以便在該半導體晶圓100之上表面1〇〇3進行蝕 刻而形成一沉積層及一細微圖案103a。圖中，位於該半導 體晶圓1 0 0周緣的沉積層已被移除，而標號4 〇 〇表示一無線 電信號（R F )發生器，標號5 〇 〇則代表一互相匹配的電路。 該傳統乾式蝕刻裝置中，因為該半導體晶圓1 〇 〇係架 设於電極3 0 〇，之上進行蝕刻，該半導體晶圓1 〇 〇的側面 1 〇 〇 b與底面1 〇 〇 c均未被蝕刻到，所以，該半導體晶圓丨〇 〇 的側面1 0 0 b與底面1 〇 〇 c皆無法移除。 【發明内容】 鑒於上述缺點，本發明之.目標在於提供一種利 以乾式蝕刻半導體晶圓之電極，1 # 用電漿 一 n首诚θ η /、係可有效地移除沉籍协 一丰導體曰曰圓之周緣下表面、側表面、盥上 之，於 不致對該半導體晶圓造成任何傷宝者。一 之異物且 只要採用本發明之電極以乾^刻 達成上述或其他進一步的目標，實 圓方式要 Λ無太大困難。兮φ & -成對出現之電極，组’包括有利用電漿以移除半以為 之周緣異物之第一與第二電極。$第一電極_第曰曰圓 乐一扁As shown in FIG. 9, a conventional dry etching device for forming a fine circuit pattern on a semiconductor wafer is a flat first electrode 300 and another flat second electrode 300 ′ in a certain reaction gas. An electric field is formed in between, and the dry type engraving device generates plasma (plasma) to enter the upper surface of the semiconductor wafer 100 so as to etch the upper surface of the semiconductor wafer 100 to form a deposition layer and a Fine pattern 103a. In the figure, the deposited layer at the periphery of the semiconductor wafer 100 has been removed, and reference numeral 400 indicates a radio frequency signal (RF) generator, and reference numeral 500 indicates a matching circuit. In the conventional dry etching device, since the semiconductor wafer 1000 is mounted on the electrode 300 and is etched, neither the side surface 100b nor the bottom surface 100c of the semiconductor wafer 100 is not etched. It is etched so that neither the side 100b nor the bottom 100c of the semiconductor wafer can be removed. [Summary of the invention] In view of the above disadvantages, the purpose of the present invention is to provide an electrode that facilitates dry etching of semiconductor wafers. 1 # Plasma with n first sincerity θ η /, can effectively remove Shen Jixie Yifeng The lower surface, side surface, and upper surface of the circumference of the conductor do not cause any damage to the semiconductor wafer. As long as the above-mentioned or other further objectives are achieved by dry etching using the electrode of the present invention, the solid circle method is not too difficult. Φ &-The electrodes appearing in pairs, and the group 'includes first and second electrodes that use a plasma to remove half-thinking peripheral foreign matter. $ 第一 electrode_ 第 Yuan Yue Yuan Le Yibian
第9頁 1230415 五、發明說明（5) 平部與一大小相當於一半導體晶圓周緣一面之環狀凸緣， 而該第二電極則内含一第二扁平部與一大小相當於該半導 體晶圓周緣另一面之環狀凸緣，其中該第一與第二凸緣大 小一致。 又，該第一電極上表面以該第一凸緣為界之内部區域 最好沉積形成一層絕緣材料或貼設一絕緣層。 【實施方式】Page 9 1230415 V. Description of the invention (5) The flat portion and a ring-shaped flange whose size is equivalent to one side of the periphery of a semiconductor wafer, and the second electrode contains a second flat portion and a size equivalent to the semiconductor An annular flange on the other side of the wafer periphery, wherein the first and second flanges are the same size. In addition, it is preferable that an inner region of the upper surface of the first electrode bounded by the first flange is formed as an insulating material or an insulating layer is pasted. [Embodiment]
第1圖係本發明半導體晶圓乾式蝕刻用電極之部分斷 面圖。如圖所示，本發明之電極為一成對出現之電極組， 包括一第一電極10與一第二電極20。該第一與第二電極 10/20係一產生電漿（等離子體）之裝置以供移除沉積於一 半導體晶圓周緣之異物者。Fig. 1 is a partial sectional view of an electrode for dry etching of a semiconductor wafer according to the present invention. As shown in the figure, the electrode of the present invention is a pair of electrode groups, and includes a first electrode 10 and a second electrode 20. The first and second electrodes 10/20 are a plasma (plasma) generating device for removing foreign matter deposited on the periphery of a semiconductor wafer.
本案中，雖然該第一電極10做為陽極而第二電極20做 為陰極使用，但反之亦無不可。該第一電極10係呈扁平圓 盤狀，外觀與一般傳統電極相似，惟其底面具有一環狀之 第一凸緣10a及一設於該第一凸緣10a與該第一電極10周緣 間之進氣孔10b。該進氣孔10b係供引導一種用以產生電漿 之反應氣體，使之進入一内部設置該第一與第二電極 10/20之真空室（未示）、。 該第二電極20亦呈扁平圓盤狀，具有與該第一電極10 相同的直徑。又，該第二電極2 0中央部設有一開口 2 0 a， 而周緣與該開口 20a之間形成一大小與該第一凸緣1 0a相當 之環狀第二凸緣20b。 1230415 五、發明說明（6) 該第一電極1 0之第一凸緣1 〇a外側與該第二恭η 第二凸緣20b外側之平坦區域分別定義為^ 二=極20之 與一第二扁平部2〇c。 平部l〇c 一絕緣體或絕緣層11係沉積或貼附於該第一凸 底面之靠内區域，用以避免當RF電力施加於該第一盥a_ 電極10/20之間時兩電極間發生電場或電磁場Λ，其^材^二 為聚醯亞胺（poly imide)、鐵氟龍（Teflon)、欲^ #可 或陶磁等。 ^、石央、 第2與第3圖顯示採用本發明半導體晶圓乾式蝕 極時半導體晶圓之餘刻狀態。以下兹參閱該兩圖式 : 發明之第一及第二電極10/20與該半導體晶圓3〇 情況予以申述之。 m 如第2圖所示，該半導體晶圓3〇係利用一靜電 而插設於該做為陽極之第一電極丨〇及做為陰極之第二 2〇:間。該靜電夾盤40係進入該第二電極2〇之開口2〇a後 3:Λ低位置，藉使該半導體晶圓3〇之周緣下表面 30c侍與該第二電極2〇之第二凸緣2〇b形成接觸狀態。 此時若經過該第一電極1〇之進氣孔1〇b 一 氣體並由該RF發生哭50裎征兩士认分结 m 兩 =生的5〇詖供电力給該弟二電極2〇時，則該 ^20 Γ ^ 一凸緣丨與第一扁平部1 〇c及該第二電 七一命f 一凸緣2〇b與第二扁平部2 〇c所涵蓋的範圍内將形 =%或包磁％，而該反應氣體隨即在該第一凸緣“a 二、:凸緣20b之間及該第一扁平部1〇c與第二扁平部2〇c 之間座生兩種強度不同的電漿。In this case, although the first electrode 10 is used as the anode and the second electrode 20 is used as the cathode, the reverse is not necessary. The first electrode 10 is in the shape of a flat disk, and its appearance is similar to that of a conventional electrode, except that the bottom electrode has a ring-shaped first flange 10a and a space between the first flange 10a and the periphery of the first electrode 10. Air inlet hole 10b. The air inlet hole 10b is used to guide a reaction gas for generating plasma, and to enter a vacuum chamber (not shown), in which the first and second electrodes 10/20 are disposed. The second electrode 20 also has a flat disk shape and has the same diameter as the first electrode 10. In addition, an opening 20a is provided at the central portion of the second electrode 20, and a ring-shaped second flange 20b is formed between the peripheral edge and the opening 20a and has a size equivalent to that of the first flange 10a. 1230415 V. Description of the invention (6) The flat areas outside the first flange 10a of the first electrode 10 and outside the second flange 20b are defined as ^ 2 = the sum of the pole 20 and the first Two flat portions 20c. Flat portion 10c An insulator or insulating layer 11 is deposited or attached to the inner region of the first convex bottom surface, so as to avoid the RF between the two electrodes when the first power a_ electrode 10/20 is applied. When an electric or electromagnetic field Λ occurs, the two materials are poly imide, Teflon, Yukaku or ceramic magnet. ^, Shi Yang, Figures 2 and 3 show the remaining state of the semiconductor wafer when the semiconductor wafer dry-etching electrode of the present invention is used. The two drawings are hereinafter referred to: The first and second electrodes 10/20 of the invention and the semiconductor wafer 30 are described in detail. As shown in FIG. 2, the semiconductor wafer 30 is interposed between the first electrode as an anode and the second 20: as a cathode by using an electrostatic. The electrostatic chuck 40 enters the low position of 3: Λ after the opening 20a of the second electrode 20, so that the lower surface 30c of the peripheral edge of the semiconductor wafer 30 serves the second protrusion of the second electrode 20 The edge 20b is brought into contact. At this time, if a gas is passed through the air inlet hole 10b of the first electrode 10 and a cry occurs from the RF, 50 points will be identified, and two 50 m of electric power will be supplied to the second electrode 2. When the ^ 20 Γ ^ a flange 丨 and the first flat portion 10c and the second electric Qiyiming f a flange 20b and the second flat portion 20c will be shaped =% Or magnetic permeability%, and the reaction gas then generates two between the first flange "a II :: flange 20b and between the first flat portion 10c and the second flat portion 20c. Plasma with different strength.
1230415 五、發明說明（7) 本案中，電漿係沿該第一凸緣10a與該第二凸緣2〇b之 寬度形成，此寬度相當於該半導體晶圓3 0中準備接受姓刻 之周緣寬度B(B區）。因此，該半導體晶圓30中具有細微電 路圖案31的A區將不會受到該電漿的影響，而該半導體晶 圓3 0的側表面3 0 b則會被形成於該第一扁平部1 〇 ◦與該第二 扁平部2 0 c之間的電襞C所姓刻。 因為該半導體晶圓30的底面係與該第二電極2〇的第二 凸緣20b上表面接觸，所以，反應離子蝕刻RIE (Reactive1230415 V. Description of the invention (7) In this case, the plasma is formed along the width of the first flange 10a and the second flange 20b, which is equivalent to the semiconductor wafer 30 ready to accept the last name. Perimeter width B (B zone). Therefore, the area A with the fine circuit pattern 31 in the semiconductor wafer 30 will not be affected by the plasma, and the side surface 3 0 b of the semiconductor wafer 30 will be formed in the first flat portion 1 〇◦ The name of the electric ballast C between the second flat part 20 c and the second flat part 20 c is engraved. Since the bottom surface of the semiconductor wafer 30 is in contact with the top surface of the second flange 20b of the second electrode 20, reactive ion etching (Reactive)
Ion Etching)主要是在該半導體晶圓3〇的上表面3〇&與側 表面30b進行。 /、 其次，由於該絕緣層11係沉積（或貼設）於該第一電極 1 0之上表面，所以，A區内部不會形成任何電場或電磁 場，可防止在該區域内產生電漿以改善蝕刻效率。 此處的標號60代表一匹配電路。Ion Etching) is mainly performed on the upper surface 30 & the side surface 30b of the semiconductor wafer 30. / Secondly, because the insulating layer 11 is deposited (or attached) on the surface of the first electrode 10, no electric or electromagnetic field will be formed inside the area A, which can prevent the generation of plasma in this area. Improve etching efficiency. Reference numeral 60 here represents a matching circuit.
如第3圖所示，該靜電夾盤4〇係可通過該第二電極的 開口 20a而上升，藉使該半導體晶圓3〇的周緣上表面 住該第一電極10的第一凸緣1〇a表面。今經由該第一電極 1 0的進氣孔1 Ob導入反應氣體並由該RF發生器5〇提供電力 時’第一凸緣10a與第二凸緣2〇b之間隨即產生電聚。此 時’電漿的蝕刻動作主要是在該半導體晶圓30的下表面 30。與側表面m進行’藉以移除沉積糾區的異物。 第4圖顯不-的斷面’本發明的電極 真空室7。包括有：-用以導入可供產生電浆之反庫氣體彳 進入該第-電極1G與第二電簡之吹管71 ;-供^入該·As shown in FIG. 3, the electrostatic chuck 40 can be raised through the opening 20 a of the second electrode, so that the upper surface of the peripheral edge of the semiconductor wafer 30 can hold the first flange 1 of the first electrode 10. 〇a surface. When a reactive gas is introduced through the air inlet hole 1 Ob of the first electrode 10 and power is supplied from the RF generator 50, electricity is generated between the first flange 10a and the second flange 20b. At this time, the plasma etching operation is mainly performed on the lower surface 30 of the semiconductor wafer 30. Performed with the side surface m to remove foreign matter in the deposition correction region. Fig. 4 shows a cross-section of the electrode vacuum chamber 7 of the present invention. Including:-for introducing anti-storage gas that can be used to generate plasma 彳 into the first-electrode 1G and the blowing tube 71 of the second electric cell;-for the ·
第12頁 1230415Page 12 1230415
五、發明說明（8) 導體，圓30之埠口70a ; 一用以排放該半導體晶圓3〇蝕刻 後廢氣的排氣口70b ;及用以上下移動半導體晶圓3〇之該 靜電夾盤40。V. Description of the invention (8) Conductor, round 30 port 70a; an exhaust port 70b for exhausting the semiconductor wafer 30 after etching; and the electrostatic chuck for moving the semiconductor wafer 30 up and down 40.
姓刻之前置作業係先經由埠口 7 0 a將半導體晶圓3 〇 i关 入，真空室7〇且置於該靜電夾盤4〇之上，然後在反應氣體 的氛圍中’令該RF發生器50透過第二電極2〇提供電壓。此 % ’該半導體晶圓3〇之中心部位上表面受到該第一電極 之絕緣層1 1保護，而電漿僅發生在第一凸緣丨〇 a與第二凸 緣20b之間及第一扁平部丨〇c與第二扁平部2〇c之間，該半 導體晶圓30周緣部位之上、下、與侧表面3〇a/3〇c/3〇b乃 得依前述方式進行蝕刻。 與傳統情況相同’於實施蝕刻時該半導體晶圓3 〇上的 異物被移除，而反應氣體則經由該排氣口 7〇b被排出。 表1羅列使用本發明電極對半導體晶圓實施蝕刻之各 種反應氣體與使用對應反應氣體而被移除之異物。The previous operation is to first lock in the semiconductor wafer 300 via the port 70a, and place the vacuum chamber 70 above the electrostatic chuck 40. Then, in the atmosphere of the reaction gas, 'make the The RF generator 50 provides a voltage through the second electrode 20. The upper surface of the central part of the semiconductor wafer 30 is protected by the insulating layer 11 of the first electrode, and the plasma only occurs between the first flange 20a and the second flange 20b and the first Between the flattened portion oc and the second flattened portion oc, the upper, lower, and side surfaces of the semiconductor wafer 30 at the peripheral portion 30a / 3cc / 3b must be etched in the aforementioned manner. As in the conventional case, foreign matter on the semiconductor wafer 30 is removed when the etching is performed, and the reaction gas is discharged through the exhaust port 70b. Table 1 lists the various reaction gases for etching semiconductor wafers using the electrodes of the present invention and the foreign substances removed using the corresponding reaction gases.
1230415 五、發明說明（9) 表1 材 貿 S 反應氣艘 有機 ARC (SiON)'^ CF4, SF6 無機 ARC (CxSiY) CF4, 〇2 — 氡化物層（Si〇2) CF4, CHF3, C4Fs, C2F6, Ar,〇2, CH2F2 氛化物層（s13n4)-^^- CF4, SFe, CHF3, Ar, 〇2 聚矽化物層（Si) ' - HBr, Cl2, CC14, SF6, 〇2 矽化鎢（WSix) ^ sf6, ci2 鎢(W) — SF6, CF4, Ar, 02 鋁（Al) ~S' Cl2, CC14, BC13 銅（Cu) Cl2 氧化钽（Ta02) _ SF6, Cl2, cf4 钽（Ta〇N) sf6, Cl2, cf4 鈦(Ti) ^ cf4i sf6 發化欽（TiSix) sog sf6, CF4, O2 H(Si〇3/2) Φ1230415 V. Description of the invention (9) Table 1 Materials Trading S Reactors Organic ARC (SiON) '^ CF4, SF6 Inorganic ARC (CxSiY) CF4, 〇2 — Trioxide layer (Si〇2) CF4, CHF3, C4Fs, C2F6, Ar, 〇2, CH2F2 Alumina layer (s13n4)-^^-CF4, SFe, CHF3, Ar, 〇2 Polysilicide layer (Si) '-HBr, Cl2, CC14, SF6, 〇2 Tungsten silicide ( WSix) ^ sf6, ci2 tungsten (W) — SF6, CF4, Ar, 02 aluminum (Al) ~ S 'Cl2, CC14, BC13 copper (Cu) Cl2 tantalum oxide (Ta02) _ SF6, Cl2, cf4 tantalum (Ta〇 N) sf6, Cl2, cf4 titanium (Ti) ^ cf4i sf6 TiSix sog sf6, CF4, O2 H (Si〇3 / 2) Φ
如如所述’傳統餘玄,丨鞋要、系 即，使用一種濕式餘刻事2^ 2 =除某種4勿質’亦 外，可能還需要-種圓的氮化物層之 電路圖案。如此’一個蝕刻步ς纟^形成細微的 置來完成，使得整個飾利制尤要—種特定的蝕刻裝 « 而且，以傳統姓刻裝置的電； 半導體晶圓周緣上表面與側表面的里#t ’只有>儿積在 表面部分則無能為力。 /、 了破移除，對於下 然而，如果改採本發明的電極 時，只須循序供應對應於各種 -表1所不異物 同材^之適當反應氣體即As mentioned in the 'traditional Yuxuan, shoes, and systems, use a wet type engraving 2 ^ 2 = In addition to some kind of 4 do not matter', you may also need a circuit pattern of a round nitride layer . In this way, an etching step is completed to form a minute device, which makes the entire decoration system more important-a specific etching device «Moreover, the electricity of the device is engraved with the traditional name; the upper surface of the peripheral edge of the semiconductor wafer and the inner surface of the side surface #t 'Only > there is nothing that can be done on the surface. / 、 After the removal, for the next, however, if the electrode of the present invention is changed, it is only necessary to sequentially supply the appropriate reaction gas corresponding to various
1230415 五、發明說明（10) 可，完全不需要額外設備，故能大 再者，使用本發明的電極時，田間化裟程。 上表面、側表面、及下表面外，、除了半導體晶圓之 響…，得以在不損傷半導體位均不受電： 電路圖案的條件下’提昇蝕刻致^。央表面所形咸細 以上，對於熟悉本技術領域 ° 本理念當可運用於其他不同的方=人士而言，本發明的A 例僅供例證而非用以限制其實^圍：本：明提示之實： 化仍應受申請專利範圍各ψ請項:惟任何w伸之變 工業應用 伙以上說明可以釋知 體晶圓用電極係可“沉積於= : 乾式飪刻半導 側表面、及下表面之里、； _ θ曰圓周緣上表面、 備或步驟，故可藉以;，：完全不需要其他任何多餘之設 產性。 精乂簡化製程，降低成本，改善品質與生1230415 V. Description of the invention (10) Yes, no additional equipment is required at all, so it can be great. Furthermore, when using the electrode of the present invention, the field is transformed. Except for the upper surface, the side surface, and the lower surface, in addition to the effects of the semiconductor wafer ..., it is possible to prevent the semiconductor bits from being damaged without damage to the electrical circuit: under the condition of the circuit pattern ', the etching is promoted ^. The shape of the central surface is more than the above. For those who are familiar with the technical field, the concept of this invention can be applied to different parties. The A example of the present invention is for illustration only and is not intended to limit the fact. Actuality: Chemicals should still be subject to patent application. Each item: However, the above description can explain that the electrode system for bulk wafers can be "deposited on the surface of the semi-conductive side of the dry cooker, and the bottom In the surface, _ θ refers to the upper surface, preparation, or steps of the peripheral edge, so you can use it to:,: No need for any other extra design productivity. Simplify the process, reduce costs, improve quality and production
I 1230415 圖式簡單說明 _ 為使本發明之結構、 見，以下為配合實施例而裎=丨1用等更易於瞭解起 中·· 而提供之相關圖式簡要說明，其 第1圖係本發明半導 面圖； 阅％、微％用私極之部分斷 第2圖顯示採用本發 一半導體晶圓之上表面跑 晶圓乾式餘刻用電極時 第3圖顯示採用本發與狀態、； 一半導體晶圓之下表面鱼 曰曰圓乾式飯刻用電極時 第4圖係-設有本發H面之㈣狀態； 第5圖係一表面沉積夕極之乾式蝕刻裝置斷面圖； 第6圖顯示因設傷運二=2導體晶圓侧視圖； 之現象； 導致+導體晶圓表面沉積異物 第7a至7e圖係顯示利 氮化 物層之過程變化斷面圖；傳、、先濕式蝕刻法以移除 第8 a至8 e圖係顯示利 化物層之過程變化斷面圖；2、·先乾式蝕刻法以移除一聚矽 第9圖係利用傳統電極 亍等體日日®之示意圖。 【圖式標號說明】 10 ----電極 10a 環狀之第—凸緣 10b 進氣孔 l〇c 第一扁平部 1230415 圖式簡單說明 11-----—-絕緣層 20--------第二電極 20a-------開口 20b-------環狀第二凸緣 20c-------第二扁平部 30 --------半導體晶圓 30a-------半導體晶圓的上表面 30b-------半導體晶圓的側表面 30c-------半導體晶圓的下表面 31 --------電路圖案 40--------靜電夾盤 50--------RF發生器 60--------配電路 70 --------真空室 70a-------半導體晶圓的埠口 70b-------排氣口 71 --------吹管 100 -------半導體晶圓 100a-------半導體晶圓的上表面 1 0 Ob------半導體晶圓的侧面 100c------底面 101 -------氮化物層 102 -------氧化物層 103 -------阻光層I 1230415 Brief description of the drawings _ In order to make the structure of the present invention, see the following, in order to match the examples, it is easier to understand the starting point, etc. The related drawings are briefly explained. The first drawing is the text Inventive semiconducting surface view; Figures 2 and 3 show the partial break with a private pole. Figure 2 shows the use of the present invention when a semiconductor wafer runs on the top surface of a wafer with dry electrodes. Figure 3 shows the use of the current and state. ; Figure 4 is a round dry rice carving electrode on the lower surface of a semiconductor wafer. Figure 4 is a state where the H surface of the present invention is provided; Figure 5 is a cross-sectional view of a dry etching device with a surface deposited on the electrode; Fig. 6 shows the side view of the conductor wafer due to injury 2; the phenomenon; foreign matter deposition on the + conductor wafer surface. Figs. 7a to 7e are cross-sectional views showing the process change of the nitride layer; The wet etching method to remove the 8a to 8e pictures is a cross-sectional view showing the process change of the formation layer; 2. the dry etching method to remove a polysilicon. The 9th picture is to use a conventional electrode Schematic of Day®. [Illustration of figure numbers] 10 ---- electrode 10a ring-shaped first-flange 10b air inlet hole 10c first flat portion 1230415 simple illustration of the diagram 11 -------insulation layer 20 --- ----- Second electrode 20a ------- Opening 20b ------- Annular second flange 20c ------- Second flat portion 30 ------ --Semiconductor wafer 30a ------- Upper surface of semiconductor wafer 30b ------- Side surface of semiconductor wafer 30c ------- Lower surface of semiconductor wafer 31- ------ Circuit pattern 40 -------- Static chuck 50 -------- RF generator 60 -------- With circuit 70 ------ --Vacuum chamber 70a ------- Port of semiconductor wafer 70b ------- Exhaust port 71 -------- Blowpipe 100 ------- Semiconductor wafer 100a ------- top surface of semiconductor wafer 1 0 Ob ------ side surface of semiconductor wafer 100c ------ bottom surface 101 ------- nitride layer 102- ----- Oxide layer 103 ------- Light blocking layer
第17頁 1230415Page 12 1230415
第18頁Page 18
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2002-0011395A KR100442194B1 (en) | 2002-03-04 | 2002-03-04 | Electrodes For Dry Etching Of Wafer |
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| TW200304183A TW200304183A (en) | 2003-09-16 |
| TWI230415B true TWI230415B (en) | 2005-04-01 |
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| JP (1) | JP4152895B2 (en) |
| KR (1) | KR100442194B1 (en) |
| AU (1) | AU2002253689A1 (en) |
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| WO (1) | WO2003075333A1 (en) |
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2002
- 2002-03-04 KR KR10-2002-0011395A patent/KR100442194B1/en active IP Right Review Request
- 2002-04-19 US US10/506,558 patent/US20050178505A1/en not_active Abandoned
- 2002-04-19 JP JP2003573690A patent/JP4152895B2/en not_active Expired - Fee Related
- 2002-04-19 WO PCT/KR2002/000715 patent/WO2003075333A1/en active Application Filing
- 2002-04-19 AU AU2002253689A patent/AU2002253689A1/en not_active Abandoned
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| Publication number | Publication date |
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| TW200304183A (en) | 2003-09-16 |
| AU2002253689A1 (en) | 2003-09-16 |
| WO2003075333A1 (en) | 2003-09-12 |
| KR20030072520A (en) | 2003-09-15 |
| US20050178505A1 (en) | 2005-08-18 |
| JP2005519469A (en) | 2005-06-30 |
| KR100442194B1 (en) | 2004-07-30 |
| JP4152895B2 (en) | 2008-09-17 |
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