JP2005519469A - Semiconductor wafer dry etching electrode - Google Patents

Semiconductor wafer dry etching electrode Download PDF

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JP2005519469A
JP2005519469A JP2003573690A JP2003573690A JP2005519469A JP 2005519469 A JP2005519469 A JP 2005519469A JP 2003573690 A JP2003573690 A JP 2003573690A JP 2003573690 A JP2003573690 A JP 2003573690A JP 2005519469 A JP2005519469 A JP 2005519469A
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キム，ヨンユル
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シーアイ サイエンス，インコーポレイテッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
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Abstract

本発明は、半導体ウェーハ乾式蝕刻用電極に関し、本発明の電極は第1及び第2一対の電極からなり、前記第1電極は半導体ウェーハ端部の上下部分中いずれか一方と対向する環型の第1突出部及び第1平坦部を備え、前記の第2電極は、前記の半導体ウェーハ端部の上下部分のいずれか一方と対向し、前記の第1突出部及び第1平坦部と同一寸法で形成された第2突出部及び第2平坦部を備えていることを特徴とする。The present invention relates to a semiconductor wafer dry etching electrode, the electrode of the present invention comprises a first and a second pair of electrodes, the first electrode is an annular type facing either one of the upper and lower portions of the semiconductor wafer end portion A first protrusion and a first flat portion, wherein the second electrode faces either one of the upper and lower portions of the semiconductor wafer end, and has the same dimensions as the first protrusion and the first flat portion. The second projecting portion and the second flat portion formed in (1) are provided.

Description

本発明は、半導体ウェーハの乾式蝕刻に関するものであって、特に集積回路素子製造用の半導体ウェーハの端部に積層された各種の異物をプラズマで除去するための、半導体ウェーハ乾式蝕刻用電極に関する。   The present invention relates to dry etching of a semiconductor wafer, and more particularly to an electrode for dry etching of a semiconductor wafer for removing various foreign matters stacked on the end of a semiconductor wafer for manufacturing an integrated circuit element with plasma.

一般に、高集積度の半導体素子を製造する過程では、図5のように半導体ウェーハ100の端部にポリシリコン膜、窒化膜層、金属層等110、120が形成、累積される。また、図6のように半導体ウェーハ100の運送中、または備品200との接触により半導体ウェーハ100端部に付着した層が砕けて、半導体ウェーハ100の内部に入り込み、集積回路素子内に含有される場合が発生する。   In general, in the process of manufacturing a highly integrated semiconductor device, a polysilicon film, a nitride film layer, a metal layer, etc. 110 and 120 are formed and accumulated at the end of the semiconductor wafer 100 as shown in FIG. Further, as shown in FIG. 6, the layer attached to the edge of the semiconductor wafer 100 is broken during transportation of the semiconductor wafer 100 or by contact with the fixture 200, and enters the inside of the semiconductor wafer 100 and is contained in the integrated circuit element. A case occurs.

この他にも、近年、半導体素子のゲート電極がケイ化タングステンからタングステンに、コンデンサの絶縁膜はONO（oxide-nitrid-oxide）構造から酸化タンタルに変わり、フォトレジストのマスク微細パターン形成のための有機性ボトム反射防止膜（anti-reflective coating，以下「ARC」という）層及び無機性ARC層のSiON、障壁金属(barrier metal)層のTi、TiN層を使用する傾向により、これらの異物が半導体素子の製造工程中で、前記のような経路により半導体ウェーハを汚染させるようになる。   In addition, in recent years, the gate electrode of a semiconductor element has changed from tungsten silicide to tungsten, and the insulating film of the capacitor has changed from an ONO (oxide-nitrid-oxide) structure to tantalum oxide. Due to the tendency to use organic bottom anti-reflective coating (ARC) layer and inorganic ARC layer SiON, barrier metal layer Ti, TiN layer, these foreign substances are semiconductor During the device manufacturing process, the semiconductor wafer is contaminated by the above-described path.

このような異物は、半導体の製造工程が進行するにつれパーティクルの原因となって半導体ウェーハ100を汚染するようになるが、特に半導体ウェーハの直径が200mmから300mmに転換されると、半導体ウェーハ端部の半径もさらに大きくなるため、パーティクルによる半導体ウェーハの汚染もまた大きくなってしまうのが実情である。   Such foreign matter causes particles to contaminate the semiconductor wafer 100 as the semiconductor manufacturing process progresses, especially when the diameter of the semiconductor wafer is changed from 200 mm to 300 mm. Since the radius of the wafer becomes larger, the contamination of the semiconductor wafer by particles is also increased.

従って、半導体素子の歩留りと信頼性に影響を及ぼす半導体ウェーハ100端部の異物は完全に除去する必要がある。   Therefore, it is necessary to completely remove the foreign matter at the edge of the semiconductor wafer 100 that affects the yield and reliability of the semiconductor element.

このため、従来から、半導体ウェーハの端部に付着、累積した異物を除去するために、次のような方法が使用されてきた。   For this reason, conventionally, the following method has been used in order to remove the foreign matter adhering to and accumulating at the end of the semiconductor wafer.

例えば、湿式蝕刻を用いた窒化膜の除去工程は、次のように5段階からなる(図7a〜図7e参照)。   For example, the nitride film removal process using wet etching includes five steps as follows (see FIGS. 7a to 7e).

i. シリコン半導体ウェーハ100に既に蒸着された窒化膜101の上に、プラズマ蒸着装置を用いて酸化膜102を蒸着させる(図7a)。   i. On the nitride film 101 already deposited on the silicon semiconductor wafer 100, an oxide film 102 is deposited using a plasma deposition apparatus (FIG. 7a).

ii. 前記酸化膜102の上に感光剤を塗布して感光膜103を形成し、半導体ウェーハ100の端部にある感光膜103のみを除去して酸化膜102が表れるようにする(図7b)。   ii. A photosensitive agent is applied on the oxide film 102 to form a photosensitive film 103, and only the photosensitive film 103 at the edge of the semiconductor wafer 100 is removed so that the oxide film 102 appears (FIG. 7b). .

iii. 半導体ウェーハ100の端部に表れた酸化膜102を湿式蝕刻装置を用いて化学溶液(NHF4+HF)で除去する(図7c)。 iii. The oxide film 102 appearing at the edge of the semiconductor wafer 100 is removed with a chemical solution (NHF 4 + HF) using a wet etching apparatus (FIG. 7c).

iv. 酸化膜102の上にある感光膜103を乾式蝕刻装置を用いて除去し、洗浄装置を用いて化学溶液(H2SO4/H2O2)で残留感光膜103を除去する(図7d)。 iv. The photosensitive film 103 on the oxide film 102 is removed using a dry etching apparatus, and the residual photosensitive film 103 is removed with a chemical solution (H 2 SO 4 / H 2 O 2 ) using a cleaning apparatus (FIG. 7d).

v. 半導体ウェーハ100の端部に表れた窒化膜101を湿式蝕刻装置を用いて高温のリン酸(H3PO4)溶液で除去する(図7e)。 v. The nitride film 101 appearing at the end of the semiconductor wafer 100 is removed with a high-temperature phosphoric acid (H 3 PO 4 ) solution using a wet etching apparatus (FIG. 7e).

ところが、このような従来の湿式蝕刻による窒化膜の除去工程は、その段階が複雑で、工程の遂行において酸化膜の蒸着、感光剤の塗布、湿式蝕刻による酸化膜の除去、乾式蝕刻による感光膜の除去、洗浄、窒化膜の湿式蝕刻等のための様々な装置を要するという問題点がある。   However, the conventional removal process of the nitride film by wet etching is complicated, and the oxide film is deposited, the photosensitive agent is applied, the oxide film is removed by wet etching, and the photosensitive film is formed by dry etching. There is a problem that various apparatuses are required for removal, cleaning, wet etching of a nitride film, and the like.

一方、従来の別の例として、乾式蝕刻を用いたポリシリコン膜の除去工程は次のように5段階からなる(図8a〜図8e参照)。   On the other hand, as another conventional example, the removal process of the polysilicon film using dry etching includes five steps as follows (see FIGS. 8a to 8e).

i. シリコン半導体ウェーハ100上に蒸着されたポリシリコン膜104の上にプラズマ蒸着装置を用いて酸化膜102を蒸着させる(図8a)。   i. An oxide film 102 is deposited on the polysilicon film 104 deposited on the silicon semiconductor wafer 100 using a plasma deposition apparatus (FIG. 8a).

ii. 感光剤を塗布して感光膜103を形成し、半導体ウェーハ100の端部にある感光膜103を除去して酸化膜102が表れるようにする(図8b)。   ii. A photosensitive agent is applied to form the photosensitive film 103, and the photosensitive film 103 at the end of the semiconductor wafer 100 is removed so that the oxide film 102 appears (FIG. 8b).

iii. 半導体ウェーハ100の端部に表れた酸化膜102を湿式蝕刻装置を用いて化学溶液(NHF4+HF)で除去する(図8c)。 iii. The oxide film 102 appearing at the edge of the semiconductor wafer 100 is removed with a chemical solution (NHF 4 + HF) using a wet etching apparatus (FIG. 8c).

iv. 前記酸化膜102の上にある感光膜103を感光膜の乾式蝕刻装置を用いて除去し、洗浄装置を用いて化学溶液(H2SO4/H2O2)で残留感光膜103を除去する(図8d)。 iv. The photosensitive film 103 on the oxide film 102 is removed using a dry etching apparatus for the photosensitive film, and the residual photosensitive film 103 is removed with a chemical solution (H 2 SO 4 / H 2 O 2 ) using a cleaning apparatus. Remove (FIG. 8d).

v. 半導体ウェーハ100の端部に表れたポリシリコン膜104を従来の乾式蝕刻装置を用いて除去する(図8e)。   v. The polysilicon film 104 appearing at the end of the semiconductor wafer 100 is removed using a conventional dry etching apparatus (FIG. 8e).

以上のような従来の乾式蝕刻によるポリシリコン膜の除去工程でも、湿式蝕刻による窒化膜の除去工程と同様に、その段階が複雑で、工程の遂行において酸化膜の蒸着、感光剤の塗布、湿式蝕刻による酸化膜の除去、乾式蝕刻による感光膜の除去、洗浄、乾式蝕刻によるポリシリコン膜の除去などのための様々な装置を要するという問題点がある。   Even in the conventional removal process of the polysilicon film by dry etching, the process is complicated as in the removal process of the nitride film by wet etching, and in the execution of the process, the oxide film is deposited, the photosensitive agent is applied, and the wet process is performed. There is a problem that various apparatuses are required for removing an oxide film by etching, removing a photosensitive film by dry etching, cleaning, removing a polysilicon film by dry etching, and the like.

さらに、半導体ウェーハの端部にあるポリシリコン膜の除去の際、従来の乾式蝕刻装置による場合、半導体ウェーハ端部の上面部に対しては除去が可能であるが、半導体ウェーハ端部の側面部と下面部に対する除去は不完全であるか、ほぼ不可能になる問題点がある。   Furthermore, when removing the polysilicon film at the edge of the semiconductor wafer, the conventional dry etching apparatus can remove the upper surface of the semiconductor wafer, but the side surface of the semiconductor wafer edge. There is a problem that the removal to the lower surface portion is incomplete or almost impossible.

これだけでなく、従来の蝕刻装置は半導体ウェーハにパターンを形成するそれぞれの工程毎に個別的に使用されるしかないため、前記で説明した例のように、ある一つの異物のみを除去するに留まり、1種類の蝕刻装置では様々な異物を全部除去できないという問題点がある。   In addition to this, the conventional etching apparatus can only be used individually for each process of forming a pattern on a semiconductor wafer, so that only one foreign substance is removed as in the example described above. However, there is a problem that one type of etching apparatus cannot remove all the various foreign substances.

一方、従来において半導体素子の微細回路パターンの形成に一般的に使用されている乾式蝕刻装置は、図9に図示するように、反応ガスの雰囲気下で平板状の第1電極及び第2電極300、300’の間に電場を形成し、半導体ウェーハ100の上面部にプラズマを発生させることにより、半導体ウェーハ100の上面部100aに積層された物質を微細パターン103aの模様に蝕刻するが、このとき半導体素子の製造時に半導体ウェーハ100の端部に累積された異物積層膜の一部を除去するようになる。未説明の符号400，500はそれぞれ高周波電源とマッチングネットワーク(matching network)である。   On the other hand, a conventional dry etching apparatus generally used for forming a fine circuit pattern of a semiconductor device has a flat plate-like first electrode and second electrode 300 in an atmosphere of a reactive gas as shown in FIG. , By forming an electric field between 300 'and generating plasma on the upper surface of the semiconductor wafer 100, the material stacked on the upper surface 100a of the semiconductor wafer 100 is etched into the pattern of the fine pattern 103a. A part of the foreign material laminated film accumulated at the end of the semiconductor wafer 100 during the manufacture of the semiconductor element is removed. Reference numerals 400 and 500 that are not described are a high-frequency power source and a matching network, respectively.

しかし、このような従来の乾式蝕刻装置は、半導体ウェーハ100が一方の電極300’上に置かれた状態で工程が行われるため、プラズマが半導体ウェーハ100の側面部100bと底面100c部には影響を及ぼせないことにより、半導体ウェーハ100の側面部100bと下面100c部に積層された異物は除去することが困難であるという問題点がある。   However, in such a conventional dry etching apparatus, since the process is performed with the semiconductor wafer 100 placed on one electrode 300 ′, the plasma affects the side surface portion 100b and the bottom surface 100c portion of the semiconductor wafer 100. Therefore, it is difficult to remove the foreign matters stacked on the side surface portion 100b and the lower surface 100c portion of the semiconductor wafer 100.

本発明は前述したような諸般の問題点を解消するために案出されたものであって、その目的は半導体の製造工程中で、半導体ウェーハ端部の上面部はもちろん、側面部や下面部に積層形成された異物を、半導体ウェーハに損傷を与えることなく、効果的に完全に除去できる半導体ウェーハ乾式蝕刻用電極を提供することにある。   The present invention has been devised in order to solve the various problems as described above, and its purpose is during the semiconductor manufacturing process, not only the upper surface portion of the semiconductor wafer end portion, but also the side surface portion and the lower surface portion. An object of the present invention is to provide a semiconductor wafer dry etching electrode capable of effectively and completely removing foreign matters laminated and formed without damaging the semiconductor wafer.

前記のような目的を達成するための本発明による半導体ウェーハ乾式蝕刻用電極は、プラズマを形成させて半導体ウェーハ端部の異物を除去する第1及び第2一対の半導体ウェーハ乾式蝕刻用電極において、前記第1電極は、前記半導体ウェーハ端部の上面部、下面部のいずれか一方と対向する環状の第1突出部及び第1平坦部を備え、前記第2電極は、前記半導体ウェーハ端部の上面部、下面部の他方と対向し、前記第1突出部及び第1平坦部と同一寸法で形成された第2突出部及び第2平坦部を備えていることを特徴的な技術的思想とする。   The semiconductor wafer dry etching electrode according to the present invention for achieving the above-mentioned object is a first and second pair of semiconductor wafer dry etching electrodes for forming a plasma and removing foreign matter at the edge of the semiconductor wafer. The first electrode includes an annular first projecting portion and a first flat portion facing either the upper surface portion or the lower surface portion of the semiconductor wafer end portion, and the second electrode is formed on the semiconductor wafer end portion. A technical idea that includes a second projecting portion and a second flat portion facing the other of the upper surface portion and the lower surface portion, and having the same dimensions as the first projecting portion and the first flat portion. To do.

ここで、前記第1電極の前記半導体ウェーハと対向する面の中心部から突出部の内径に至る部位に絶縁体を塗布し、又は絶縁膜を付着することもできる。   Here, an insulator may be applied or an insulating film may be attached to a portion extending from the center of the surface of the first electrode facing the semiconductor wafer to the inner diameter of the protrusion.

本発明に係る半導体ウェーハ乾式蝕刻用電極は、半導体の製造工程で別途の追加工程を要することなく、半導体ウェーハ端部の上面部はもちろん、側面部や下面部に積層された様々な異物を全て除去することにより、工程の単純化と工程費用の節減、そして歩留りと品質及び生産性の向上に寄与する。   The electrode for dry etching of a semiconductor wafer according to the present invention does not require any additional steps in the semiconductor manufacturing process, and removes all the various foreign substances laminated on the side surface and the bottom surface as well as the upper surface of the semiconductor wafer edge. The removal contributes to simplification of the process, reduction of process cost, and improvement of yield, quality and productivity.

以下、本発明の好適な実施例を添付する図面により詳細に説明する。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図1は、本発明に係る半導体ウェーハ乾式蝕刻用電極を示した部分断面斜視図であって、半導体ウェーハの端部に付着、累積した異物を除去するためのプラズマ発生手段の一対の電極、即ち、第1電極10と第2電極20が示されている。   FIG. 1 is a partial cross-sectional perspective view showing an electrode for dry etching of a semiconductor wafer according to the present invention, and a pair of electrodes of plasma generating means for removing foreign matter adhering to and accumulating at the end of a semiconductor wafer, that is, A first electrode 10 and a second electrode 20 are shown.

便宜上、これらの電極10、20のうち第1電極10を陽極(anode)にし、第2電極20を陰極(cathode)にして説明するが、第1電極10が陰極、第2電極20が陽極になることもある。   For convenience, the first electrode 10 of these electrodes 10 and 20 will be described as an anode and the second electrode 20 will be described as a cathode, but the first electrode 10 is a cathode and the second electrode 20 is an anode. Sometimes.

前記第1電極10の大まかな形状は、通常の電極と同様に円形の平板からなるが、その底面部に環状の突出部10aが形成されていることを特徴的な構造とし、この突出部10aと外径の間には本発明の第1及び第2電極10、20が設置される真空チャンバー(図示省略)の内部に、プラズマ形成用の反応ガスを吹き込むためのガス吹込口10bが形成されている。   The rough shape of the first electrode 10 is a circular flat plate as in the case of a normal electrode, but has a characteristic structure in which an annular protrusion 10a is formed on the bottom surface thereof, and this protrusion 10a. Between the outer diameter and the outer diameter, a gas blowing port 10b for blowing a reactive gas for plasma formation is formed inside a vacuum chamber (not shown) in which the first and second electrodes 10 and 20 of the present invention are installed. ing.

そして、前記の第2電極20は、前記の第1電極10に対応する同一直径の円形の平板からなるが、中央には上下に貫通された開口部20aが形成されており、この開口部20aと外径の間には前記第1電極の突出部10a（以下，便宜上，「第1突出部」という）と対向する同一寸法の環型突出部20b （以下，前記の第1突出部と区分して「第2突出部」という）が形成されている。   The second electrode 20 is formed of a circular flat plate having the same diameter corresponding to the first electrode 10, and an opening 20a penetrating vertically is formed at the center. The opening 20a And the outer diameter of the ring-shaped protruding portion 20b (hereinafter referred to as the first protruding portion) of the same size facing the protruding portion 10a of the first electrode (hereinafter referred to as “first protruding portion” for convenience). (Referred to as “second projecting portion”).

さらに、前記第1電極10の第1突出部10aと第2電極20の第2突出部20b外側の平坦部は、便宜上それぞれ第1平坦部10cと第2平坦部20cと称して区分する。   Further, the flat portions outside the first protruding portion 10a of the first electrode 10 and the second protruding portion 20b of the second electrode 20 are classified as a first flat portion 10c and a second flat portion 20c for convenience.

一方、前記第1電極10の底面中心部から第1突出部10aの内径に至る部位には、第1電極10と第2電極20の間に高周波電力が印加されたとき、この部位に電場または電磁場が形成できないようにするために絶縁体11が塗布されたり、絶縁膜が付着されることもある。このような絶縁体11には、ポリイミド(Polyimide)またはテフロン(Teflon)（登録商標、以下同じ）、シリコン(silicon)、石英(quartz)、セラミック(ceramic)などを例として挙げられる。   On the other hand, when a high frequency power is applied between the first electrode 10 and the second electrode 20 in a portion from the center of the bottom surface of the first electrode 10 to the inner diameter of the first protrusion 10a, an electric field or Insulator 11 may be applied or an insulating film may be deposited to prevent the formation of an electromagnetic field. Examples of the insulator 11 include polyimide or Teflon (registered trademark, the same applies hereinafter), silicon, quartz, ceramic, and the like.

添付する図面の図2と図3はそれぞれ本発明に係る電極を用いた半導体ウェーハの蝕刻を説明する図面であって、以下では図面を中心に本発明の電極10、20と半導体ウェーハ30間の相互作用を説明する。   2 and 3 of the accompanying drawings are drawings for explaining etching of a semiconductor wafer using the electrode according to the present invention, respectively, and hereinafter, between the electrodes 10 and 20 of the present invention and the semiconductor wafer 30 with a focus on the drawings. Explain the interaction.

まず、図2により見てみると、半導体ウェーハ30を静電チャック(Electrostatic Chuck)40により陽極の第1電極10と陰極の第2電極20の間に介在させ、静電チャック40が第2電極20の開口部20aを介して低い位置に取り付けられることにより、半導体ウェーハ30端部の下面部30cが第2電極20の第2突出端20bの上側に接触する。   First, referring to FIG. 2, a semiconductor wafer 30 is interposed between an anode first electrode 10 and a cathode second electrode 20 by an electrostatic chuck 40, and the electrostatic chuck 40 is a second electrode. By being attached to a lower position through the 20 openings 20a, the lower surface portion 30c of the end portion of the semiconductor wafer 30 contacts the upper side of the second protruding end 20b of the second electrode 20.

この状態で、第1電極10のガス吹込口10bを通して反応ガスを吹き込み、高周波電源50から第2電極20に電力を印加すると、第1電極10の第1突出部10a及び第1平坦部10c、第2電極20の第2突出部20b及び第2平坦部20cを通じて電場または電磁場が形成され、反応ガスにより2つの突出部10a、20bと2つの平坦部10c、20c間に互いに異なる強度を有する2種類のプラズマが発生する。   In this state, when the reactive gas is blown through the gas blowing port 10b of the first electrode 10 and electric power is applied from the high frequency power supply 50 to the second electrode 20, the first protruding portion 10a and the first flat portion 10c of the first electrode 10 are obtained. An electric field or an electromagnetic field is formed through the second protrusion 20b and the second flat part 20c of the second electrode 20, and the reaction gas has two different strengths between the two protrusions 10a and 20b and the two flat parts 10c and 20c. A kind of plasma is generated.

このとき、プラズマは第1突出部10aと第2突出部20bそれぞれの幅に沿って形成されるが、これら突出部10a、20bの幅は対向している半導体ウェーハ30の蝕刻しようとする端部(図面に「B」で表された領域)に該当する程度の寸法で製作され使用されることにより、半導体ウェーハ30の微細パターン31が形成されている部位(図面に「A」で表された領域)にはプラズマの影響が及ばず、第1平坦部10cと第2平坦部20cの間 (図面に「C」で表された部位)に形成されたプラズマは半導体ウェーハ30の側面部30bを蝕刻する。   At this time, the plasma is formed along the width of each of the first protrusion 10a and the second protrusion 20b, and the width of the protrusions 10a and 20b is the end of the semiconductor wafer 30 that is opposed to be etched. By manufacturing and using a size corresponding to (region represented by “B” in the drawing), the portion where the fine pattern 31 of the semiconductor wafer 30 is formed (represented by “A” in the drawing) (Region) is not affected by the plasma, and the plasma formed between the first flat portion 10c and the second flat portion 20c (the portion indicated by `` C '' in the drawing) passes through the side surface portion 30b of the semiconductor wafer 30. Etch.

特に、半導体ウェーハ30の下面部30cが第2電極20の第2突出部20bの上面部に接した状態であるため、主に半導体ウェーハ30の上面部30aと側面部30bに局限され、この部分に対する異物を除去できる範囲内でRIE(Reactive Ion Etching)により蝕刻が行われる。   In particular, since the lower surface portion 30c of the semiconductor wafer 30 is in contact with the upper surface portion of the second protruding portion 20b of the second electrode 20, it is mainly limited to the upper surface portion 30a and the side surface portion 30b of the semiconductor wafer 30, and this portion Etching is performed by RIE (Reactive Ion Etching) within a range in which foreign matter can be removed.

さらに、第1電極10の底面中心部から第1突出部10aの内径に至る部位に備えられている絶縁体11により、「A」領域には電場または電磁場が形成されないため、この「A」領域でのプラズマ発生が事前に防止されることで、より安定的な蝕刻効果を示すことができる。   Further, since the electric field or electromagnetic field is not formed in the “A” region by the insulator 11 provided in the region from the center of the bottom surface of the first electrode 10 to the inner diameter of the first protruding portion 10a, this “A” region By preventing plasma generation in advance, a more stable etching effect can be shown.

図面における未説明の符号60はマッチングネットワークである。   Reference numeral 60 in the drawing which is not described is a matching network.

一方、図3のように、第2電極20の開口部20aを通して静電チャック40を上昇させて、半導体ウェーハ30端部の上面部30aが第1電極10の第1突出部10aの表面に接するようにした状態で、第1電極10のガス吹込口10bを通して反応ガスを吹き込み、高周波電源50から電力を印加すると、前記と同様に第1突出部10aと第2突出部20bを通してプラズマが発生するが、このときは主に半導体ウェーハ30端部の下面部30cと側面部30bに局限され、この部分(「B」領域)に対する異物を除去できる範囲内でプラズマにより蝕刻が行われる。   On the other hand, as shown in FIG. 3, the electrostatic chuck 40 is raised through the opening 20a of the second electrode 20, and the upper surface 30a at the end of the semiconductor wafer 30 contacts the surface of the first protrusion 10a of the first electrode 10. In such a state, when reactive gas is blown through the gas blowing port 10b of the first electrode 10 and electric power is applied from the high frequency power supply 50, plasma is generated through the first protruding portion 10a and the second protruding portion 20b as described above. However, at this time, the etching is performed mainly by the plasma within a range in which foreign matters on the portion (“B” region) can be removed.

図4は、本発明の電極が通常の真空チャンバーに設置されて適用された例を示しているが、この真空チャンバー70には本発明の電極10、20でプラズマを発生させるための反応ガス吹込用の導管71と、半導体ウェーハ30を搬入するための出入口70a、半導体ウェーハ30の蝕刻後のガスを排出するための排出口70b、そして半導体ウェーハ30が上下に昇降できるようにする静電チャック40を備えている。   FIG. 4 shows an example in which the electrode of the present invention is installed and applied in a normal vacuum chamber. This vacuum chamber 70 is injected with a reactive gas for generating plasma with the electrodes 10 and 20 of the present invention. Conduit 71, inlet / outlet port 70a for carrying in semiconductor wafer 30, discharge port 70b for discharging gas after etching of semiconductor wafer 30, and electrostatic chuck 40 for allowing semiconductor wafer 30 to move up and down It has.

従って、出入口70aを通して真空チャンバー70内に半導体ウェーハ30を進入させて静電チャック40の上に載置した後、反応ガスの雰囲気下で第2電極20を通して高周波電源50の電圧を印加すると、第1電極10の絶縁体11により半導体ウェーハ30上面部の中央部は完全に保護された上で、第1電極10の第1突出部10a及び第1平坦部10cと第2電極20の第2突出部20b及び第2平坦部20cの間でのみプラズマが形成されることにより、前述したような過程を通して半導体ウェーハ30端部の上面部30a、下面部30c、側面部30bに対する蝕刻が行われる。   Accordingly, after the semiconductor wafer 30 is advanced into the vacuum chamber 70 through the entrance / exit 70a and placed on the electrostatic chuck 40, the voltage of the high frequency power supply 50 is applied through the second electrode 20 in the atmosphere of the reaction gas. The central portion of the upper surface of the semiconductor wafer 30 is completely protected by the insulator 11 of the first electrode 10, and the first protrusion 10a and the first flat portion 10c of the first electrode 10 and the second protrusion of the second electrode 20 By forming plasma only between the portion 20b and the second flat portion 20c, the upper surface portion 30a, the lower surface portion 30c, and the side surface portion 30b at the end of the semiconductor wafer 30 are etched through the process described above.

このようにして蝕刻工程が進行される間、従来と同様に半導体ウェーハ30から除去された異物と反応ガスは排出口70bを通して吸い出される。   While the etching process is proceeding in this way, the foreign matter and the reaction gas removed from the semiconductor wafer 30 are sucked out through the discharge port 70b as in the prior art.

一方、本発明による電極を用いて行われる半導体ウェーハの端部に対する乾式蝕刻は、表1に示した蝕刻用反応ガスを用いて対応する異物を除去することができる。

Figure 2005519469
On the other hand, the dry etching performed on the edge portion of the semiconductor wafer using the electrode according to the present invention can remove the corresponding foreign matter using the etching reaction gas shown in Table 1.
Figure 2005519469

前述したように、従来は、窒化膜除去用の湿式蝕刻装置または微細パターン形成用の乾式蝕刻装置のように、ある1種類の物質のみを除去するために考案されたり、そのような機能のみを持つ蝕刻装置が使用されてきたため、各種の異物を除去するためには対応する蝕刻装置が必要で、工程もまた複雑だった。   As described above, conventionally, such as a wet etching apparatus for removing a nitride film or a dry etching apparatus for forming a fine pattern, it has been devised to remove only one kind of substance, or only such a function is performed. Since the etching apparatus that has been used has been used, a corresponding etching apparatus is required to remove various foreign substances, and the process is also complicated.

また、電極の構造においても、従来は半導体ウェーハの端部中、上面部と側面部に対する異物の除去のみが確かに行われただけで、半導体ウェーハ端部の下面部に対する異物の除去は非常に困難だった。   Also in the structure of the electrode, conventionally, only the removal of foreign matter on the upper surface and side surfaces of the end portion of the semiconductor wafer has been reliably performed, and the removal of foreign matter on the lower surface portion of the semiconductor wafer end portion has been extremely difficult. It was difficult.

しかし、本発明の電極を適用する場合は、半導体ウェーハに微細パターンを形成する過程で除去されなかった、表1に例示されている異物を除去するための各異物に対応する蝕刻用反応ガスの交替のみを通じて、連続的に全ての異物を除去することが可能であるため、別途の装備を備える必要がなく工程が単純化される。   However, when the electrode of the present invention is applied, the etching reaction gas corresponding to each foreign material for removing the foreign material illustrated in Table 1 that was not removed in the process of forming the fine pattern on the semiconductor wafer was used. Since it is possible to remove all foreign substances continuously only through replacement, it is not necessary to provide additional equipment, and the process is simplified.

これだけでなく、半導体ウェーハ端部の上面部と側面部及び下面部以外の部位には、プラズマの影響が及ばないようになっているため、端部に対する効果的な蝕刻が行われ、また、半導体ウェーハ中央部の微細パターン部位には全く損傷を与えない。   In addition to this, the portions other than the top surface, the side surface, and the bottom surface of the semiconductor wafer edge are not affected by plasma, so that the edge is effectively etched, and the semiconductor There is no damage to the fine pattern portion at the center of the wafer.

本発明に係る半導体ウェーハの乾式蝕刻用電極は、前記で説明した実施例に限定されず、特許請求の範囲に記載された技術的思想の範疇内で当業者により多様な変更及び変形実施が可能であることは勿論、このような変更及び変形実施は記載された特許請求の範囲に属すると言える。   The electrode for dry etching of a semiconductor wafer according to the present invention is not limited to the embodiment described above, and various modifications and changes can be made by those skilled in the art within the scope of the technical idea described in the claims. Of course, such modifications and variations are considered to be within the scope of the appended claims.

本発明に係る半導体ウェーハ乾式蝕刻用電極を示した部分断面斜視図である。1 is a partial cross-sectional perspective view showing a semiconductor wafer dry etching electrode according to the present invention. 本発明に係る電極を用いた半導体ウェーハの上面部及び側面部の蝕刻を説明する図である。It is a figure explaining the etching of the upper surface part and side part of a semiconductor wafer using the electrode which concerns on this invention. 本発明に係る電極を用いた半導体ウェーハの下面部及び側面部の蝕刻を説明する図である。It is a figure explaining the etching of the lower surface part and side part of a semiconductor wafer using the electrode which concerns on this invention. 本発明に係る電極が設置された乾式蝕刻装置を示した断面図である。It is sectional drawing which showed the dry-type etching apparatus in which the electrode which concerns on this invention was installed. 異物が積層された半導体ウェーハを示した側面図である。It is the side view which showed the semiconductor wafer on which the foreign material was laminated | stacked. 装備により半導体ウェーハに異物が形成積層される場面を描写した図である。It is the figure which depicted the scene where a foreign material was formed and laminated on a semiconductor wafer by equipment. 図７a〜図７eは、従来の湿式蝕刻による窒化膜の除去工程を示す図である。7a to 7e are views showing a conventional nitride film removing process by wet etching. 図8a〜図8eは、従来の乾式蝕刻によるポリシリコン膜の除去工程を示す図である。8a to 8e are diagrams illustrating a conventional process of removing a polysilicon film by dry etching. 従来の電極を用いた半導体ウェーハの乾式蝕刻装置を示す図である。It is a figure which shows the dry-type etching apparatus of the semiconductor wafer using the conventional electrode.

Claims (2)

プラズマを形成させて半導体ウェーハの端部の異物を除去する第1及び第2一対の半導体ウェーハ乾式蝕刻用電極において、
前記第1電極は、前記半導体ウェーハ端部の上面部、下面部のいずれか一方と対向する環状の第1突出部及び第1平坦部を備え、前記第2電極は、前記半導体ウェーハ端部の上面部、下面部の他方と対向し、前記第1突出部及び第1平坦部と同一寸法で形成された第2突出部及び第2平坦部を備えていることを特徴とする半導体ウェーハ乾式蝕刻用電極。 In the first and second pair of semiconductor wafer dry etching electrodes that form plasma and remove foreign matter at the edge of the semiconductor wafer,
The first electrode includes an annular first projecting portion and a first flat portion facing either one of an upper surface portion and a lower surface portion of the semiconductor wafer end portion, and the second electrode is formed on the semiconductor wafer end portion. Semiconductor wafer dry etching, comprising a second protrusion and a second flat part facing the other of the upper surface part and the lower surface part and having the same dimensions as the first protrusion and the first flat part Electrode. 前記第1電極の前記半導体ウェーハと対向する面の中心部から突出部の内径に至る部位に絶縁体が塗布され、又は絶縁膜が付着されたことを特徴とする請求項1記載の半導体ウェーハ乾式蝕刻用電極。   2. The semiconductor wafer dry process according to claim 1, wherein an insulator is applied to an area extending from the center of the surface of the first electrode facing the semiconductor wafer to the inner diameter of the protrusion, or an insulating film is attached. Etching electrode.
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