TW200304183A - Electrode for dry etching a semiconductor wafer - Google Patents
Electrode for dry etching a semiconductor wafer Download PDFInfo
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- TW200304183A TW200304183A TW092104346A TW92104346A TW200304183A TW 200304183 A TW200304183 A TW 200304183A TW 092104346 A TW092104346 A TW 092104346A TW 92104346 A TW92104346 A TW 92104346A TW 200304183 A TW200304183 A TW 200304183A
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- electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000001312 dry etching Methods 0.000 title claims abstract description 22
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 77
- 210000002381 plasma Anatomy 0.000 description 16
- 238000005530 etching Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 9
- 239000000126 substance Substances 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 239000012495 reaction gas Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000002981 blocking agent Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000005672 electromagnetic field Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000035508 accumulation Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000003504 photosensitizing agent Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- -1 CH2F2 nitride Chemical class 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- GWFXMCXJFOEMNQ-UHFFFAOYSA-N [O].O=[N] Chemical compound [O].O=[N] GWFXMCXJFOEMNQ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32541—Shape
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
200304183 五、發明說明200304183 V. Description of Invention
【發明所屬之技術領域】 本發明係與半導體晶圓 用電漿以供製造積體電路晶 物之半導體晶圓乾式餘刻用 之乾式蝕刻有關，尤指一種使 片時移除沉積於晶圓周緣之異 電極。 【先前技術】[Technical field to which the invention belongs] The present invention relates to dry etching of plasma for semiconductor wafers for dry etching of semiconductor wafers for manufacturing integrated circuit crystals, and more particularly, to remove and deposit on the wafer periphery when the wafer is removed. Different electrodes. [Prior art]
第5圖所示為熟悉此行業技術之人員共知者，即：製 作南度集積之半導體晶片時，半導體晶圓丨〇 〇之周緣必會 形成如聚矽化物層、氮化物層、及金屬層等之若干沉積層 110、120。而且，如第6圖所示，傳送（或利用機具設備 2 0 0運送）該半導體晶圓100的過程中，由於晶圓周緣之沉 積層因可能發生碎裂而產生小顆粒進入晶片中央區域，導 致積體電路晶片受到污損。Figure 5 shows what everyone who is familiar with the technology of this industry knows, that is, when making semiconductor wafers of Nando accumulation, the periphery of the semiconductor wafer, such as polysilicide layer, nitride layer, and metal, must be formed. Layers, such as a number of deposited layers 110, 120. In addition, as shown in FIG. 6, during the process of transferring (or transporting by using equipment 200) the semiconductor wafer 100, small particles may enter the central region of the wafer due to the possible fragmentation of the deposited layer on the periphery of the wafer. As a result, the integrated circuit chip is damaged.
其次’因為近來半導體晶片的閘電極材料已經從矽化 鎢改成鎢.，並且電容器的絕緣層也從原先的氧—氮-氧 (ONO，oxide-nitride-oxide)結構改變為氧化鈕，加以又 採用一種有機基底之抗反射塗層（anti—ref lective coating，以下簡稱心〇，一種如Si〇N之無機ARC層以形成 纖細的光阻圖案，以及做為一種障礙金屬層之鈦及氮化鈦 層’因此’依前法製作時這些物質也會沾污半導體晶圓。 思即’製作半導體晶圓;[〇 〇時，上述物質係扮演了一 個污損晶圓的粒子源，特別是當晶圓直徑從200 mm擴大為 3 0 0 mm時，由於晶圓周緣的半徑也變大，所以半導體晶圓 被粒子沾污的情況也更加嚴重。Secondly, because the gate electrode material of semiconductor wafers has been changed from tungsten silicide to tungsten recently, and the insulating layer of the capacitor has also changed from the original oxygen-nitrogen-oxide (ONO) structure to an oxide button, An organic-based anti-reflective coating (hereinafter referred to as Xin 0), an inorganic ARC layer such as SiON to form a thin photoresist pattern, and titanium and nitride as a barrier metal layer These materials will also contaminate semiconductor wafers when the titanium layer is' produced 'according to the previous method. Think of' making semiconductor wafers; [00〇, the above substances act as a source of particles that foul the wafer, especially when When the wafer diameter is increased from 200 mm to 300 mm, since the radius of the wafer periphery also becomes larger, the situation of semiconductor wafers being contaminated by particles is also more serious.
200304183200304183
五、發明說明（2) 因鑒於這些蓄積在半導體晶圓1〇〇周緣的物質會降低 半導體晶片的產能與品質，所以有必要加以徹底清除。一 前此已有若干供以清除上述蓄積物質的傳統方法可以 應用。以下係以一種如第7a至7e圖所示包括五個步驟用以 消除氮化物層之濕式蝕刻法為例說明之： i ·利用一電漿沉積裝置在矽半導體晶圓丨〇()上之氮化 物層101表面形成一層氧化物層1〇2(第73圖）； i i ·塗佈感光劑於該氧化物層1 〇 2以形成一阻光層 103，移除該阻光層1〇3位於矽半導體晶圓1〇〇之周緣&分 以便使該處的氧化物層102曝露於外（第7b圖）； iii·利用化學溶液（NHFJHF)以一濕式蝕刻裝置移除 曝光的氧化物層102部分（第7c圖）； iv.先以一乾式蝕刻裝置移除覆蓋在該氧化物層1〇2 上面的阻光層103，次以化學溶液（H2S〇4/H2〇2)利用一清洗 裝置清洗殘餘的阻光劑103(第7d圖）；及 ν·利用一濕式蝕刻裝置以熱濃磷酸（h3p〇4)移除位於 該半導體晶圓100周緣曝露於外之該氮化物層1〇1(第化 圖）。 以上所述氮化物層的濕式蝕刻程序至為繁複，需要各 種不同的設備來執行多項步驟，包括：氧化物層的沉積、 阻光劑的塗佈、移除該阻光劑的乾式蝕刻、移除該氧化物 層的濕式蝕刻、殘餘阻光劑的徹底移除、清洗步驟、以及 該氮化物層的濕式蝕刻動作。 另一方面，以下再以一種如第以至“圖所示也包括五V. Explanation of the invention (2) In view of the fact that these substances accumulated on the periphery of the semiconductor wafer 100 will reduce the productivity and quality of the semiconductor wafer, it is necessary to completely remove them. A number of conventional methods have previously been applied to remove such accumulations. The following is an example of a wet etching method including five steps to remove nitride layers as shown in Figures 7a to 7e: i. Using a plasma deposition device on a silicon semiconductor wafer An oxide layer 102 is formed on the surface of the nitride layer 101 (Fig. 73); ii. A photosensitizer is coated on the oxide layer 102 to form a light blocking layer 103, and the light blocking layer 1 is removed. 3 is located on the periphery of the silicon semiconductor wafer 100 in order to expose the oxide layer 102 there (Fig. 7b); iii. Using a chemical solution (NHFJHF) to remove the exposed Part of the oxide layer 102 (FIG. 7c); iv. First remove the light blocking layer 103 over the oxide layer 102 with a dry etching device, and then use a chemical solution (H2S〇4 / H2〇2) The remaining photoresist 103 was cleaned by a cleaning device (Fig. 7d); and ν · The wet exposed etching device was used to remove the nitrogen exposed on the periphery of the semiconductor wafer 100 with hot concentrated phosphoric acid (h3p〇4) Compound layer 101 (see figure). The wet etching process of the nitride layer described above is complicated and requires various equipment to perform multiple steps, including: deposition of an oxide layer, coating of a light-blocking agent, dry etching to remove the light-blocking agent, The wet etching to remove the oxide layer, the complete removal of the residual light blocking agent, the cleaning step, and the wet etching action of the nitride layer. On the other hand, the following uses a
200304183 五、發明說明（3) 個步驟用以消除聚矽化物層之乾式蝕刻法為例說明之· i·利用一電漿沉積裴置在矽半導體晶圓100上之聚 化物層104表面形成該氧化物層1〇2(第仏圖）； i i ·塗佈感光劑於該氧化物層1 〇 2以形成一阻光； 103，移除該阻光層103位於矽半導體晶圓1〇〇之周緣^ 以便使該處的氧化物層1 0 2曝露於外（第8 b圖）； i i i ·利用化學溶液（NHFJHF)以一濕式蝕刻裝置移除 曝光的氧化物層102部分（第8c圖）； 、 iv.先以一乾式蝕刻裝置移除覆蓋在該氧化物層1〇2 上面的阻光層103，次以化學溶液（H2S〇4/H2〇2)利用一清洗 裝置清洗殘餘的阻光劑103 (第8d圖）；及 彳 V.使用傳統乾式蝕刻裝置移除位在該半導體晶圓1〇〇 周緣且曝露於外之該聚矽化物層104(第8e圖）。 此種聚矽化物層之乾式蝕刻作業，其程序之繁複實不 亞於前述氮化物層之濕式蝕刻手續，也需要各種不同的設 備來執行多項步驟，包括：氧化物層的沉積、阻光劑的塗 佈、移除該阻光劑的乾式蝕刻、移除該氧化物層的濕式蝕 刻、清洗步驟、以及該聚矽化物層的乾式蝕刻動作。 然而’在利用傳統的乾式蝕刻裝置進行移除半導體晶 圓周緣的聚矽化物層時，卻只有該半導體晶圓周緣上表^ 的聚矽化物層能夠完全清除，底面或侧面的部分無法充分 移除或頂多僅能做到部分移除。 再者，應用於程序中以形成圖案於該半導體晶圓表面 之不同傳統蝕刻裝置因只能分別使用於單一步驟，亦即，200304183 V. Description of the invention (3) The dry etching method for removing the polysilicide layer is described as an example. I. A plasma is used to deposit the polymer layer 104 on the silicon semiconductor wafer 100 to form the surface. Oxide layer 102 (picture ii); ii. Coating a photosensitizer on the oxide layer 102 to form a light-blocking layer; 103, removing the light-blocking layer 103 located on a silicon semiconductor wafer 100 Perimeter ^ in order to expose the oxide layer 102 there (Fig. 8b); iii. Using a chemical solution (NHFJHF) to remove the exposed oxide layer 102 portion (Fig. 8c) ); Iv. First remove the light blocking layer 103 covering the oxide layer 10 with a dry etching device, and then use a cleaning device to clean the remaining resistance with a chemical solution (H2S〇4 / H2〇2). Photoresist 103 (Figure 8d); and 彳 V. The conventional polysilicon layer 104 located on the periphery of the semiconductor wafer 100 and exposed is removed using a conventional dry etching device (Figure 8e). The dry etching operation of the polysilicide layer is as complicated as the wet etching procedure of the aforementioned nitride layer. It also requires various equipment to perform multiple steps, including: oxide layer deposition, light blocking Coating, dry etching to remove the light blocking agent, wet etching to remove the oxide layer, cleaning step, and dry etching of the polysilicide layer. However, when using a conventional dry etching device to remove the polysilicide layer on the periphery of a semiconductor wafer, only the polysilicide layer on the periphery of the semiconductor wafer can be completely removed, and the bottom or side portions cannot be fully moved. Divide or at most only partially remove. Furthermore, different traditional etching devices used in the process to form a pattern on the surface of the semiconductor wafer can only be used in a single step, that is,
第8頁 200304183 五、發明說明（4) 每一種钱刻裝置僅能移除某一特定異物，所以其中任一種 蝕刻裝置皆無法滿足各種物質的需要。Page 8 200304183 V. Description of the invention (4) Each type of money engraving device can only remove a specific foreign object, so any of the etching devices cannot meet the needs of various substances.
如第9圖所示，一用以形成細微電路圖案於半導體晶 片上之傳統乾式蝕刻裝置係在某一反應氣體中一扁平狀第 一電極300與另一扁平狀第二電極300’之間形成一電場， 且該乾式蝕刻裝置產生電漿（等離子體）進入該半導體晶圓 100之上表面以便在該半導體晶圓1〇〇之上表面10〇3進行蝕 刻而形成一沉積層及一細微圖案l〇3a。圖中，位於該半導 體晶圓100周緣的沉積層已被移除，而標號400表示一無線 電信號（RF )發生器，標號5 〇 〇則代表一互相匹配的電路。 該傳統乾式蝕刻裝置中，因為該半導體晶圓1〇〇係架 設於電極3 0 0 ’之上進行蝕刻，該半導體晶圓1 〇 〇的側面 1 0 0 b與底面1 0 〇 c均未被蝕刻到，所以，該半導體晶圓丨〇 〇 的側面100b與底面100c皆無法移除。 【發明内容】As shown in FIG. 9, a conventional dry etching device for forming a fine circuit pattern on a semiconductor wafer is formed between a flat first electrode 300 and another flat second electrode 300 ′ in a certain reaction gas. An electric field, and the dry etching device generates plasma (plasma) to enter the upper surface of the semiconductor wafer 100 so as to etch the upper surface of the semiconductor wafer 100 to form a deposition layer and a fine pattern l03a. In the figure, the deposited layer on the periphery of the semiconductor wafer 100 has been removed, and reference numeral 400 represents a radio frequency signal (RF) generator, and reference numeral 500 represents a mutually matched circuit. In the conventional dry etching apparatus, since the semiconductor wafer 100 is mounted on the electrode 300 ′ for etching, the side surface 100 b and the bottom surface 100 c of the semiconductor wafer 100 are not etched. It is etched so that neither the side surface 100b nor the bottom surface 100c of the semiconductor wafer can be removed. [Summary of the Invention]
鑒於上述缺點，本:發明之目標在於提供一種利用電聚 以乾式餘刻半導體晶圓之電極，其係可有效地移除沉積於 一半導體晶圓之周緣下表面、側表面、與上表面之異物且 不致對該半導體晶圓造成任何傷害者。 只要採用本發明之電極以乾式蝕刻半導體晶圓方式 達成上述或其他進一步的目標，實無太大困難。該電極 一成對出現之電極組，包括有利用電漿以移除半導體曰^ 之周緣異物之第一與第二電極。該第一電極内含一二 ^ 一届In view of the above disadvantages, the present invention aims to provide an electrode for dry-etching a semiconductor wafer using electropolymerization, which can effectively remove the lower surface, side surface, and upper surface of a semiconductor wafer deposited on the periphery. Foreign matter does not cause any harm to the semiconductor wafer. As long as the electrode of the present invention is used to dry-etch a semiconductor wafer to achieve the above or other further objectives, there is not much difficulty. The electrodes are a pair of electrode groups, which include first and second electrodes that use a plasma to remove foreign matter on the periphery of the semiconductor. The first electrode contains one or two ^ one session
第9頁 200304183 五、發明說明（5) = 導;;=緣-面之環狀凸緣， 體晶圓周緣另-面：環㈡千：：；二小相當於該半導 小一致。 /、Τ$弟一與第二凸緣大 又該第一電極上表面以該第一凸络 最好沉積形成一層 緣為界之内部區域 ’絶緣材料或貼設一絕緣居 【實施方式] 第1圖係本發明半導體晶圓乾式蝕刻 面圖。如圖所示，本發明之電極為—成二电極之部分斷 包括-第-電極1()與一第二電極2()。肖第—应組’ 10/20係一產生電漿（等離子體）裝 銘、一电極 半導體晶圓周緣之異物者。 以供移除沉積於- Φ 本案中，雖然該第一電極10做為陽極而第二電極2〇做 為陰極使用，但反之亦無不可。該第—電極10係呈扁平圓 盤狀，外觀與一般傳統電極相似，惟其底面具有一環狀之 第一凸緣10a及一設於該第一凸緣l〇a與該第一電極1〇周緣 間之進氣孔10b。該進氣孔10b係供引導一種用以產生電聚 之反應氣體，使之進入一内部設置該第一與第二電極 10/20之真空室（未示）、。 該第二電極20亦呈扁平圓盤狀，具有與該第一電極10 相同的直徑。又，該第二電極20中央部設有一開口 20a， 而周緣與該開口 20a之間形成一大小與該第一凸緣l〇a相當 之環狀第二凸緣20b。Page 9 200304183 V. Description of the invention (5) = guide;; = edge-to-face annular flange, the other side of the body wafer periphery: ring ㈡1000 ::; the second small is equivalent to the semi-conductor. /, The first and second flanges are large, and the upper surface of the first electrode is bounded by the first convexity and preferably formed to form a layer bounded by an inner region 'insulating material or an insulating residence is attached [Embodiment] No. FIG. 1 is a dry etching surface view of a semiconductor wafer according to the present invention. As shown in the figure, the electrode of the present invention is-partly broken into two electrodes, including-a first electrode 1 () and a second electrode 2 (). Xiao Di—Ying Group ’10/20 is a plasma (plasma) inscription, an electrode, and a foreign object on the periphery of a semiconductor wafer. For removal and deposition in-Φ In this case, although the first electrode 10 is used as the anode and the second electrode 20 is used as the cathode, the reverse is not necessary. The first electrode 10 is in the shape of a flat disk, and its appearance is similar to that of a conventional electrode, except that the bottom electrode has a ring-shaped first flange 10a and a first flange 10a and the first electrode 10. Air holes 10b between the edges. The air inlet hole 10b is used to guide a reaction gas for generating electricity to enter a vacuum chamber (not shown), in which the first and second electrodes 10/20 are disposed. The second electrode 20 also has a flat disk shape and has the same diameter as the first electrode 10. In addition, an opening 20a is provided at a central portion of the second electrode 20, and a ring-shaped second flange 20b is formed between the peripheral edge and the opening 20a in a size equivalent to the first flange 10a.
第10頁 200304183Page 10 200304183
一電極2 0之 一扁平部1 0 c 該第一電極1 0之第一凸緣1 〇 a外侧與該第 第二凸緣2Ob外側之平坦區域分別定義為_第 與一第二扁平部20c。 一絕緣體或絕緣層1 1係沉積或貼附於 底面之靠内區域，用以避免當RF電力施加於节第一 電極1 0/20之間時兩電極間發生電場或電磁場二 為聚醯亞胺（poly imide)、鐵氟龍（Tefl0n )、 /、 可 或陶磁等。 /、石英、 第2與第3圖顯示採用本發明半導體晶圓乾式蝕 带 極時半導體晶圓之蝕刻狀態。以下茲參閱該兩圖 = 發明之第一及第二電極10/20與該半導體晶圓3〇 / 情況予以申述之。 生领 如第2圖所示，該半導體晶圓3〇係利用一靜電夾盤 而插設於該做為陽極之第一電極丨〇及做為陰極之第二電極 20之間。該靜電夾盤4〇係進入該第二電極2〇之開口 後 停留於一稍低位置，藉使該半導體晶圓3 〇之周緣下表面 30c得與該第二電極20之第二凸緣2 〇b形成接觸狀態。 此時若經過該第一電極1〇之進氣孔1〇b導入一種反應 氣體並由該RF發生器50提供電力給該第二電極2〇時，則“該 第^電極10之第一凸緣1()a與第一扁平部1〇c及該第二電 極20之第二凸緣2〇b與第二扁平部2〇c所涵蓋的範圍内將$形 成一電場或電磁場，而該反應氣體隨即在該第一凸緣丨〇 a 與第二凸緣20b之間及該第一扁平部1〇c與第二扁平部2〇c 之間產生兩種強度不同的電漿。One of the flat portions 1 0 c of one electrode 2 0 The flat areas outside the first flange 10 a of the first electrode 10 and outside the second flange 2Ob are defined as the first and second flat portions 20 c, respectively. . An insulator or insulation layer 11 is deposited or attached to the inner area of the bottom surface to avoid the occurrence of an electric or electromagnetic field between the two electrodes when RF power is applied between the first electrodes 10/20 of the node. Amine (poly imide), Teflon (Tefl0n), /, Ke or ceramics. /, Quartz, Figures 2 and 3 show the etching state of the semiconductor wafer when the semiconductor wafer dry-etching strip electrode of the present invention is used. In the following, please refer to these two figures = the first and second electrodes 10/20 of the invention and the semiconductor wafer 30 / representation. As shown in FIG. 2, the semiconductor wafer 30 is interposed between the first electrode 20 serving as an anode and the second electrode 20 serving as a cathode using an electrostatic chuck. The electrostatic chuck 40 enters the opening of the second electrode 20 and stays at a slightly lower position, so that the lower surface 30c of the peripheral edge of the semiconductor wafer 30 and the second flange 2 of the second electrode 20 〇b forms a contact state. At this time, if a reactive gas is introduced through the air inlet hole 10b of the first electrode 10 and the RF generator 50 supplies power to the second electrode 20, "the first protrusion of the third electrode 10 An electric field or an electromagnetic field will be formed within the range covered by the edge 1 () a and the first flat portion 10c and the second flange 20b and the second flat portion 20c of the second electrode 20, and the The reaction gas then generates two kinds of plasmas having different strengths between the first flange 10a and the second flange 20b and between the first flat portion 10c and the second flat portion 20c.
200304183 五、發明說明（7) 本案中，電漿係沿該第一凸緣10a與該第二凸緣2〇b之 寬度形成，此寬度相當於該半導體晶圓3 0中準備接受钱刻 之周緣寬度B(B區）。因此，該半導體晶圓3〇中具有細微電 路圖案31的Α區將不會受到該電漿的影響，而該半導體晶 圓30的侧表面30b則會被形成於該第一扁平部1〇c與該第二 扁平部2 0 c之間的電漿C所蝕刻。 因為該半導體晶圓30的底面係與該第二電極2〇的第二 凸緣20b上表面接觸，所以，反應離子蝕刻RIE (Reactive200304183 V. Description of the invention (7) In this case, the plasma is formed along the width of the first flange 10a and the second flange 20b, which is equivalent to the semiconductor wafer 30 ready to receive money. Perimeter width B (B area). Therefore, the A region having the fine circuit pattern 31 in the semiconductor wafer 30 will not be affected by the plasma, and the side surface 30b of the semiconductor wafer 30 will be formed on the first flat portion 10c. The plasma C is etched from the second flat portion 20 c. Since the bottom surface of the semiconductor wafer 30 is in contact with the upper surface of the second flange 20b of the second electrode 20, reactive ion etching (Reactive)
Ion Etching)主要是在該半導體晶圓3〇的上表面3〇a與侧 表面3 0 b進行。 其次，由於該絕緣層丨丨係沉積（或貼設）於該第一電極 10之上表面，所以，A區内部不會形成任何電場或電磁 場，可防止在該區域内產生電漿以改善蝕刻效率。 此處的標號6 〇代表一匹配電路。 如第3圖所示，該靜電夾盤40係可通過該第二電極的 開口 2〇a而上升，藉使該半導體晶圓30的周緣上表面3〇ai) 住該第:電極10的第一凸緣1〇a表面。今經由該第一電極 lj的進氣孔l〇b導入反應氣體並由該以發生器5〇提供電力Ion Etching) is mainly performed on the upper surface 30a and the side surface 30b of the semiconductor wafer 30. Secondly, since the insulating layer is deposited (or attached) on the upper surface of the first electrode 10, no electric or electromagnetic field will be formed inside the area A, which can prevent the generation of plasma in this area to improve the etching. effectiveness. The reference numeral 6 0 here represents a matching circuit. As shown in FIG. 3, the electrostatic chuck 40 can be raised through the opening 20a of the second electrode, and the upper surface of the peripheral edge of the semiconductor wafer 30 can be held by the upper surface of the second electrode: A flange 10a surface. The reaction gas is introduced through the air inlet hole 10b of the first electrode lj and is supplied with electricity by the generator 50.
拄Ϊ將=緣10a與第二凸緣20b之間隨即產生電漿。此 刻動作主要是在該半導體晶圓30的下表面 ^篦4 薛_ b進行，藉以移除沉積在β區的異物。 直Λ不：的斷®，本發明的電極即設置其間。該 進：:—用以導入可供產生電漿之反應氣體使 °" 極10與第二電極2 0之吹管71 ; —供送入該年电 Plasma is generated between the edge 10a and the second flange 20b. The action at this moment is mainly performed on the lower surface of the semiconductor wafer 30 ^ 篦 4 Xue_b, thereby removing the foreign matter deposited in the β region. Straight Λ: The broken electrode, the electrode of the present invention is disposed therebetween. The feed ::-used to introduce the reactive gas that can be used to generate the plasma so that the electrode 10 and the second electrode 20 0 blow tube 71;-for the year
200304183200304183
導體，圓30之埠口70a ; 一用以排放該半導體晶圓3〇蝕刻 後廢氣的排氣口 70b ;及用以上下移動半導體晶圓3〇之該 靜電夾盤40。A conductor, a port 30a of a circle 30; an exhaust port 70b for exhausting the exhaust gas after the semiconductor wafer 30 is etched; and the electrostatic chuck 40 for moving the semiconductor wafer 30 up and down.
银刻之前置作業係先經由埠口 7〇a將半導體晶圓3〇送 入該真空室70且置於該靜電夾盤40之上，然後在反應氣體 的氛圍中，令該RF發生器5〇透過第二電極2〇提供電壓。此 時，該半導體晶圓30之中心部位上表面受到該第一電極i 〇 之絕緣層11保護，而電漿僅發生在第一凸緣1〇a與第二凸 緣20b之間及第一扁平部1〇c與第二扁平部2〇c之間，該半 ，體f圓30周緣部位之上、下、與侧表面3〇a/3〇c/3〇b乃 得依前述方式進行蝕刻。 與傳統情況相同，於實施蝕刻時該半導體晶圓3〇上的 八物被移除，而反應氣體則經由該排氣口 7〇b被排出。 表1羅列使用本發明電極對半導體晶圓實施蝕刻之各 種反應氣體與使用對應反應氣體而被移除之異物。Prior to the silver engraving operation, the semiconductor wafer 30 is firstly sent into the vacuum chamber 70 through the port 70a and placed on the electrostatic chuck 40, and then the RF generator is made in a reactive gas atmosphere. 50 provides a voltage through the second electrode 20. At this time, the upper surface of the center portion of the semiconductor wafer 30 is protected by the insulating layer 11 of the first electrode i 0, and the plasma only occurs between the first flange 10a and the second flange 20b and the first Between the flattened portion 10c and the second flattened portion 20c, the half of the body f circle 30 above, below, and the side surface 30a must be carried out in the manner described above. Etching. As in the conventional case, the eight objects on the semiconductor wafer 30 are removed when the etching is performed, and the reaction gas is discharged through the exhaust port 70b. Table 1 lists the various reaction gases for etching semiconductor wafers using the electrodes of the present invention and the foreign substances removed using the corresponding reaction gases.
200304183 五、發明說明（9) 表1 材 質 反應氣艘 有機 ARC (Si〇N^~~ CF4, SFg 無機 ARC (CXSW) CF4, 〇2 氣化物層（Si〇2) CF4, CHF3, C4Fs, C2Ffi, Ar, 〇2, CH2F2 氮化物層（Sl3N4；) CF4, SF6, CHF3, Ar, 02 聚矽化物層（Si) HBr, Cl2, CC14, SF6, O2 矽化鎢（WSix) ^~— SF6, Ch 鎢（W) SF6, CF4, Ar, O2 鋁（A1) 〜 CI2, ecu, bci3 銅（Cu) — Cl2 氣化輕（Ta〇2) SF6, CI2, cf4 鈕（Ta〇N) sf6, ci2, cf4 鈥（Ti) — cf4i sf6 發化妖（TiSix) sf6, cf4, 〇2 S 0 G, [RxSiOySi〇2]n H(Si03/2)n ’ sf6, cf4, 〇2 如前所述，傳統蝕刻裝置通常只能移除某種物質， 即，使用一種濕式蝕刻裝置移除半導體晶圓的氮化物声」 外，可能還需要-種乾式㈣裝置在晶圓之上形成細^ 電路圖案。如此，一個餘刻步㈣冑要一種特定的银刻肩 置來完成，使付整個蝕刻製程變成非常複雜。 而且，以傳統蝕刻裝置的電極結構來看，口 面與側表面的異物可被移：二於] 表面部分則無能為力。 然而，如果改採本發明的電極以移除表丨 時，只須循序供應對應於各種不同村曾>/Λ w *之適當反應氣骨200304183 V. Description of the invention (9) Table 1 Material reaction gas organic ARC (Si〇N ^ ~~ CF4, SFg inorganic ARC (CXSW) CF4, 〇2 gas layer (Si〇2) CF4, CHF3, C4Fs, C2Ffi , Ar, 〇2, CH2F2 nitride layer (Sl3N4;) CF4, SF6, CHF3, Ar, 02 polysilicon layer (Si) HBr, Cl2, CC14, SF6, O2 tungsten silicide (WSix) ^ ~ — SF6, Ch Tungsten (W) SF6, CF4, Ar, O2 Aluminum (A1) ~ CI2, ecu, bci3 Copper (Cu) — Cl2 Gasified light (Ta〇2) SF6, CI2, cf4 Button (Ta〇N) sf6, ci2, cf4 '(Ti) — cf4i sf6 TiSix sf6, cf4, 〇2 S 0 G, [RxSiOySi〇2] n H (Si03 / 2) n' sf6, cf4, 〇2 As mentioned before, traditional Etching devices usually can only remove certain substances, that is, using a wet etching device to remove nitride sound from semiconductor wafers. In addition, a dry-type device may be required to form a thin circuit pattern on the wafer. In this way, a special step of silver engraving is required to complete a remaining step, which makes the entire etching process very complicated. Moreover, from the electrode structure of the traditional etching device, foreign matter on the mouth surface and the side surface can be removed. : Two on] the surface portion is powerless However, if the shift to the electrode of the present invention to remove Shu table, corresponding to only sequentially supply the village had various > / Λ w * The reaction of the appropriate air-bone.
200304183 五、發明說明（10) 可，7G全不需要額外設備，故能大幅簡化製程。200304183 V. Description of the invention (10) Yes, 7G does not require additional equipment, so it can greatly simplify the manufacturing process.
上轰ί者二Ϊ用本發明的電極時，除了半導體晶圓之A 響。因此，得以在不損傷半導體晶圓中央表：ς:聚影 電路圖案的條件下，提昇蝕刻效率。、 /成細微 、上對於‘悉本技術領域的人士而言，太狄 :念當可運用於其他不同的方式，故：明的基 例僅供例證而非用以限制其實施範圍者，:j k不之實施 又甲明專利乾圍各申請項之節制。 < 文 工業應用 從以上說明可 體晶圓用電極係可 側表面、及下表面 備或步驟，故可葬When using the electrode of the present invention, except for the A ring of a semiconductor wafer. Therefore, it is possible to improve the etching efficiency without damaging the central table of the semiconductor wafer. For those who are aware of this technical field, Taidi: Niandang can be used in other different ways, so: the basic examples are for illustration only and not to limit the scope of their implementation ,: The implementation of jk does not control the application of each patent. < Industrial applications From the above description, the electrode system for bulk wafers can be prepared on the side surface and the bottom surface, so it can be buried.
=知，本#明所提供之乾式餘刻半導 矛、》儿積於一半導體晶圓周緣上表面、 •v ^物且完全不f要其他任何多餘之設 200304183 圖式簡單說明 為使本發明之結構、特徵、及效用等更 $ •，以下為配合實施例而提供之相關圖式簡要說明，其 面圖第丨圖係本發明半導體晶圓乾式物電極之部分斷 第2圖顯示採用本發明半導體晶圓乾式蝕 一半導體晶圓之上表面與側面之蝕刻狀態；^ 第3圖顯示採用本發明半導體^ 一半導體晶圓之下表面與側面之餘刻回狀乾態式姓刻用電極時 第4圖係一設有本發明電極之乾式蝕刻裝置斷面圖； 第5圖係一表面沉積多個層次之半導體晶圓侧視 第6圖顯示因設備運轉導致半導體晶圓表面沉物 之現象； 谓兵獨 第7a至7e圖係顯示利用傳統濕式蝕刻法以移除一 物層之過程變化斷面圖； ^ 第8a至8e圖係顯示利用傳統乾式蝕刻法以移除一 化物層之過程變化斷面圖；及 Λ 第9圖係利用傳統電極以蝕刻半導體晶圓之示意圖。 【圖式標號說明】 10--------電極 l〇a-------環狀之第一凸緣 1 Ob-------進氣孔 10c 弟一爲平部= 知 ， 本 # The dry type semi-conducting semi-conductive spear provided in this article is stored on the upper surface of the periphery of a semiconductor wafer. It is not necessary to have any other extra settings. The structure, features, and utility of the invention are more detailed. • The following is a brief description of the related drawings provided in conjunction with the embodiments. The top view is the part of the semiconductor wafer dry type electrode of the present invention. The second figure shows the use of The semiconductor wafer of the present invention is dry-etched on an upper surface and a side surface of a semiconductor wafer; FIG. 3 shows the use of the semiconductor of the present invention. In the case of electrodes, FIG. 4 is a cross-sectional view of a dry etching device provided with electrodes of the present invention; FIG. 5 is a side view of a semiconductor wafer with multiple layers deposited on the surface; FIG. Phenomenon; Figures 7a to 7e show cross-sections of process changes using traditional wet etching to remove a layer; ^ Figures 8a to 8e show traditional dry etching to remove one compound Layer over Change in cross-sectional view; FIG. 9 and Λ using a conventional electrode-based schematic diagram of the semiconductor wafer to etching. [Illustration of figure number] 10 -------- electrode 10a ------- first annular flange 1 Ob ------- air inlet 10c unit
200304183 圖式簡單說明 11--------絕緣層 20 第二電極 · 20a-------開口 20b — -----環狀第二凸緣 ^ 20c-------第二扁平部 30 --------半導體晶圓 30a-------半導體晶圓的上表面 3 0b 半導體晶圓的側表面 30c-------半導體晶圓的下表面 31 --------電路圖案 ⑩ 40--------靜電夾盤 50--------RF發生器 60---------配電路 70 --------真空室 70a-------半導體晶圓的埠口 70b-------排氣口 71 --------吹管 100-------半導體晶圓 100a------半導體晶圓的上表面 _ 100b------半導體晶圓的側面 100c------底面 101 -------氮化物層 102 -------氧化物層 103 -------阻光層200304183 Brief description of the diagram 11 -------- Insulating layer 20 Second electrode · 20a ------- Opening 20b------ Ring-shaped second flange ^ 20c ----- --Second flat part 30 -------- Semiconductor wafer 30a ------- Surface of semiconductor wafer 30b Side surface of semiconductor wafer 30c ------- Semiconductor wafer Round lower surface 31 -------- Circuit pattern⑩ 40 -------- Electrostatic chuck 50 -------- RF generator 60 --------- With circuit 70 -------- Vacuum chamber 70a ------- Port 70b of semiconductor wafer ------- Exhaust port 71 -------- Blow pipe 100- ------ Semiconductor wafer 100a ------ Top surface of semiconductor wafer_ 100b ------ Side surface 100c of semiconductor wafer ------ Bottom surface 101 ------ -Nitride layer 102 ------- Oxide layer 103 ------- Light blocking layer
第17頁 200304183Page 17 200304183
第18頁Page 18
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2002-0011395A KR100442194B1 (en) | 2002-03-04 | 2002-03-04 | Electrodes For Dry Etching Of Wafer |
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| TW200304183A true TW200304183A (en) | 2003-09-16 |
| TWI230415B TWI230415B (en) | 2005-04-01 |
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| TW092104346A TWI230415B (en) | 2002-03-04 | 2003-03-03 | Electrode for dry etching a semiconductor wafer |
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| JP (1) | JP4152895B2 (en) |
| KR (1) | KR100442194B1 (en) |
| AU (1) | AU2002253689A1 (en) |
| TW (1) | TWI230415B (en) |
| WO (1) | WO2003075333A1 (en) |
Families Citing this family (42)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100447891B1 (en) * | 2002-03-04 | 2004-09-08 | 강효상 | Dry Etching Method For Wafer |
| JP4122004B2 (en) * | 2003-05-12 | 2008-07-23 | 株式会社ソスル | Plasma etching chamber and plasma etching system using the same |
| US7404874B2 (en) | 2004-06-28 | 2008-07-29 | International Business Machines Corporation | Method and apparatus for treating wafer edge region with toroidal plasma |
| US7090782B1 (en) | 2004-09-03 | 2006-08-15 | Lam Research Corporation | Etch with uniformity control |
| KR100611727B1 (en) * | 2005-06-24 | 2006-08-10 | 주식회사 씨싸이언스 | Electrodes for dry etching of wafer and dry etching chamber |
| KR101218114B1 (en) * | 2005-08-04 | 2013-01-18 | 주성엔지니어링(주) | Etching apparatus using the plasma |
| KR100727469B1 (en) * | 2005-08-09 | 2007-06-13 | 세메스 주식회사 | etching system for plasma |
| US20070068623A1 (en) * | 2005-09-27 | 2007-03-29 | Yunsang Kim | Apparatus for the removal of a set of byproducts from a substrate edge and methods therefor |
| US8475624B2 (en) * | 2005-09-27 | 2013-07-02 | Lam Research Corporation | Method and system for distributing gas for a bevel edge etcher |
| US7909960B2 (en) * | 2005-09-27 | 2011-03-22 | Lam Research Corporation | Apparatus and methods to remove films on bevel edge and backside of wafer |
| CN1978351A (en) * | 2005-12-02 | 2007-06-13 | 鸿富锦精密工业（深圳）有限公司 | Device and method for removing mould cavity protective membrane |
| US8012306B2 (en) * | 2006-02-15 | 2011-09-06 | Lam Research Corporation | Plasma processing reactor with multiple capacitive and inductive power sources |
| US8911590B2 (en) * | 2006-02-27 | 2014-12-16 | Lam Research Corporation | Integrated capacitive and inductive power sources for a plasma etching chamber |
| US7938931B2 (en) * | 2006-05-24 | 2011-05-10 | Lam Research Corporation | Edge electrodes with variable power |
| US9184043B2 (en) * | 2006-05-24 | 2015-11-10 | Lam Research Corporation | Edge electrodes with dielectric covers |
| US7718542B2 (en) * | 2006-08-25 | 2010-05-18 | Lam Research Corporation | Low-k damage avoidance during bevel etch processing |
| KR101359402B1 (en) * | 2006-10-30 | 2014-02-07 | 주성엔지니어링(주) | Etching Apparatus for edges of substrate |
| KR100978754B1 (en) | 2008-04-03 | 2010-08-30 | 주식회사 테스 | Plasma processing apparatus |
| KR100835408B1 (en) * | 2006-12-28 | 2008-06-04 | 동부일렉트로닉스 주식회사 | Variable insulator for a bevel etching apparatus |
| US20080156772A1 (en) * | 2006-12-29 | 2008-07-03 | Yunsang Kim | Method and apparatus for wafer edge processing |
| US7858898B2 (en) * | 2007-01-26 | 2010-12-28 | Lam Research Corporation | Bevel etcher with gap control |
| US8398778B2 (en) | 2007-01-26 | 2013-03-19 | Lam Research Corporation | Control of bevel etch film profile using plasma exclusion zone rings larger than the wafer diameter |
| US8580078B2 (en) * | 2007-01-26 | 2013-11-12 | Lam Research Corporation | Bevel etcher with vacuum chuck |
| US7943007B2 (en) | 2007-01-26 | 2011-05-17 | Lam Research Corporation | Configurable bevel etcher |
| US8268116B2 (en) * | 2007-06-14 | 2012-09-18 | Lam Research Corporation | Methods of and apparatus for protecting a region of process exclusion adjacent to a region of process performance in a process chamber |
| KR101262904B1 (en) * | 2007-02-06 | 2013-05-09 | 참엔지니어링(주) | Plasma etching apparatus |
| US8137501B2 (en) * | 2007-02-08 | 2012-03-20 | Lam Research Corporation | Bevel clean device |
| KR101353041B1 (en) * | 2007-03-08 | 2014-02-17 | (주)소슬 | plasma etching apparatus and method |
| KR101311723B1 (en) * | 2007-03-08 | 2013-09-25 | (주)소슬 | plasma etching apparatus and method of etching a substrate using the same |
| US8980049B2 (en) * | 2007-04-02 | 2015-03-17 | Charm Engineering Co., Ltd. | Apparatus for supporting substrate and plasma etching apparatus having the same |
| US8563619B2 (en) * | 2007-06-28 | 2013-10-22 | Lam Research Corporation | Methods and arrangements for plasma processing system with tunable capacitance |
| WO2009085238A1 (en) * | 2007-12-27 | 2009-07-09 | Lam Research Corporation | Copper discoloration prevention following bevel etch process |
| TWI501704B (en) * | 2008-02-08 | 2015-09-21 | Lam Res Corp | Methods and apparatus for changing area ratio in a plasma processing system |
| US9136105B2 (en) * | 2008-06-30 | 2015-09-15 | United Microelectronics Corp. | Bevel etcher |
| KR101540609B1 (en) * | 2009-02-24 | 2015-07-31 | 삼성전자 주식회사 | Apparatus for etching edge of wafer |
| US20130098390A1 (en) * | 2011-10-25 | 2013-04-25 | Infineon Technologies Ag | Device for processing a carrier and a method for processing a carrier |
| US9184030B2 (en) | 2012-07-19 | 2015-11-10 | Lam Research Corporation | Edge exclusion control with adjustable plasma exclusion zone ring |
| US11251019B2 (en) * | 2016-12-15 | 2022-02-15 | Toyota Jidosha Kabushiki Kaisha | Plasma device |
| JP6863199B2 (en) | 2017-09-25 | 2021-04-21 | トヨタ自動車株式会社 | Plasma processing equipment |
| US10566181B1 (en) * | 2018-08-02 | 2020-02-18 | Asm Ip Holding B.V. | Substrate processing apparatuses and substrate processing methods |
| CN112992637A (en) * | 2019-12-02 | 2021-06-18 | Asm Ip私人控股有限公司 | Substrate supporting plate, substrate processing apparatus including the same, and substrate processing method |
| CN112981372B (en) * | 2019-12-12 | 2024-02-13 | Asm Ip私人控股有限公司 | Substrate support plate, substrate processing apparatus including the same, and substrate processing method |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5687670A (en) * | 1979-12-15 | 1981-07-16 | Anelva Corp | Dry etching apparatus |
| US4793975A (en) * | 1985-05-20 | 1988-12-27 | Tegal Corporation | Plasma Reactor with removable insert |
| JPS6316625A (en) * | 1986-07-09 | 1988-01-23 | Matsushita Electric Ind Co Ltd | Electrode for dry etching |
| JPH02298024A (en) * | 1989-05-12 | 1990-12-10 | Tadahiro Omi | Reactive ion etching apparatus |
| JP2758755B2 (en) * | 1991-12-11 | 1998-05-28 | 松下電器産業株式会社 | Dry etching apparatus and method |
| JPH07142449A (en) * | 1993-11-22 | 1995-06-02 | Kawasaki Steel Corp | Plasma etching system |
| TW299559B (en) * | 1994-04-20 | 1997-03-01 | Tokyo Electron Co Ltd | |
| JP3107971B2 (en) * | 1994-05-17 | 2000-11-13 | 株式会社半導体エネルギー研究所 | Gas phase reactor |
| JP3521587B2 (en) * | 1995-02-07 | 2004-04-19 | セイコーエプソン株式会社 | Method and apparatus for removing unnecessary substances from the periphery of substrate and coating method using the same |
| KR0122876Y1 (en) * | 1995-03-30 | 1999-02-18 | 문정환 | Plasma etching apparatus of semiconductor apparatus |
| KR19980034188A (en) * | 1996-11-05 | 1998-08-05 | 김광호 | Lower electrode plate of semiconductor etching equipment |
| KR100246858B1 (en) * | 1997-05-07 | 2000-03-15 | 윤종용 | Dry etching apparatus |
| US6441554B1 (en) * | 2000-11-28 | 2002-08-27 | Se Plasma Inc. | Apparatus for generating low temperature plasma at atmospheric pressure |
| KR100439940B1 (en) * | 2002-01-11 | 2004-07-12 | 주식회사 래디언테크 | Etching process module for edge of wafer |
-
2002
- 2002-03-04 KR KR10-2002-0011395A patent/KR100442194B1/en active IP Right Review Request
- 2002-04-19 US US10/506,558 patent/US20050178505A1/en not_active Abandoned
- 2002-04-19 JP JP2003573690A patent/JP4152895B2/en not_active Expired - Fee Related
- 2002-04-19 WO PCT/KR2002/000715 patent/WO2003075333A1/en active Application Filing
- 2002-04-19 AU AU2002253689A patent/AU2002253689A1/en not_active Abandoned
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI230415B (en) | 2005-04-01 |
| AU2002253689A1 (en) | 2003-09-16 |
| WO2003075333A1 (en) | 2003-09-12 |
| KR20030072520A (en) | 2003-09-15 |
| US20050178505A1 (en) | 2005-08-18 |
| JP2005519469A (en) | 2005-06-30 |
| KR100442194B1 (en) | 2004-07-30 |
| JP4152895B2 (en) | 2008-09-17 |
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