1225293 五 發明說明（1) ^發明係有關於為一種用於積體電路 锯f造方法，特別係指一種可有效提高產二之基板構造 锡焊（SMT)黏著度者。 產可靠度及增 按，申請人前於八十九年十一月十丄 ^ ^路封裝之基板構造及其製造方法』專利申f『用於蕷1225293 5 Description of the invention (1) ^ The invention relates to a manufacturing method for integrated circuit saws, and particularly refers to a soldering (SMT) adhesion that can effectively improve the substrate structure of the second production. Production reliability and increase According to the applicant, before November 10, 1989, the substrate structure of the ^ ^ circuit package and its manufacturing method "patent application f" for 蓣
1包為第1 5 0 9 °8號。其專利特徵如：;所並亍已核 一匕括有複數個相互排列之金屬片丨0，每一 斤不， :土 一表面I2及一第二表面Η; 一封膠體le，其:二0設有 ::士屬片ίο包覆住，以形成一基板，並使每二金： 第一表面1 2及第二表面丨4由封膠體i 6露出，以 ^一積體電路連接之訊號輸人端及用以與 接之訊號輸出端。 W览路板連 上述之該專利雖確可達到其創作目的及功 存在有以下之缺失·· w ’仍One pack is No. 15 0 9 ° 8. Its patent features are as follows :; the core has a plurality of metal pieces arranged on each other, each catty is not: a soil surface I2 and a second surface Η; a colloid le, which: two 0 is provided with :: the genus sheet is covered to form a substrate, and every two gold: the first surface 12 and the second surface 丨 4 are exposed by the sealing compound i 6, and are connected by a integrated circuit Signal input terminal and signal output terminal for connection. Although the above-mentioned patent can indeed achieve its creative purposes and functions, there are the following shortcomings ...
1 ·由於金屬片1 〇在製造上，不論以沖壓或蝕刻方式皆I 將其製成較高之厚度，以致於其封裝後，外界之不利因、子 (溫度及濕度）將滲透進入積體電路内，將影響到 之電性特性，以致於其可靠度較低。 償髖電路 2·因金屬片1 0厚度較薄，所以在錫焊（SMT)過程中，焊錫 將無法在金屬片1 0之側邊攀爬，以致於影響到封裝體固定 於印刷電路板之穩定度。1 · Because the metal sheet 10 is manufactured, whether it is stamped or etched, it will be made into a higher thickness, so that after its packaging, external adverse factors, temperature (humidity and humidity) will penetrate into the product In the circuit, the electrical characteristics will be affected, so that its reliability is low. Compensating hip circuit 2. Due to the thin thickness of the metal sheet 10, during the soldering (SMT) process, the solder will not be able to climb on the side of the metal sheet 10, which will affect the package's fixing to the printed circuit board. stability.
1225293 五 發明說明（2) 神 方 有鑑於此’本發明人乃本 ，而發明出本發明用於積體電路=創新突破之精 法，其可改進上述該專利之缺造及製造 八便其更為實用者。 本發明之主要目的，在於提供一 之基板構造及其製造方法，盆且 j於積體電路封裝 以達到提高其封裝可靠度之目、^。㈢加基板厚度之功效， 之美= 之：：的’在於提供-種用於積體電路封裝 高焊(SMT)過程中，使烊錫可攀純 同之回度，可提咼基板固定於印刷電路板之穩定度。 是以，為達上述之目的，本發明之主要特徵在於包括 有：複數個相互排列之下層金屬片，該每一下層金屬片設 有一上表面及一下表面；複數個相互排列之上層金屬片， 該每一上層金屬片設有一上表面及一下表面，^下表面係 相對應地疊設於該下層金屬片之上表面；及一封膠體，其 係用以將該下層金屬片及該上層金屬片包覆黏著住，並使 該每一上層金屬片之上表面由封膠體露出，該每一下層金 屬片之下表面由封膠體露出’用以電連接至印刷電路板。 如是，即可達到上述之功效及目的。 本案得藉由以下圖式及說明，得以更深入之瞭解。 iu式 請參閱圖2’為本發明用於積體電路封裝之基板構造 1225293 五、發明說明（3) 之剖視圖，其包括有複數個相互排列之下層金屬片2 〇、複 數個相互排列之上層金屬片2 6及封膠體3 2，其中： 該母一下層金屬片2 0設有一上表面2 2及一下表面2 4。 η亥母一上層金屬片2 6設有一上表面2 8及一下表面3 0， 下表面3 0係相對應地疊設於下層金屬片2 〇之上表面2 2上， 而於每一對應之上層金屬片26間設有中間板33,係用以設 置積體電路。 —封膠體32係用以將下層金屬片2〇及上層金屬片26包覆 ^著住’並使每一上層金屬片26之上表面28及中間板33由 j膠體32露出，每一下層金屬片2〇之下表面24由封膠體22 =出’用以電連接至印刷電路板3 4，將該積體電路之訊號 傳遞至印刷電路板。 如疋’藉由本發明之基板構造進行積體電路之封裝 時:由於，基板係由上、下層金屬片26、2〇組合而成，使 其厚度較咼，可更有效防止外界不利因子（溫度、濕度）影 響到積體電路，電性特性，因此，可使封裝體得到較佳之 7靠度且¥ 4封裝體封裝完成而進行錫焊（$ μ τ)於印刷 電路板32上時，可藉由焊錫36攀爬至該基板之上層金屬片、 26上，因此，可得到較佳之黏著度。 請參閱圖3、圖4及圖5，在本實施例中，係於一下声 金屬，40上以沖壓或蝕刻方式形成若干個下層金屬片組 42，每一下層金屬片組42形成有複數個相互排列之 屬片20 ;及於一上層金屬板44上以沖壓或蝕刻方 ^ 干個上層金屬片組46，每一上層金屬片組46形成有複1225293 Five invention descriptions (2) In view of this, the inventor is the inventor, and invented the invention for the integrated method of integrated circuit = innovative breakthrough, which can improve the lack of the above patent and manufacture it. More practical. The main object of the present invention is to provide a substrate structure and a manufacturing method thereof, and to package the integrated circuit to achieve the purpose of improving the reliability of the package. The effect of increasing the thickness of the substrate, the beauty = :: 'is to provide-a type used in the integrated circuit package high soldering (SMT) process, so that tin tin can achieve the same degree of return, can improve the substrate fixed to printing Circuit board stability. Therefore, in order to achieve the above-mentioned object, the main features of the present invention include: a plurality of lower metal sheets arranged on each other, each lower metal sheet being provided with an upper surface and a lower surface; a plurality of upper metal sheets arranged on each other, Each upper metal sheet is provided with an upper surface and a lower surface, and the lower surface is correspondingly stacked on the upper surface of the lower metal sheet; and a colloid is used for the lower metal sheet and the upper metal sheet. The sheets are covered and adhered, and the upper surface of each upper metal sheet is exposed by the sealing compound, and the lower surface of each lower metal sheet is exposed by the sealing compound for electrical connection to the printed circuit board. If so, the above-mentioned effects and purposes can be achieved. This case can be understood more deeply by the following drawings and descriptions. Please refer to FIG. 2 for the iu formula. FIG. 2 ′ is a cross-sectional view of the substrate structure for integrated circuit packaging of the present invention. The metal sheet 26 and the sealing compound 32 are provided, wherein: the mother lower metal sheet 20 is provided with an upper surface 22 and a lower surface 24. An upper layer of metal sheet 26 is provided with an upper surface 28 and a lower surface 30. The lower surface 30 is superimposed on the upper surface 22 of the lower metal sheet 2 and corresponding to each other. An intermediate plate 33 is provided between the upper metal sheets 26, which is used to set an integrated circuit. —The sealing colloid 32 is used to cover the lower metal sheet 20 and the upper metal sheet 26, and to expose the upper surface 28 and the intermediate plate 33 of each upper metal sheet 26 from the j colloid 32, and each lower metal The lower surface 24 of the sheet 20 is formed by the sealing compound 22 to be electrically connected to the printed circuit board 34, and the signal of the integrated circuit is transmitted to the printed circuit board. For example, when packaging integrated circuits by using the substrate structure of the present invention: Because the substrate is composed of upper and lower metal sheets 26 and 20, its thickness is thicker, which can more effectively prevent external adverse factors (temperature , Humidity) affect the integrated circuit, electrical characteristics, so that the package can get a better 7-reliance and ¥ 4 package is completed and soldered ($ μ τ) on the printed circuit board 32, can The solder 36 climbs onto the upper metal sheets 26 of the substrate, so better adhesion can be obtained. Please refer to FIG. 3, FIG. 4, and FIG. 5. In this embodiment, a plurality of lower metal sheet groups 42 are formed on the acoustic metal by stamping or etching. Each of the lower metal sheet groups 42 is formed with a plurality of The sheets 20 are arranged on each other; and an upper metal sheet group 46 is formed by punching or etching on an upper metal sheet 44, and each upper metal sheet group 46 is formed with a compound
1225293 五、發明說明（4) ΐίΠΓ上層金屬片26及中間板33,將上層金屬板“盥 Κι:; 4〇相互疊合，請配合參閱圖2,再以工举塑膠 為材枓射出成型，髂卜、丁馬1 p m ^ w 成封膠F ^ #將 下層金屬片26、20包覆著，而形 ;οίϊί層金屬片26之上表面28、中間板33及 !二=1表®24由封膠體32露出，**，即可將 :可1 if ΐ之下層金屬片20與上層金“26予以切割， 即了成為本發明之基板構造。 法包；；列i:明用於積趙電路封*之基板構造之製造方 下層金屬 提供複數個相互排列之上層金屬片26，每一上層金屬 =26設有一上表面28及一下表面3〇，下表面3 ^ 疊設於下層金屬片20之上表面22，而於戽 η Μ ώ 屬片26間設有中間板33; & 22㈣母_對應之上層金 提供一封膠體32,其係利用工業塑膠材料型， 用以：下層金屬片2〇及上層金屬Μ 26包覆黏著住=每 二上層金屬片26之上表面28及中間板33由封膠體32露出， 母一下層金屬片20之下表面24由封膠體32露出， 可完成本發明基板構造之製造。 尺 在較佳實施例之詳細說明中所提出之 了”說明本發明之技術㈣，並非將本二 於實施例’凡依本發明之精神及以下申請專^ 所作種種變化實施均屬本發明之範圍。 现固& 1225293 圖式簡單說明 圖1為習知影像感測器封裝構造之示意圖。 圖2為本發明用於積體電路封裝之基板構造之剖視圖。 圖3為本發明用於積體電路封裝之基板製造方法之第一示 意圖。。 圖4為本發明用於積體電路封裝之基板製造方法之第二示 意圖。 圖5為本發明之上層金屬片2 6與下層金屬片2 0於製程中疊 合時之剖視圖。1225293 V. Description of the invention (4) ΐίΠΓ upper metal sheet 26 and intermediate plate 33, superimposed the upper metal plate "washer :; 40" on top of each other, please refer to Figure 2, and then use industrial plastics as the material for injection molding髂 卜 、 丁马 1 pm ^ w 成 封 胶 F ^ # Cover the lower metal sheets 26, 20 and shape; οοϊί the upper surface 28 of the metal sheet 26, the middle plate 33 and! 二 = 1 表 ®24 Exposed from the sealing compound 32, **, the following can be cut: if the lower metal sheet 20 and the upper gold 26 are cut, the substrate structure of the present invention can be obtained.包 I ;; column i: The manufacturer of the substrate structure used for the product of JZC circuit seal *. The lower layer metal provides a plurality of upper layer metal sheets 26 arranged on each other. Each upper layer metal = 26 is provided with an upper surface 28 and a lower surface 3〇 The lower surface 3 ^ is superposed on the upper surface 22 of the lower metal sheet 20, and an intermediate plate 33 is provided between the 26 metal sheets 26; & 22 ㈣_ corresponding to the upper layer of gold to provide a colloid 32, which is Use industrial plastic material type to cover: the lower metal sheet 20 and the upper metal M 26 are covered and adhered = the upper surface 28 and the middle plate 33 of every two upper metal sheets 26 are exposed by the sealant 32, and the lower metal sheet 20 The lower surface 24 is exposed by the sealant 32, which can complete the manufacture of the substrate structure of the present invention. The ruler proposed in the detailed description of the preferred embodiment "explains the technology of the present invention", and does not implement the various changes made in this embodiment in accordance with the spirit of the present invention and the following applications. Scope. Now solid & 1225293 Schematic illustration. Figure 1 is a schematic diagram of a conventional image sensor package structure. Figure 2 is a cross-sectional view of the substrate structure of the present invention for integrated circuit packaging. First schematic diagram of a substrate manufacturing method for a body circuit package. Fig. 4 is a second schematic diagram of a substrate manufacturing method for an integrated circuit package of the present invention. Fig. 5 is an upper layer metal sheet 26 and a lower layer metal sheet 20 of the present invention. A cross-sectional view of the process during stacking.
本發明之圖號 下 層 金 屬 片 20 上 表 上 層 金 屬 片 26 上 表 中 間 板 33 封 膠 焊 錫 36 下 層 上 層 金 屬 板 44 上 層 面22 下表面24 面28 下表面30 體3 2 印刷電路板3 4 金屬板40 下層金屬片組42 金屬片組4 6Drawing number of the present invention Lower metal sheet 20 Upper surface upper metal sheet 26 Upper surface intermediate plate 33 Sealing solder 36 Lower upper layer metal plate 44 Upper surface layer 22 Lower surface 24 Surface 28 Lower surface 30 Body 3 2 Printed circuit board 3 4 Metal plate 40 Lower metal sheet group 42 Metal sheet group 4 6
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