JP2009193982A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP2009193982A
JP2009193982A JP2008029916A JP2008029916A JP2009193982A JP 2009193982 A JP2009193982 A JP 2009193982A JP 2008029916 A JP2008029916 A JP 2008029916A JP 2008029916 A JP2008029916 A JP 2008029916A JP 2009193982 A JP2009193982 A JP 2009193982A
Authority
JP
Japan
Prior art keywords
semiconductor device
slope
devices
electrode
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008029916A
Other languages
Japanese (ja)
Inventor
Kazuma Sekiya
一馬 関家
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
Original Assignee
Disco Abrasive Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Abrasive Systems Ltd filed Critical Disco Abrasive Systems Ltd
Priority to JP2008029916A priority Critical patent/JP2009193982A/en
Publication of JP2009193982A publication Critical patent/JP2009193982A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24998—Reinforcing structures, e.g. ramp-like support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stack-type semiconductor device that is miniaturized without disconnecting a lead wire. <P>SOLUTION: In the stack-type semiconductor device where a plurality of devices are laminated on a frame substrate having a plurality of outer lead terminals, the plurality of devices are laminated in steps by an insulating adhesive for resin-sealing, an electrode formed in each device has an exposed, inclined surface, and the electrode is connected to the outer lead terminal along the inclined surface by a lead wire. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、スタックタイプの半導体装置及びその製造方法に関する。   The present invention relates to a stack type semiconductor device and a method for manufacturing the same.

近年、携帯機器、特に携帯電話市場における小型化の要求に伴い、搭載される半導体装置に対しても小型化が要求されている。この要求を満たすために、複数のデバイスを積層し更に樹脂封止したスタックタイプの半導体装置が開発されている（例えば、特開２００１−１１８８７７号参照）。   In recent years, with the demand for miniaturization in the mobile device market, particularly in the mobile phone market, miniaturization is also required for the semiconductor devices to be mounted. In order to satisfy this requirement, a stack type semiconductor device in which a plurality of devices are stacked and further sealed with a resin has been developed (see, for example, JP-A-2001-118877).

代表的なスタックタイプの半導体装置は、デバイスを支持するデバイス支持領域とデバイスの外周に形成された複数の電極と電気的に接続されるアウターリード端子とを有するフレーム基板上に複数のデバイスが積層され、各デバイスの電極とアウターリード端子とが金線によって連結され、エポキシ樹脂等でパッケージングされて構成されている。
特開２００１−１１８８７７号公報 A typical stack type semiconductor device has a plurality of devices stacked on a frame substrate having a device support region for supporting the device and outer lead terminals electrically connected to a plurality of electrodes formed on the outer periphery of the device. The electrodes of each device and the outer lead terminals are connected by a gold wire and packaged with an epoxy resin or the like.
JP 2001-118877 A

従来のスタックタイプの半導体装置では、金線が下層デバイスのコーナーに接触して断線する恐れがあることから金線はアーチ状に湾曲して接続されており、比較的多くの金線が必要となりコスト高になるという問題がある。   In a conventional stack type semiconductor device, the gold wire may be bent and connected in an arch shape because it may come into contact with the corner of the lower layer device, and a relatively large number of gold wires are required. There is a problem of high costs.

また、アーチ状に湾曲した金線が樹脂でモールドされてパッケージングされるため、外径が比較的大きくなるという問題がある。   Further, since the arch-shaped curved gold wire is molded with resin and packaged, there is a problem that the outer diameter becomes relatively large.

本発明はこのような点に鑑みてなされたものであり、その目的とするところは、リード線が下層のデバイスのコーナーに接触して断線することがなく、樹脂モールドでのパッケージングを小型化できるスタックタイプの半導体装置及びその製造方法を提供することである。   The present invention has been made in view of these points, and the object of the present invention is to reduce the size of the packaging with a resin mold without causing the lead wire to contact with the corner of the underlying device and disconnection. A stack type semiconductor device and a method for manufacturing the same are provided.

請求項１記載の発明によると、複数のアウターリード端子を有するフレーム基板上に複数のデバイスが積層されたスタックタイプの半導体装置であって、該複数のデバイスは絶縁性接着剤で階段状に積層されて樹脂封止され、且つ各デバイスに形成された電極が露出した斜面を有しており、該電極と前記アウターリード端子とが斜面に沿ってリード線で接続されていることを特徴とするスタックタイプの半導体装置が提供される。   According to the first aspect of the present invention, there is provided a stack type semiconductor device in which a plurality of devices are stacked on a frame substrate having a plurality of outer lead terminals, and the plurality of devices are stacked stepwise with an insulating adhesive. The electrode formed on each device has an exposed slope, and the electrode and the outer lead terminal are connected by a lead wire along the slope. A stack type semiconductor device is provided.

請求項２記載の発明によると、半導体装置の製造方法であって、それぞれ電極を有する複数のデバイスを絶縁性接着剤で階段状にフレーム基板に積層する積層工程と、積層された複数のデバイスを樹脂封止する樹脂封止工程と、階段状の端部を研削して斜面を形成し、各デバイスに形成された電極を斜面に露出させる電極露出工程と、斜面に露出した電極とフレーム基板に形成されたアウターリード端子とを斜面に沿ってリード線で接続する接続工程と、を具備したことを特徴とする半導体装置の製造方法が提供される。   According to invention of Claim 2, it is a manufacturing method of a semiconductor device, Comprising: The lamination process which laminates | stacks several devices each having an electrode on a frame board | substrate in step shape with an insulating adhesive, Resin sealing process for resin sealing, stepped end portions are ground to form slopes, electrode exposure process for exposing electrodes formed on each device to the slopes, and electrodes and frame substrates exposed on the slopes There is provided a method for manufacturing a semiconductor device, comprising: a connecting step of connecting a formed outer lead terminal with a lead wire along a slope.

本発明によると、斜面に露出した各デバイスの電極とアウターリード端子とを斜面に沿ってリード線で接続するようにしたので、リード線が下層のデバイスのコーナーに接触して断線することがないと共に、使用するリード線を少なくできるので、コストの低減を図ることができる。更に、リード線がアーチ状に湾曲していないので、樹脂モールドでのパッケージングを小型化できる。   According to the present invention, since the electrode of each device exposed on the slope and the outer lead terminal are connected by the lead wire along the slope, the lead wire does not come into contact with the corner of the lower layer device and is disconnected. In addition, since the number of lead wires to be used can be reduced, the cost can be reduced. Furthermore, since the lead wire is not curved in an arch shape, the packaging with the resin mold can be reduced in size.

以下、本発明の実施形態を図面を参照して詳細に説明する。図１を参照すると、複数のバンプ電極４ａ，４ｂ，４ｃを有する第１デバイス２上にＤＡＦ（ダイアタッチフィルム）等の絶縁性接着剤１０を介して複数のバンプ電極８ａ，８ｂ，８ｃを有する第２デバイス６が階段状に積層され、更に第２デバイス６上にＤＡＦ等の絶縁性接着剤１６を介して複数のバンプ電極１４ａ，１４ｂ，１４ｃを有する第３デバイス１２が階段状に積層されて積層デバイス１８を構成する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, a plurality of bump electrodes 8a, 8b, and 8c are provided on a first device 2 having a plurality of bump electrodes 4a, 4b, and 4c via an insulating adhesive 10 such as DAF (die attach film). The second device 6 is stacked stepwise, and the third device 12 having a plurality of bump electrodes 14a, 14b, and 14c is stacked on the second device 6 via an insulating adhesive 16 such as DAF. Thus, the laminated device 18 is configured.

２０はフレーム基板であり、デバイス支持領域２２と複数のアウターリード端子２４ａ，２４ｂ，２４ｃを有している。積層デバイス１８をＤＡＦ等の絶縁性接着剤２６を介して、矢印Ａに示すようにフレーム基板２０のデバイス支持領域２２上に搭載することにより、図２に示す構成が得られる。   Reference numeral 20 denotes a frame substrate, which has a device support region 22 and a plurality of outer lead terminals 24a, 24b, and 24c. By mounting the laminated device 18 on the device support region 22 of the frame substrate 20 as indicated by an arrow A through an insulating adhesive 26 such as DAF, the configuration shown in FIG. 2 is obtained.

次いで、図３に示すように、エポキシ樹脂等で樹脂封止（パッケージング）２８した後、図４に示すように端部を研削して樹脂封止２８の端部に斜面３０を形成し、第１〜第３デバイス２，６，１２のバンプ電極４ａ〜４ｃ、８ａ〜８ｃ、１４ａ〜１４ｃを斜面３０に露出させる。   Next, as shown in FIG. 3, after resin sealing (packaging) 28 with an epoxy resin or the like, the end portion is ground as shown in FIG. 4 to form a slope 30 at the end portion of the resin seal 28, The bump electrodes 4 a to 4 c, 8 a to 8 c, and 14 a to 14 c of the first to third devices 2, 6 and 12 are exposed to the inclined surface 30.

すなわち、樹脂封止２８と共に各バンプ電極４ａ〜４ｃ、８ａ〜８ｃ、１４ａ〜１４ｃを研削することにより、各バンプ電極を斜面３０に沿って削ぎ落として各バンプ電極４ａ〜４ｃ、８ａ〜８ｃ、１４ａ〜１４ｃを斜面３０に露出させることができる。   That is, by grinding the bump electrodes 4a to 4c, 8a to 8c, and 14a to 14c together with the resin sealing 28, the bump electrodes 4a to 4c and 8a to 8c are scraped off along the inclined surface 30. 14 a to 14 c can be exposed to the inclined surface 30.

このように各バンプ電極を斜面３０に露出させた後、図５に示すようにリード線３２ａをバンプ電極４ａ，８ａ、１４ａにボンディング接続すると共に、アウターリード端子２４ａにボンディング接続することにより、各バンプ電極４ａ，８ａ，１４ａがリード線３２ａを介してアウターリード端子２４ａに接続される。   After each bump electrode is exposed to the inclined surface 30 in this way, the lead wire 32a is bonded to the bump electrodes 4a, 8a, and 14a and bonded to the outer lead terminal 24a as shown in FIG. The bump electrodes 4a, 8a and 14a are connected to the outer lead terminal 24a via the lead wire 32a.

同様に、バンプ電極４ｂ，８ｂ，１４ｂがリード線３２ｂを介してアウターリード端子２４ｂに接続され、バンプ電極４ｃ，８ｃ，１４ｃがリード線３２ｃを介してアウターリード端子２４ｃに接続され、スタックタイプの半導体装置３４が完成する。尚、リード線３２ａ〜３２ｃとしては金線を採用するのが好ましい。   Similarly, the bump electrodes 4b, 8b, and 14b are connected to the outer lead terminal 24b via the lead wire 32b, and the bump electrodes 4c, 8c, and 14c are connected to the outer lead terminal 24c via the lead wire 32c. The semiconductor device 34 is completed. In addition, it is preferable to employ | adopt a gold wire as lead wire 32a-32c.

スタックタイプの半導体装置３４は以上詳述したように構成されているので、リード線３２ａ〜３２ｃが下層のデバイスのコーナーに接触して断線する恐れがないと共に、使用するリード線を少なくできるので、半導体装置のコストの低減を図ることができる。   Since the stack type semiconductor device 34 is configured as described in detail above, the lead wires 32a to 32c are not in contact with the corners of the underlying device, and the lead wires to be used can be reduced. The cost of the semiconductor device can be reduced.

また、リード線３２ａ〜３２ｃは斜面３０に沿って各バンプ電極にボンディング接続できるので、リード線３２ａ〜３２ｃを湾曲する必要がなく樹脂封止でのパッケージングを小型化できる。尚、リード線３２ａ〜３２ｃを樹脂で封止することが好ましい。   Further, since the lead wires 32a to 32c can be bonded to the bump electrodes along the inclined surface 30, it is not necessary to bend the lead wires 32a to 32c, and the packaging with resin sealing can be reduced in size. The lead wires 32a to 32c are preferably sealed with resin.

積層デバイスをフレーム基板に搭載する様子を示す斜視図である。It is a perspective view which shows a mode that a laminated device is mounted in a frame board | substrate. フレーム基板に搭載された積層デバイスの斜視図である。It is a perspective view of the lamination | stacking device mounted in the frame board | substrate. 樹脂封止された状態の半導体装置の斜視図である。It is a perspective view of the semiconductor device of the state sealed with resin. 端部に斜面を形成して各バンプ電極を斜面に露出させた状態の半導体装置の斜視図である。It is a perspective view of a semiconductor device in a state where a slope is formed at an end and each bump electrode is exposed on the slope. 各バンプ電極をアウターリード端子に接続した状態の半導体装置の斜視図である。It is a perspective view of a semiconductor device in a state where each bump electrode is connected to an outer lead terminal.

符号の説明Explanation of symbols

２ 第１デバイス
４ａ〜４ｃ バンプ電極
６ 第２デバイス
８ａ〜８ｃ バンプ電極
１０，１６，２６ 絶縁性接着剤
１２ 第３デバイス
１４ａ〜１４ｃ バンプ電極
２０ フレーム基板
２２ デバイス支持領域
２４ａ〜２４ｃ アウターリード端子
２８ 樹脂封止
３０ 斜面
３２ａ〜３２ｃ リード線
３４ スタックタイプの半導体装置 2 1st device 4a-4c Bump electrode 6 2nd device 8a-8c Bump electrode 10,16,26 Insulating adhesive 12 3rd device 14a-14c Bump electrode 20 Frame substrate 22 Device support area 24a-24c Outer lead terminal 28 Resin sealing 30 Slopes 32a to 32c Lead wire 34 Stack type semiconductor device

Claims (2)

複数のアウターリード端子を有するフレーム基板上に複数のデバイスが積層されたスタックタイプの半導体装置であって、
該複数のデバイスは絶縁性接着剤で階段状に積層されて樹脂封止され、且つ各デバイスに形成された電極が露出した斜面を有しており、
該電極と前記アウターリード端子とが斜面に沿ってリード線で接続されていることを特徴とするスタックタイプの半導体装置。 A stack type semiconductor device in which a plurality of devices are stacked on a frame substrate having a plurality of outer lead terminals,
The plurality of devices are stepwise laminated with an insulating adhesive and resin-sealed, and have slopes on which electrodes formed in each device are exposed,
A stack type semiconductor device, wherein the electrode and the outer lead terminal are connected by a lead wire along a slope. 半導体装置の製造方法であって、
それぞれ電極を有する複数のデバイスを絶縁性接着剤で階段状にフレーム基板に積層する積層工程と、
積層された複数のデバイスを樹脂封止する樹脂封止工程と、
階段状の端部を研削して斜面を形成し、各デバイスに形成された電極を斜面に露出させる電極露出工程と、
斜面に露出した電極とフレーム基板に形成されたアウターリード端子とを斜面に沿ってリード線で接続する接続工程と、
を具備したことを特徴とする半導体装置の製造方法。 A method for manufacturing a semiconductor device, comprising:
A laminating step of laminating a plurality of devices each having an electrode on a frame substrate in a stepped manner with an insulating adhesive,
A resin sealing step of resin-sealing a plurality of stacked devices;
An electrode exposing step of grinding the stepped end to form a slope and exposing the electrodes formed on each device to the slope;
A connection step of connecting the electrodes exposed on the slope and the outer lead terminals formed on the frame substrate with lead wires along the slope;
A method for manufacturing a semiconductor device, comprising:
JP2008029916A 2008-02-12 2008-02-12 Semiconductor device and manufacturing method thereof Pending JP2009193982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008029916A JP2009193982A (en) 2008-02-12 2008-02-12 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008029916A JP2009193982A (en) 2008-02-12 2008-02-12 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2009193982A true JP2009193982A (en) 2009-08-27

Family

ID=41075786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008029916A Pending JP2009193982A (en) 2008-02-12 2008-02-12 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2009193982A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409452A (en) * 2014-12-23 2015-03-11 南通富士通微电子股份有限公司 Semiconductor laminating and packaging structure
CN104485291A (en) * 2014-12-23 2015-04-01 南通富士通微电子股份有限公司 Stacked semiconductor packaging method
CN108933109A (en) * 2017-05-27 2018-12-04 晟碟信息科技（上海）有限公司 The semiconductor devices of angled naked core

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118887A (en) * 1999-10-14 2001-04-27 Resuka:Kk Bonding strength testing device
JP2001217373A (en) * 2000-02-02 2001-08-10 Seiko Epson Corp Method for manufacturing semiconductor device and method for manufacturing semiconductor unit and semiconductor device and semiconductor unit
JP2007134486A (en) * 2005-11-10 2007-05-31 Toshiba Corp Stacked semiconductor device and its manufacturing method
JP2010506426A (en) * 2006-10-10 2010-02-25 テッセラ，インコーポレイテッド Edge connected wafer level laminate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001118887A (en) * 1999-10-14 2001-04-27 Resuka:Kk Bonding strength testing device
JP2001217373A (en) * 2000-02-02 2001-08-10 Seiko Epson Corp Method for manufacturing semiconductor device and method for manufacturing semiconductor unit and semiconductor device and semiconductor unit
JP2007134486A (en) * 2005-11-10 2007-05-31 Toshiba Corp Stacked semiconductor device and its manufacturing method
JP2010506426A (en) * 2006-10-10 2010-02-25 テッセラ，インコーポレイテッド Edge connected wafer level laminate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409452A (en) * 2014-12-23 2015-03-11 南通富士通微电子股份有限公司 Semiconductor laminating and packaging structure
CN104485291A (en) * 2014-12-23 2015-04-01 南通富士通微电子股份有限公司 Stacked semiconductor packaging method
CN108933109A (en) * 2017-05-27 2018-12-04 晟碟信息科技（上海）有限公司 The semiconductor devices of angled naked core
US10490529B2 (en) 2017-05-27 2019-11-26 Sandisk Information Technology (Shanghai) Co., Ltd. Angled die semiconductor device

Similar Documents

Publication Publication Date Title
US20060278970A1 (en) Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
WO2004004005A1 (en) Semiconductor device and its manufacturing method
JP5557204B2 (en) Integrated circuit package system and manufacturing system thereof
JP2005203775A (en) Multichip package
JP2012216644A (en) Semiconductor device and method of manufacturing the same
US6972372B1 (en) Method and apparatus for stacking electrical components using outer lead portions and exposed inner lead portions to provide interconnection
JP2009218804A (en) Semiconductor device, and communication apparatus and electronic apparatus provided with the same
TWI429054B (en) Integrated circuit package system with offset stack
JP2011181697A (en) Semiconductor package, and method of manufacturing the same
JP2009193982A (en) Semiconductor device and manufacturing method thereof
JP5275019B2 (en) Semiconductor device
JP2005340415A (en) Semiconductor package and manufacturing method thereof
JP2007116030A (en) Semiconductor device and semiconductor package using it
JP2010087403A (en) Semiconductor device
JP2008085032A (en) Semiconductor device
JP4181557B2 (en) Semiconductor device and manufacturing method thereof
KR101686349B1 (en) Semiconductor package and fabricating method thereof
JP4716836B2 (en) Semiconductor device
KR20080020137A (en) Stack package having a reverse pyramidal shape
JP2006066551A5 (en)
JP2009193983A (en) Semiconductor device and manufacturing method thereof
JP2008041999A (en) Semiconductor device and its manufacturing method
JP2007234683A (en) Semiconductor device, and its manufacturing method
JP2009193984A (en) Semiconductor device and manufacturing method thereof
JP5149694B2 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110117

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120229

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121218

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130416