JP2009193983A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2009193983A
JP2009193983A JP2008029917A JP2008029917A JP2009193983A JP 2009193983 A JP2009193983 A JP 2009193983A JP 2008029917 A JP2008029917 A JP 2008029917A JP 2008029917 A JP2008029917 A JP 2008029917A JP 2009193983 A JP2009193983 A JP 2009193983A
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semiconductor device
slope
devices
frame substrate
electrode
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Kazuma Sekiya
一馬 関家
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Disco Corp
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Disco Abrasive Systems Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a stack-type semiconductor device that is miniaturized without disconnecting a lead wire. <P>SOLUTION: In the stack-type semiconductor device where a plurality of devices are laminated on a frame substrate having a plurality of outer lead terminals, the plurality of devices in which an electrode is arranged on an inclined surface formed at an outer periphery are laminated on the frame substrate by an insulating adhesive, and the electrode arranged on the inclines surface is connected to the outer lead terminal by a lead wire. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、スタックタイプの半導体装置及びその製造方法に関する。   The present invention relates to a stack type semiconductor device and a method for manufacturing the same.

近年、携帯機器、特に携帯電話市場における小型化の要求に伴い、搭載される半導体装置に対しても小型化が要求されている。この要求を満たすために、複数のデバイスを積層し更に樹脂封止したスタックタイプの半導体装置が開発されている（例えば、特開２００１−１１８８７７号及び特開２００２−２２２９１３号参照）。   In recent years, with the demand for miniaturization in portable equipment, particularly in the mobile phone market, miniaturization is also demanded for semiconductor devices to be mounted. In order to satisfy this requirement, a stack type semiconductor device in which a plurality of devices are stacked and further resin-sealed has been developed (see, for example, Japanese Patent Application Laid-Open Nos. 2001-118877 and 2002-222913).

代表的なスタックタイプの半導体装置は、デバイスを支持するデバイス支持領域とデバイスの外周に形成された複数の電極と電気的に接続されるアウターリード端子とを有するフレーム基板上に複数のデバイスが積層され、各デバイスの電極とアウターリード端子とが金線によって連結され、エポキシ樹脂等でパッケージングされて構成されている。
特開２００１−１１８８７７号公報 特開２００２−２２２９１３号公報 A typical stack type semiconductor device has a plurality of devices stacked on a frame substrate having a device support region for supporting the device and outer lead terminals electrically connected to a plurality of electrodes formed on the outer periphery of the device. The electrodes of each device and the outer lead terminals are connected by a gold wire and packaged with an epoxy resin or the like.
JP 2001-118877 A JP 2002-222913 A

従来のスタックタイプの半導体装置では、金線が下層デバイスのコーナーに接触して断線する恐れがあることから金線はアーチ状に湾曲して接続されており、比較的多くの金線が必要となりコスト高になるという問題がある。   In a conventional stack type semiconductor device, the gold wire is bent and connected in an arch shape because there is a risk that the gold wire contacts the corner of the lower layer device, and a relatively large number of gold wires are required. There is a problem of high costs.

また、アーチ状に湾曲した金線が樹脂でモールドされてパッケージングされるため、外径が比較的大きくなるという問題がある。   Further, since the arch-shaped curved gold wire is molded with resin and packaged, there is a problem that the outer diameter becomes relatively large.

本発明はこのような点に鑑みてなされたものであり、その目的とするところは、リード線が下層のデバイスのコーナーに接触して断線することがなく、且つ小型化可能なスタックタイプの半導体装置及びその製造方法を提供することである。   The present invention has been made in view of the above points, and an object of the present invention is to achieve a stack type semiconductor in which the lead wire does not come into contact with the corner of the underlying device and is disconnected, and can be miniaturized. An apparatus and a method for manufacturing the same are provided.

請求項１記載の発明によると、複数のアウターリード端子を有するフレーム基板上に複数のデバイスが積層されたスタックタイプの半導体装置であって、外周に形成された斜面に電極が配設されたデバイスが絶縁性接着剤を介して該フレーム基板に複数積層されており、斜面に配設された前記電極と前記アウターリード端子とがリード線で接続されていることを特徴とする半導体装置が提供される。   According to the first aspect of the present invention, there is provided a stack type semiconductor device in which a plurality of devices are stacked on a frame substrate having a plurality of outer lead terminals, wherein the electrodes are disposed on the slope formed on the outer periphery. Is laminated on the frame substrate via an insulating adhesive, and the electrode disposed on the slope and the outer lead terminal are connected by a lead wire. The

請求項２記載の発明によると、複数のアウターリード端子を有するフレーム基板上に複数のデバイスを積層するスタックタイプの半導体装置の製造方法であって、デバイスの電極が形成された半導体基板の外周に斜面を形成し、該斜面に沿ってデバイスの電極を折り曲げ、該デバイスを絶縁性接着剤を介して前記フレーム基板に複数個積層し、斜面に配設された前記電極と前記アウターリード端子とをリード線で接続する、各工程を具備したことを特徴とする半導体装置の製造方法が提供される。   According to a second aspect of the present invention, there is provided a manufacturing method of a stack type semiconductor device in which a plurality of devices are stacked on a frame substrate having a plurality of outer lead terminals, and the outer periphery of the semiconductor substrate on which the device electrodes are formed. Forming a slope, bending the electrode of the device along the slope, laminating a plurality of the devices on the frame substrate via an insulating adhesive, and connecting the electrode disposed on the slope and the outer lead terminal Provided is a method of manufacturing a semiconductor device characterized by comprising each step of connecting with lead wires.

本発明によると、外周に形成された斜面に電極が配設されたデバイスを絶縁性接着剤を介してフレーム基板に複数積層し、斜面に配設された電極とアウターリード端子とをリード線で接続して半導体装置を構成したので、リード線が下層のデバイスのコーナーに接触して断線することがないと共に、使用するリード線を少なくできるので、コストの低減を図ることができる。   According to the present invention, a plurality of devices having electrodes disposed on the slope formed on the outer periphery are stacked on the frame substrate via the insulating adhesive, and the electrodes disposed on the slope and the outer lead terminals are connected with the lead wires. Since the semiconductor device is configured by connection, the lead wire does not come into contact with the corner of the lower-layer device, and the lead wire to be used can be reduced, so that the cost can be reduced.

以下、本発明の実施形態を図面を参照して詳細に説明する。図１（Ａ）を参照すると、シリコン基板等の半導体基板３上に図示しない電子回路が形成され、該電子回路に接続された複数の電極４が外周部に形成された半導体デバイス２の斜視図が示されている。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1A, a perspective view of a semiconductor device 2 in which an electronic circuit (not shown) is formed on a semiconductor substrate 3 such as a silicon substrate, and a plurality of electrodes 4 connected to the electronic circuit are formed on the outer periphery. It is shown.

本実施形態では、電極４が形成された半導体基板３の両端部（外周部）３ａ，３ｂを研削して三角柱形状に取り除き、デバイス（第１デバイス）２の両端部に図１（Ｂ）に示すように斜面６を形成する。次いで、複数の電極４を斜面６に沿って折り曲げる。   In this embodiment, both end portions (outer peripheral portions) 3a and 3b of the semiconductor substrate 3 on which the electrode 4 is formed are ground and removed into a triangular prism shape, and the both ends of the device (first device) 2 are shown in FIG. A slope 6 is formed as shown. Next, the plurality of electrodes 4 are bent along the slope 6.

このように構成されたデバイス２を図２に示すように複数積層する。即ち、第１デバイス２上にＤＡＦ（ダイアタッチフィルム）等の絶縁性接着剤８を介して第２デバイス１０を積層し、第２デバイス１０上にＤＡＦ等の絶縁性接着剤１６を介して第３デバイス１８を積層して、積層デバイス２４を形成する。   A plurality of devices 2 configured as described above are stacked as shown in FIG. That is, the second device 10 is laminated on the first device 2 via an insulating adhesive 8 such as DAF (die attach film), and the second device 10 is laminated on the second device 10 via an insulating adhesive 16 such as DAF. Three devices 18 are stacked to form a stacked device 24.

第２デバイス１０は、第１デバイス２と同様に外周部に形成された斜面１４と、斜面１４に沿って折り曲げられた複数の電極１２を有しており、第３デバイス１８も、外周部に形成された斜面２２と、斜面２２に沿って折り曲げられた複数の電極２０を有している。   Similar to the first device 2, the second device 10 includes a slope 14 formed on the outer peripheral portion and a plurality of electrodes 12 bent along the slope 14, and the third device 18 is also provided on the outer peripheral portion. A slope 22 is formed, and a plurality of electrodes 20 are bent along the slope 22.

２８はフレーム基板であり、デバイス支持領域３０と複数のアウターリード端子３２を有している。積層デバイス２４をＤＡＦ等の絶縁性接着剤２６を介して、矢印Ａに示すようにフレーム基板２８のデバイス支持領域３０上に搭載する。   A frame substrate 28 has a device support region 30 and a plurality of outer lead terminals 32. The laminated device 24 is mounted on the device support region 30 of the frame substrate 28 as indicated by an arrow A through an insulating adhesive 26 such as DAF.

次いで、図３に示すように第１、第２、第３デバイス２，１０，１８の電極４，１２，２０をリード線３４の一端にボンディング接続すると共に、リード線３４の他端をアウターリード端子３２にボンディング接続することにより、スタックタイプの半導体装置３６が完成する。特に図示しないが、半導体装置３６は次いで樹脂封止される。   Next, as shown in FIG. 3, the electrodes 4, 12, and 20 of the first, second, and third devices 2, 10, and 18 are bonded to one end of the lead wire 34, and the other end of the lead wire 34 is connected to the outer lead. By making a bonding connection to the terminal 32, the stack type semiconductor device 36 is completed. Although not particularly shown, the semiconductor device 36 is then sealed with resin.

スタックタイプの半導体装置３６は以上詳述したように構成されているので、リード線３４が下層のデバイスのコーナーに接触して断線する恐れがないと共に、各電極がデバイスの周辺部に形成された斜面に沿って折り曲げられているので、リード線を少なくすることができ、半導体装置のコストの低減を図ることができる。   Since the stack type semiconductor device 36 is configured as described in detail above, there is no risk of the lead wires 34 coming into contact with the corners of the underlying device and breaking, and each electrode is formed in the peripheral portion of the device. Since it is bent along the slope, lead wires can be reduced and the cost of the semiconductor device can be reduced.

図１（Ａ）は半導体デバイスの斜視図であり、図１（Ｂ）は基板の両端部を斜めに削除して斜面を形成し、各電極を斜面に沿って折り曲げた状態の半導体デバイスの斜視図である。FIG. 1A is a perspective view of a semiconductor device, and FIG. 1B is a perspective view of the semiconductor device in which both ends of the substrate are removed obliquely to form a slope, and each electrode is bent along the slope. FIG. 積層デバイスをフレーム基板に搭載する様子を示す斜視図である。It is a perspective view which shows a mode that a laminated device is mounted in a frame board | substrate. 各電極をアウターリード端子に接続した状態の半導体装置の斜視図である。It is a perspective view of a semiconductor device in a state where each electrode is connected to an outer lead terminal.

符号の説明Explanation of symbols

２ デバイス（第１デバイス）
３ 半導体基板
４，１２，２０ 電極
６，１４，２２ 斜面
８，１６，２６ 絶縁性接着剤
１０ 第２デバイス
１８ 第３デバイス
２４ 積層デバイス
２８ フレーム基板
３０ デバイス支持領域
３２ アウターリード端子
３４ リード線
３６ スタックタイプの半導体装置 2 devices (first device)
3 Semiconductor substrate 4, 12, 20 Electrode 6, 14, 22 Slope 8, 16, 26 Insulating adhesive 10 Second device 18 Third device 24 Laminated device 28 Frame substrate 30 Device support region 32 Outer lead terminal 34 Lead wire 36 Stack type semiconductor device

Claims (2)

複数のアウターリード端子を有するフレーム基板上に複数のデバイスが積層されたスタックタイプの半導体装置であって、
外周に形成された斜面に電極が配設されたデバイスが絶縁性接着剤を介して該フレーム基板に複数積層されており、
斜面に配設された前記電極と前記アウターリード端子とがリード線で接続されていることを特徴とする半導体装置。 A stack type semiconductor device in which a plurality of devices are stacked on a frame substrate having a plurality of outer lead terminals,
A plurality of devices in which electrodes are arranged on the slope formed on the outer periphery are laminated on the frame substrate via an insulating adhesive,
A semiconductor device, wherein the electrode disposed on the slope and the outer lead terminal are connected by a lead wire. 複数のアウターリード端子を有するフレーム基板上に複数のデバイスを積層するスタックタイプの半導体装置の製造方法であって、
デバイスの電極が形成された半導体基板の外周に斜面を形成し、
該斜面に沿ってデバイスの電極を折り曲げ、
該デバイスを絶縁性接着剤を介して前記フレーム基板に複数個積層し、
斜面に配設された前記電極と前記アウターリード端子とをリード線で接続する、
各工程を具備したことを特徴とする半導体装置の製造方法。 A method of manufacturing a stack type semiconductor device in which a plurality of devices are stacked on a frame substrate having a plurality of outer lead terminals,
A slope is formed on the outer periphery of the semiconductor substrate on which the device electrode is formed,
Bend the electrode of the device along the slope,
Laminating a plurality of the devices on the frame substrate via an insulating adhesive,
Connecting the electrode disposed on the slope and the outer lead terminal with a lead wire;
A method of manufacturing a semiconductor device, comprising each step.
JP2008029917A 2008-02-12 2008-02-12 Semiconductor device and manufacturing method thereof Pending JP2009193983A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04247632A (en) * 1991-02-01 1992-09-03 Fujitsu Ltd Semiconductor device
JP2001118887A (en) * 1999-10-14 2001-04-27 Resuka:Kk Bonding strength testing device
JP2004063804A (en) * 2002-07-29 2004-02-26 Sharp Corp Semiconductor device, stacked type semiconductor device and manufacturing method thereof
JP2007134486A (en) * 2005-11-10 2007-05-31 Toshiba Corp Stacked semiconductor device and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04247632A (en) * 1991-02-01 1992-09-03 Fujitsu Ltd Semiconductor device
JP2001118887A (en) * 1999-10-14 2001-04-27 Resuka:Kk Bonding strength testing device
JP2004063804A (en) * 2002-07-29 2004-02-26 Sharp Corp Semiconductor device, stacked type semiconductor device and manufacturing method thereof
JP2007134486A (en) * 2005-11-10 2007-05-31 Toshiba Corp Stacked semiconductor device and its manufacturing method

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