JP2005327755A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2005327755A
JP2005327755A JP2004141747A JP2004141747A JP2005327755A JP 2005327755 A JP2005327755 A JP 2005327755A JP 2004141747 A JP2004141747 A JP 2004141747A JP 2004141747 A JP2004141747 A JP 2004141747A JP 2005327755 A JP2005327755 A JP 2005327755A
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Prior art keywords
semiconductor element
semiconductor
pad
pad electrode
wiring board
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JP2004141747A
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Japanese (ja)
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Fumito Ito
史人 伊藤
Toshitaka Akaboshi
年隆 赤星
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin semiconductor device wherein semiconductor elements are stacked. <P>SOLUTION: The semiconductor device is provided with a wiring board 1 having a wire connection pad 7; a first semiconductor element 2 that is provided with a bonding pad 7 as a pad electrode and is mounted on the wiring board 1 with a first adhesive layer 3 in between; a second semiconductor element 4 which is provided with a bonding pad 7 facing the bonding pad 7 of the first semiconductor element 2 and is mounted on the first semiconductor element 2 with a second adhesive layer 11 in between, and wherein the bonding pads 7 are joined with each other; and metallic thin wire 8 that connects the bonding pads of the first and second semiconductor elements 2 and 4 and the wire connection pad 7 of the wiring board 1, and electrically connects the first and second semiconductor elements 2 and 4 and the wiring board 1. In this case, the first semiconductor element 2 is directly connected with the second semiconductor element 4, so that the semiconductor elements 2 and 4 are unnecessary to be connected individually with the wiring board 1 through the metallic thin wire 8 and no plate member to ensure a space is needed. Therefore, a thin laminated semiconductor device can be easily manufactured. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は複数の半導体素子を積層した積層型の半導体装置及びその製造方法に関するものである。   The present invention relates to a stacked semiconductor device in which a plurality of semiconductor elements are stacked and a manufacturing method thereof.

小型・軽量の携帯情報機器等の機能拡大に伴い、半導体メモリーを複数個搭載した半導体装置を始めとして、複数の半導体素子を積層した小型、薄型の積層型半導体装置への要望が増している。   With the expansion of functions of small and light portable information devices, there is an increasing demand for small and thin stacked semiconductor devices in which a plurality of semiconductor elements are stacked, including a semiconductor device having a plurality of semiconductor memories.

図３は従来の積層型半導体装置を示す。配線基板１上に第１の半導体素子２が接続層３を介して実装され、第１の半導体素子２の上に第２の半導体素子４が板部材５を介して実装され、第１の半導体素子２及び第２の半導体素子４のボンディングパッド６がそれぞれ配線基板１のワイヤー接続用パッド７に金属細線８により電気的に接続されており、これら第１および第２の半導体素子２，３を保護する形で封止する封止樹脂９と外部接続用のボール１０とが設けられている。１１は接着層である（例えば特許文献１参照）。
特開２００２−３４３９２８号公報 FIG. 3 shows a conventional stacked semiconductor device. A first semiconductor element 2 is mounted on the wiring substrate 1 via a connection layer 3, and a second semiconductor element 4 is mounted on the first semiconductor element 2 via a plate member 5, and the first semiconductor The bonding pads 6 of the element 2 and the second semiconductor element 4 are electrically connected to the wire connection pads 7 of the wiring board 1 by the fine metal wires 8, respectively. The first and second semiconductor elements 2 and 3 are connected to each other. A sealing resin 9 for sealing in a protective form and a ball 10 for external connection are provided. Reference numeral 11 denotes an adhesive layer (see, for example, Patent Document 1).
JP 2002-343928 A

上記した従来の積層型半導体装置は、第１の半導体素子２と第２の半導体素子４との間に板部材５を配置することでスペースを形成し、第１の半導体素子２を金属細線８によって配線基板１に結線する一方で、第２の半導体素子４も別途に金属細線８によって配線基板１に結線することにより、同一サイズの第１の半導体素子２と第２の半導体素子４との積層を可能とした構造である。しかし半導体素子の積層数を増やしつつ半導体装置の薄型化が要求される現状で、下段の第１の半導体素子２の金属細線８接続のための板部材５の設置や上段の第２の半導体素子４から金属細線８接続を行うことは、薄型化を阻害する結果になっている。   In the conventional stacked semiconductor device described above, a space is formed by disposing the plate member 5 between the first semiconductor element 2 and the second semiconductor element 4, and the first semiconductor element 2 is connected to the metal thin wire 8. The second semiconductor element 4 is separately connected to the wiring board 1 by a metal thin wire 8 while being connected to the wiring board 1 by the above-described method, whereby the first semiconductor element 2 and the second semiconductor element 4 having the same size are connected. It is a structure that enables lamination. However, in the current situation where thinning of the semiconductor device is required while increasing the number of stacked semiconductor elements, the installation of the plate member 5 for connecting the thin metal wires 8 of the lower first semiconductor element 2 and the upper second semiconductor element Connecting the metal thin wire 8 from 4 results in inhibiting the thinning.

本発明は上記問題を解決するもので、半導体素子を積層した薄型の半導体装置を提供することを目的とする。   The present invention solves the above-described problems, and an object thereof is to provide a thin semiconductor device in which semiconductor elements are stacked.

上記課題を解決するために、本発明の半導体装置は、ワイヤー接続用パッドを有した配線基板と、パッド電極を有し、前記配線基板上に実装された第１の半導体素子と、前記第１の半導体素子のパッド電極に対向配置されるパッド電極を有し、前記第１の半導体素子上に接着層により実装され、前記パッド電極どうし接合された第２の半導体素子と、前記第１および第２の半導体素子のパッド電極どうしの接合部と前記配線基板のワイヤー接続用パッドとを結線して、前記第１の半導体素子と第２の半導体素子と配線基板とを導通させる金属細線とを備えた構成としたものである。これによれば、第１の半導体素子と第２の半導体素子との接続をダイレクトに行うため、第１および第２の半導体素子をそれぞれ配線基板に対して金属細線で接続する必要はなく、そのために従来のように板部材を用いてスペースを確保する必要もなく、積層型の半導体装置を薄型化可能である。   In order to solve the above problems, a semiconductor device of the present invention includes a wiring board having a wire connection pad, a first semiconductor element having a pad electrode and mounted on the wiring board, and the first semiconductor element. A second semiconductor element having a pad electrode disposed opposite to the pad electrode of the semiconductor element, mounted on the first semiconductor element by an adhesive layer, and joined to the pad electrodes; and the first and first semiconductor elements And a metal thin wire that connects the bonding portion between the pad electrodes of the semiconductor element and the wire connection pad of the wiring board to electrically connect the first semiconductor element, the second semiconductor element, and the wiring board. This is a configuration. According to this, since the first semiconductor element and the second semiconductor element are directly connected, there is no need to connect the first and second semiconductor elements to the wiring board with the metal thin wires, respectively. In addition, it is not necessary to secure a space by using a plate member as in the prior art, and the stacked semiconductor device can be thinned.

第１および第２の半導体素子に互いに対向するように形成された複数組のパッド電極の内、少なくとも一組において、一方のパッド電極は素子内のパターンと独立して形成し、他方のパッド電極は素子内のパターンと接続して形成して、前記他方のパッド電極を有した第１または第２の半導体素子が独立して配線基板と導通された構成としてもよい。   At least one of a plurality of sets of pad electrodes formed so as to face each other on the first and second semiconductor elements, one pad electrode is formed independently of the pattern in the element, and the other pad electrode May be formed in connection with a pattern in the element, and the first or second semiconductor element having the other pad electrode may be independently connected to the wiring substrate.

第１の半導体素子のパッド電極と第２の半導体素子のパッド電極とが、前記第２の半導体素子の実装に先立って少なくとも一方のパッド電極上に形成されたバンプを介して接合された構成としてもよい。必要に応じてバンプを設けて変形させながら接続することにより、安定した接続が可能となる。   A configuration in which the pad electrode of the first semiconductor element and the pad electrode of the second semiconductor element are joined via bumps formed on at least one of the pad electrodes prior to mounting the second semiconductor element. Also good. Stable connection is possible by providing bumps as necessary and connecting them while deforming them.

第１および第２の半導体素子間の接着層は、第１および第２の半導体素子に形成された複数組のパッド電極の内側に配置されたシート状接着層であってよい。また第１および第２の半導体素子間の接着層は、絶縁性のペーストよりなるものであってよい。   The adhesive layer between the first and second semiconductor elements may be a sheet-like adhesive layer disposed inside a plurality of sets of pad electrodes formed on the first and second semiconductor elements. The adhesive layer between the first and second semiconductor elements may be made of an insulating paste.

本発明の半導体装置の製造方法は、ワイヤー接続用パッドを有した配線基板上に第１の半導体素子をそのパッド電極を上向きにして実装し、前記第１の半導体素子のパッド電極と前記配線基板のワイヤー接続用パッドとを金属細線で結線し、前記第１の半導体素子上に、前記第１の半導体素子のパッド電極に対向配置されるパッド電極を有した第２の半導体素子を接着層を介して実装することを特徴とする。   According to a method of manufacturing a semiconductor device of the present invention, a first semiconductor element is mounted on a wiring board having a wire connection pad with the pad electrode facing upward, and the pad electrode of the first semiconductor element and the wiring board are mounted. The second semiconductor element having a pad electrode disposed opposite to the pad electrode of the first semiconductor element on the first semiconductor element is connected with an adhesive layer. It is characterized by mounting via.

第１の半導体素子のパッド電極と第２の半導体素子のパッド電極との内の少なくとも一方の上に予めバンプを形成し、前記第１の半導体素子のパッド電極上あるいはその上に形成されたバンプと前記配線基板のワイヤー接続用パッドとを金属細線で結線するようにしてもよい。バンプを変形させながらパッド電極どうしを接続させることで安定した接続を実現可能である。   A bump is formed in advance on at least one of the pad electrode of the first semiconductor element and the pad electrode of the second semiconductor element, and the bump formed on or on the pad electrode of the first semiconductor element. And a wire connection pad of the wiring board may be connected by a fine metal wire. A stable connection can be realized by connecting the pad electrodes while deforming the bumps.

対向するパッド電極間に配置されるバンプと金属細線との実装前の厚みの総和が第１および第２の半導体素子間の接着層の厚みより大きいのが好ましい。バンプと金属細線との実装前の総厚を接着層より厚くすることにより、バンプを変形させながら接続させる際の接触面積がより大きくなり、安定した接続を実現することが可能である。   It is preferable that the sum of the thicknesses before mounting of the bumps and the fine metal wires disposed between the opposing pad electrodes is larger than the thickness of the adhesive layer between the first and second semiconductor elements. By making the total thickness of the bumps and fine metal wires before mounting larger than the adhesive layer, the contact area when connecting the bumps while deforming them becomes larger, and stable connection can be realized.

本発明の半導体装置及びその製造方法は、半導体素子間はパッド電極どうし対向させて接続し、各半導体素子から配線基板への個別配線は一括して行う構成なので、半導体素子各々に対して金属細線による結線を行う従来法で要したスペースは不要であり、各半導体素子をパッド電極どうし対向配置するのに必要な最低限の厚みにて実装することができ、半導体素子を積層しながらも厚みを抑えた積層型半導体装置を実現可能である。   In the semiconductor device and the manufacturing method thereof according to the present invention, the semiconductor elements are connected so that the pad electrodes are opposed to each other, and the individual wiring from each semiconductor element to the wiring substrate is performed collectively. The space required by the conventional method of connecting by the above is unnecessary, and each semiconductor element can be mounted with the minimum thickness required to place the pad electrodes facing each other. A suppressed stacked semiconductor device can be realized.

以下、本発明の実施の形態を図面を参照しながら説明する。
図１は本発明の一実施形態における半導体装置の構成を示す（ａ）断面図および（ｂ）平面図、図２は同半導体装置の製造方法を示す工程断面図である。 Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1A is a sectional view and FIG. 2B is a plan view showing a configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view showing a method for manufacturing the semiconductor device.

図１（ａ）に示すように、この半導体装置は、ワイヤー接続用パッド７を有した配線基板１と、ボンディングパッド（パッド電極）６を素子面に有し、配線基板１上に実装された第１の半導体素子２と、ボンディングパッド（パッド電極）６を素子面に有し、第１の半導体素子２上に実装された第２の半導体素子４と、前記第１および第２の半導体素子２，４のボンディングパッド６どうしの接合部と前記配線基板１のワイヤー接続用パッド７とを結線した金属細線８とを備えている。また、第１の半導体素子２と第２の半導体素子４を保護する形で形成された封止樹脂９と外部接続用のボール１０とを備えている。   As shown in FIG. 1A, this semiconductor device has a wiring substrate 1 having wire connection pads 7 and a bonding pad (pad electrode) 6 on the element surface, and is mounted on the wiring substrate 1. A first semiconductor element 2, a bonding pad (pad electrode) 6 on the element surface, a second semiconductor element 4 mounted on the first semiconductor element 2, and the first and second semiconductor elements A thin metal wire 8 is provided that connects the bonding portion between the two and four bonding pads 6 and the wire connection pad 7 of the wiring board 1. Further, a sealing resin 9 formed to protect the first semiconductor element 2 and the second semiconductor element 4 and a ball 10 for external connection are provided.

詳細には、第１の半導体素子２は配線基板１上に素子面を上向きにして第１の接着層３により実装されている。第２の半導体素子４は、第１の半導体素子２上に互いの素子面が対向するように、素子面を下向きにして第２の接着層１１により実装されている。第１および第２の半導体素子２，４のボンディングパッド６は、図１（ｂ）に示すように素子面どうしが対向配置された状態で互いに対向する位置に形成されていて、バンプ１２を介して接合されている。   Specifically, the first semiconductor element 2 is mounted on the wiring substrate 1 by the first adhesive layer 3 with the element surface facing upward. The second semiconductor element 4 is mounted on the first semiconductor element 2 by the second adhesive layer 11 with the element surface facing downward so that the element surfaces face each other. The bonding pads 6 of the first and second semiconductor elements 2 and 4 are formed at positions facing each other with the element surfaces facing each other as shown in FIG. Are joined.

互いに対向する複数組のボンディングパッド６の内、所定の組においては、対向する双方が第１または第２の半導体素子２，４に対して電気的に導通したボンディングパッド６ａとして形成されていて、第１および第２の半導体素子２，４が一括して金属細線８を介して配線基板１と導通されている。他の組においては、一方は第１または第２の半導体素子２，４に対して電気的に導通したボンディングパッド６ｂとして形成され、他方は第２または第１の半導体素子４，２に対して電気的に導通を持たないダミーのボンディングパッド６ｃとして形成されていて、ボンディングパッド６ｂを有した第１または第２の半導体素子２，４が独立して金属細線８を介して配線基板１と導通されている。   Among a plurality of sets of bonding pads 6 that face each other, in a predetermined set, both of the facing pads are formed as bonding pads 6a that are electrically connected to the first or second semiconductor elements 2 and 4, The first and second semiconductor elements 2 and 4 are collectively connected to the wiring board 1 through the fine metal wires 8. In another set, one is formed as a bonding pad 6b electrically connected to the first or second semiconductor element 2 or 4, and the other is formed to the second or first semiconductor element 4 or 2. It is formed as a dummy bonding pad 6c having no electrical continuity, and the first or second semiconductor element 2 or 4 having the bonding pad 6b is electrically connected to the wiring substrate 1 through the metal thin wire 8 independently. Has been.

上記半導体装置の製造方法について説明する。
図２（ａ）は配線基板１を示し、素子搭載面にワイヤー接続用パッド７を有している。配線基板１は、リードフレームや有機基板、セラミック基板などの配線板である。この配線基板１上に、図２（ｂ）に示すように、第１の半導体素子２を素子面を上向きにして第１の接着層３を介して実装する。第１の接着層３としては、エポキシ系樹脂をベースとしたペースト状のものやシートタイプのものが使用される。 A method for manufacturing the semiconductor device will be described.
FIG. 2A shows the wiring board 1, which has wire connection pads 7 on the element mounting surface. The wiring substrate 1 is a wiring board such as a lead frame, an organic substrate, or a ceramic substrate. As shown in FIG. 2B, the first semiconductor element 2 is mounted on the wiring board 1 with the element surface facing upward via the first adhesive layer 3. As the first adhesive layer 3, a paste type or sheet type based on an epoxy resin is used.

次に、図２（ｃ）に示すように、第１の半導体素子２上のボンディングパッド６と配線基板１のワイヤ接続用パッド７とを金属細線８でワイヤボンディングする。このときには、第１の半導体素子２のボンディングパッド６上に予めバンプ１２を形成し、そのバンプ１２に対して配線基板１より金属細線８を打ち上げる方法をとることにより、安定した接続を得ることができる。   Next, as shown in FIG. 2C, the bonding pads 6 on the first semiconductor element 2 and the wire connection pads 7 on the wiring substrate 1 are wire-bonded with fine metal wires 8. At this time, a stable connection can be obtained by forming a bump 12 in advance on the bonding pad 6 of the first semiconductor element 2 and launching the fine metal wire 8 from the wiring board 1 to the bump 12. it can.

次に、図２（ｄ）に示すように、第２の半導体素子４を素子面を下向きにして第２の接着層１１を介して第１の半導体素子２上に実装する。第２の接着層１１は、第１の半導体素子２上でボンディングパッド６よりも内側に配置されるサイズとする。また、第２の半導体素子４のボンディングパッド６上に予めバンプ１２を形成しておき、互いのバンプ１２どうしを接合させる。このことにより、互いのボンディングパッド６ａ，６ｂとバンプ１２と金属細線８とを通じて、第１の半導体素子２と第２の半導体素子４との間、および第１の半導体素子２および第２の半導体素子４と配線基板１との間の導通を得ることができる。   Next, as shown in FIG. 2D, the second semiconductor element 4 is mounted on the first semiconductor element 2 via the second adhesive layer 11 with the element surface facing downward. The second adhesive layer 11 is sized to be disposed on the inner side of the bonding pad 6 on the first semiconductor element 2. Further, bumps 12 are formed in advance on the bonding pads 6 of the second semiconductor element 4 and the bumps 12 are joined to each other. Thus, the first semiconductor element 2 and the second semiconductor are connected between the first semiconductor element 2 and the second semiconductor element 4 through the mutual bonding pads 6a and 6b, the bump 12 and the thin metal wire 8. Conductivity between the element 4 and the wiring board 1 can be obtained.

その後に、図２（ｅ）に示すように、第１の半導体素子２，第２の半導体素子４、金属細線８などの配線基板１上の全構造物を封止樹脂９で覆って保護し、さらに、図２（ｆ）に示すように、封止樹脂９に背反する配線基板１の背面に外部接続用のボール１０を取り付けることによって、積層型の半導体装置が完成する。   Thereafter, as shown in FIG. 2E, the entire structure on the wiring substrate 1 such as the first semiconductor element 2, the second semiconductor element 4, and the metal thin wire 8 is covered with a sealing resin 9 to be protected. Further, as shown in FIG. 2 (f), a laminated semiconductor device is completed by attaching external connection balls 10 to the back surface of the wiring substrate 1 opposite to the sealing resin 9.

この積層型の半導体装置は、以上のように、第１の半導体素子２と第２の半導体素子４とを素子面どうしが向かい合うように実装し、各々のボンディングパッド６どうしダイレクトに接合させ、その接合部から配線基板１のワイヤ接続用パッド７へ金属細線８で一括して結線する構造なので、第１の半導体素子２と第２の半導体素子４とに個別に金属細線８による結線を行っていた従来法に比べて、結線数を少なくすることができ、また第１の半導体素子２と第２の半導体素子４との間および上段の第２の半導体素子４の上に結線のためのスペースを確保する必要もなく、容易に薄型に構成可能である。   As described above, this stacked semiconductor device has the first semiconductor element 2 and the second semiconductor element 4 mounted so that the element surfaces face each other, and the bonding pads 6 are directly bonded to each other. Since the thin metal wires 8 are collectively connected to the wire connection pads 7 of the wiring board 1 from the joint portion, the first semiconductor element 2 and the second semiconductor element 4 are individually connected by the thin metal wires 8. Compared to the conventional method, the number of connections can be reduced, and a space for connection is provided between the first semiconductor element 2 and the second semiconductor element 4 and above the second semiconductor element 4 in the upper stage. Therefore, it can be easily configured to be thin.

また複数組のボンディングパッド６の内、対向する一方にダミーのボンディングパッド６ｃを持った組を配しておくことで、第１の半導体素子２，第２の半導体素子４どうしの接続をとらずに配線基板１に個別に導通を引き出すことも可能である。   Further, by arranging a pair having a dummy bonding pad 6c on one of the opposing pairs of bonding pads 6, the first semiconductor element 2 and the second semiconductor element 4 are not connected to each other. In addition, it is possible to bring out electrical conduction to the wiring board 1 individually.

この２段積層型半導体装置のほか、３個以上の第１の半導体素子を積層する場合も、奇数段目の半導体素子を第１の半導体素子２と同様にして実装し、偶数段目の半導体素子を第２の半導体素子４と同様して実装することで、上記と同様に薄型の積層型半導体装置を構成可能である。   In addition to this two-stage stacked semiconductor device, even when three or more first semiconductor elements are stacked, the odd-numbered semiconductor elements are mounted in the same manner as the first semiconductor elements 2 and the even-numbered semiconductor elements are mounted. By mounting the element in the same manner as the second semiconductor element 4, a thin stacked semiconductor device can be configured as described above.

その他、本発明の要旨を逸脱しない範囲で、種々変形して実施可能である。   In addition, various modifications can be made without departing from the scope of the present invention.

本発明の半導体装置およびその製造方法は、半導体素子を複数個積層した積層型の半導体装置及びその製造方法として有用である。   The semiconductor device and the manufacturing method thereof of the present invention are useful as a stacked semiconductor device in which a plurality of semiconductor elements are stacked and a manufacturing method thereof.

本発明の一実施形態における半導体装置の構成図1 is a configuration diagram of a semiconductor device according to an embodiment of the present invention. 図１の半導体装置の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the semiconductor device of FIG. 従来の半導体装置の断面図Sectional view of a conventional semiconductor device

符号の説明Explanation of symbols

１ 配線基板
２ 第１の半導体素子
４ 第２の半導体素子
６ ボンディングパッド
７ ワイヤー接続用パッド
８ 金属細線
11 第２の接着層
12 バンプ DESCRIPTION OF SYMBOLS 1 Wiring board 2 1st semiconductor element 4 2nd semiconductor element 6 Bonding pad 7 Wire connection pad 8 Metal thin wire
11 Second adhesive layer
12 Bump

Claims (8)

ワイヤー接続用パッドを有した配線基板と、
パッド電極を有し、前記配線基板上に実装された第１の半導体素子と、
前記第１の半導体素子のパッド電極に対向配置されるパッド電極を有し、前記第１の半導体素子上に接着層により実装され、前記パッド電極どうし接合された第２の半導体素子と、
前記第１および第２の半導体素子のパッド電極どうしの接合部と前記配線基板のワイヤー接続用パッドとを結線して、前記第１の半導体素子と第２の半導体素子と配線基板とを導通させる金属細線と
を備えた半導体装置。 A wiring board having pads for wire connection;
A first semiconductor element having a pad electrode and mounted on the wiring board;
A second semiconductor element having a pad electrode disposed opposite to the pad electrode of the first semiconductor element, mounted on the first semiconductor element by an adhesive layer, and bonded to the pad electrodes;
The junction between the pad electrodes of the first and second semiconductor elements and the wire connection pad of the wiring board are connected to make the first semiconductor element, the second semiconductor element, and the wiring board conductive. A semiconductor device provided with a thin metal wire. 第１および第２の半導体素子に互いに対向するように形成された複数組のパッド電極の内、少なくとも一組において、一方のパッド電極は素子内のパターンと独立して形成し、他方のパッド電極は素子内のパターンと接続して形成して、前記他方のパッド電極を有した第１または第２の半導体素子が独立して配線基板と導通された請求項１記載の半導体装置。   At least one of a plurality of sets of pad electrodes formed so as to face each other on the first and second semiconductor elements, one pad electrode is formed independently of the pattern in the element, and the other pad electrode The semiconductor device according to claim 1, wherein the first or second semiconductor element having the other pad electrode is independently connected to the wiring substrate. 第１の半導体素子のパッド電極と第２の半導体素子のパッド電極とが、前記第２の半導体素子の実装に先立って少なくとも一方のパッド電極上に形成されたバンプを介して接合された請求項１または請求項２のいずれかに記載の半導体装置。   The pad electrode of the first semiconductor element and the pad electrode of the second semiconductor element are joined via bumps formed on at least one of the pad electrodes prior to mounting of the second semiconductor element. The semiconductor device according to claim 1 or 2. 第１および第２の半導体素子間の接着層は、第１および第２の半導体素子に形成された複数組のパッド電極の内側に配置されたシート状接着層である請求項１〜請求項３のいずれかに記載の半導体装置。   The adhesive layer between the first and second semiconductor elements is a sheet-like adhesive layer disposed inside a plurality of sets of pad electrodes formed on the first and second semiconductor elements. The semiconductor device according to any one of the above. 第１および第２の半導体素子間の接着層は、絶縁性のペーストよりなる請求項１〜請求項３のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the adhesive layer between the first and second semiconductor elements is made of an insulating paste. ワイヤー接続用パッドを有した配線基板上に第１の半導体素子をそのパッド電極を上向きにして実装し、
前記第１の半導体素子のパッド電極と前記配線基板のワイヤー接続用パッドとを金属細線で結線し、
前記第１の半導体素子上に、前記第１の半導体素子のパッド電極に対向配置されるパッド電極を有した第２の半導体素子を接着層を介して実装する
半導体装置の製造方法。 Mounting a first semiconductor element on a wiring board having a wire connection pad with the pad electrode facing upward;
The pad electrode of the first semiconductor element and the wire connection pad of the wiring board are connected with a fine metal wire,
A method of manufacturing a semiconductor device, wherein a second semiconductor element having a pad electrode disposed opposite to a pad electrode of the first semiconductor element is mounted on the first semiconductor element via an adhesive layer. 第１の半導体素子のパッド電極と第２の半導体素子のパッド電極との内の少なくとも一方の上に予めバンプを形成し、前記第１の半導体素子のパッド電極上あるいはその上に形成されたバンプと前記配線基板のワイヤー接続用パッドとを金属細線で結線する請求項６記載の半導体装置の製造方法。   A bump is formed in advance on at least one of the pad electrode of the first semiconductor element and the pad electrode of the second semiconductor element, and the bump formed on or on the pad electrode of the first semiconductor element. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the wire connection pad of the wiring board is connected with a thin metal wire. 対向するパッド電極間に配置されるバンプと金属細線との実装前の厚みの総和が第１および第２の半導体素子間の接着層の厚みより大きい請求項７記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the total thickness of the bumps and the fine metal wires arranged between the opposing pad electrodes before mounting is larger than the thickness of the adhesive layer between the first and second semiconductor elements.
JP2004141747A 2004-05-12 2004-05-12 Semiconductor device and its manufacturing method Withdrawn JP2005327755A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288003A (en) * 2006-04-18 2007-11-01 Sharp Corp Semiconductor device
CN107180807A (en) * 2016-03-11 2017-09-19 东芝存储器株式会社 Semiconductor device and its manufacture method
US9780049B2 (en) 2013-05-16 2017-10-03 Samsung Electronics Co., Ltd. Semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007288003A (en) * 2006-04-18 2007-11-01 Sharp Corp Semiconductor device
US9780049B2 (en) 2013-05-16 2017-10-03 Samsung Electronics Co., Ltd. Semiconductor package
CN107180807A (en) * 2016-03-11 2017-09-19 东芝存储器株式会社 Semiconductor device and its manufacture method

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