TW594562B - Branch instruction for processor - Google Patents
Branch instruction for processor Download PDFInfo
- Publication number
- TW594562B TW594562B TW089117907A TW89117907A TW594562B TW 594562 B TW594562 B TW 594562B TW 089117907 A TW089117907 A TW 089117907A TW 89117907 A TW89117907 A TW 89117907A TW 594562 B TW594562 B TW 594562B
- Authority
- TW
- Taiwan
- Prior art keywords
- branch
- instruction
- register
- bit
- scope
- Prior art date
Links
- 238000003860 storage Methods 0.000 claims description 24
- 238000012545 processing Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 12
- 238000012546 transfer Methods 0.000 claims description 10
- 206010011469 Crying Diseases 0.000 claims description 3
- 238000004590 computer program Methods 0.000 claims 10
- 238000011156 evaluation Methods 0.000 claims 4
- 108091006503 SLC26A1 Proteins 0.000 claims 1
- 238000012360 testing method Methods 0.000 claims 1
- 230000006870 function Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 108010072610 N-acetyl-gamma-glutamyl-phosphate reductase Proteins 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000000875 corresponding effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- LHMQDVIHBXWNII-UHFFFAOYSA-N 3-amino-4-methoxy-n-phenylbenzamide Chemical compound C1=C(N)C(OC)=CC=C1C(=O)NC1=CC=CC=C1 LHMQDVIHBXWNII-UHFFFAOYSA-N 0.000 description 1
- 230000001594 aberrant effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/321—Program or instruction counter, e.g. incrementing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
- Multi Processors (AREA)
- Executing Machine-Instructions (AREA)
- Debugging And Monitoring (AREA)
- Image Processing (AREA)
- Stored Programmes (AREA)
- Harvester Elements (AREA)
- Control Of Transmission Device (AREA)
- Document Processing Apparatus (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Fittings On The Vehicle Exterior For Carrying Loads, And Devices For Holding Or Mounting Articles (AREA)
Description
594562 五、發明說明(1) 【發明領域】 本發明係有關於電腦處理器的指令。 【習知技術說明】 種高 平行處理是計算程序中同時事件的資訊處理之 效率的方式。平行處理要求在電腦中許多經式的同時執 行。連續的處理或者序列的處理具有所有工作循序地完成 於單一 ί作站,鐘於管線處理具有工作完成於專業工作 1。、不官是執行於平行處理、管線或序向處理機器,電腦 =二碼$括分支’而其中指今串可以執行於序列中以及從 該序列分支至不同序歹彳的指令。 為讓本發明夕^ 顯易懂,下文特兴^述和其他目的、特徵、和優點能更明 說明如下:、牛較佳實施例,並配合所附圖式,作詳細 【圖式簡單說明】 圖。 中的微程式引 第1圖係使用處 、^ 第2圖係處理哭认态之通訊系統的方塊 第3圖係使用::詳細方塊圖。 擎功能單元的 、第1圖與第2圖的處理器 々,凡的方塊圖。 第4圖係微起 的圖。 的方塊圖 第5圖係顯示中的管線的方塊圖 第6圖俦_ - 於为支指令的示範格式 〜員不-般用途暫存器位址安排
第5頁 594562 五、發明說明(2) 【符號說明】 1 0〜通訊系統; 1 2〜運周硬體的多執行绪處理器; 13a〜10/100 BaseT八進位媒體存取控制; 1 3 b〜十億位元乙太網路裝置; 14〜PCI匯流排; 1 6〜記憶體糸統; 1 6a〜同步動態隨機存取記憶體(); 16b〜靜態隨機存取記憶體(^龍); 1 6 c〜快閃唯讀記憶體; 1 8〜第二匯流排·, 2 0〜核心處理器; 22〜功能微程式引擎 22a-22f〜微程式引擎; 24〜PCI匯流排界面; 2 6a〜同步動態隨機存取記憶體(SDR AM)控制器; 26b〜靜態隨機存取記憶體(SRAM)控制器; 27〜便條式記憶體; 28〜先進先出匯流排(FIFO Bus: FBUS )界面; 29a〜輸入與輸出FIFOs ; 29b〜輸入與輸出FIFOs ; 30〜先進系統匯流排(ASB )轉譯器; 3 2〜内部核心處理器匯流排;^ 34〜非公開匯流排; 38〜記憶體匯流排; 50〜精簡指令集運算(Rise )核心; 52〜十六仟位元組指令快取(ΐβ-kilobyte
1057-3410-PF.ptd 第6頁 594562 五、發明說明(3) 54〜八仟位元組資料快取(g-kilobyte data cache ); ^ 56〜預先擷取資料串缓衝區; 70〜控制儲存; 72〜控制器邏輯; 72a-72d 〜程式計數器(pr〇grani Counter: PC )單 元; 7 3〜指令解碼器; 7 4〜内容事件切換邏輯; 7 6〜執行盒資料路徑;
76a 〜算術邏輯單元(arithmetic logic unit: ALU ); 剷 76b〜一般用途暫存器組(generai -purpose 4 register set ); 78〜寫入移轉暫存器堆疊; 80〜讀取移轉暫存器堆疊; 【較佳實施例的詳細說明】 參照第1圖,通訊系統1 〇包括處理器1 2。在一實施例 中’處理器是運用硬體的多執行緒處理器12。處理器12被 連接至例如PCI匯流排14的匯流排,記憶體系統16以及第 二匯流排18。對於可以被分割成為平行子工作或函數的工 作’系統1 0是特別地有幫助的。特別地,對於頻寬導向而 非潛伏時間導向的工作,運用硬體的多執行緒處理器丨2是 有幫助的。運用硬體的多執行緒處理器12擁有多微程式引 擎22 ’母一微程式引擎22具有多硬體控制執行緒,多硬體
1057-3410-PF.ptd 第7頁 594562
控制執行緒可以被同時地啟動與獨立地活動於工作。 運用硬體的多執行緒處理器12也包括中 中央控制器20協助裝載用於運用硬、20, ^其=㈣之微程式碼控制以及完成其他通用電腦類型函 中」;=广異*,對於封包處理的額外支援,其 :微J式弓」擎22完成封包的較詳細處理,如同在邊界狀 ,。在一貫施例中,處理器20是運用Str〇ng奸 疋央國ARM公司的商標)。通用型微處理器〗。具有:乍 業糸、、'充。經過作業系統,處理器2〇可以呼叫函數以運算於 微程式弓丨擎22a-22f。處理器20可以使用任何支援的作業 系統,最好是即時作業系統。對於實現為Str〇ng A]架構 的核心處理 |§20,例如Microsoft-NT real-time, VXWorks與# CUS,可於網際網路得到的免費軟體作業系 統,之類的作業系統可以被使用。 用硬體的—多執行緒處理器丨2也包括複數功能微程式引 擎2 2a-22f。每一個功能微程式引擎(微程式引擎) 2 2a-22f維持硬體中的複數程式計數器與關連於程式計數 器的狀態。實際上,當在任何時間只有一個是真正地運 算’對應的一些執行緒集合可以被同時地啟動於每一個 微程式引擎22a-22f。 ' 每一微程式引擎22a-22f具有用於處理四個硬體執行 緒的能力。微程式引擎22a-22f與包括記憶體系統16及^ 流排界面24與28的共享資源一起運算。記憶體系統16包括 同步動態隨機存取記憶體(SDR AM)控制器26a與靜態隨機
594562 五、發明說明(5) ---
存取δ己憶體(SRAM )控制器26b。SDRAM記憶體i6a與SDRAM 控制器2 6 a通常被使用於處理大量的資料,例如,來自網 路封包的網路費甩的處理。SRAM控制器26b與SRAM記憶體 1 6b被使用在,例如電腦網絡封包處理、後稿語言處理 1§,或者作為用於如RAID磁碟儲存的儲存子系統的處理 器,或者用於低潛伏時間,快速存取工作,例如,存取查 詢表格,用於核心處理器2〇的記憶體等等。 處理器12包括連接處理器至第二匯流排18的匯流排界 面?8。在一實施例中,匯流排界面28連接處理器12至被通 稱為FBUS 18 (先進先出匯流排FiF〇 BUS )。處理器12包 括第二界面5例如PCI匯流排界面24,其連接存在於PCI匯 流排lj上的其他系統組件至處理器丨2。pc丨匯流排界面24 ^供南速資料路徑24a至SDRAM記憶體16a。經由該路徑, f料可以從SDRAM 16a經過PCI匯流排14快速地被移動,憑 藉直接。己隐體存取(direct memory access - DMA)移 轉。 一 母 力此早元被連接至一或多個内部匯流排。内部匯 二排疋雙數’二十二位元匯流排(換言之,一匯流排用於 讀,以及另一匯流排用於寫入)。運用硬體的多執行緒處 理為1 2也疋被構成以致在處理器1 2中的内部匯流排的頻寬 總和,過内部匯流排連接至處理器1 2的頻寬。處理器1 2包 括内部核=處理器匯流排32,例如先進系統匯流排(ASB )’ ^匯流排連接處理器核心至記憶體控制器26a、26b以 及至說明於下文中的先進系統匯流排(ASB )轉譯器30。
594562
ASB匯流排是所謂的先進微控制器匯流排架構(amba )的 子集合,AMBA是與Strong Arm處理器核心2〇 一起被使用。 處理器12也包括連接微程式引擎單元22至⑽倾控制器 2 6b、ASB轉譯器30與FBUS界面28的非公開匯流排34 (private bus )。記憶體匯流排38連接記憶體控制器 26a、26b至匯流排界面24與28以及記憶體系統16包括被使 用於開機運异等等的快閃唯讀記憶體丨6 c。 參照第2圖,每一個的微程式引擎22a —22f包括檢查旗 標以決定被運算於其上的可利用執行緒之仲裁器。來^微 程式引擎22a-22f的任何執行緒可以存取同步動態隨機存 取記憶體(SDRAM )控制器26a、靜態隨機存取記憶體 (SRAM )控制器26b或者先進先出匯流排(FBUS )界面 28。每一記憶體控制器26a與2 6b包括為了儲存未解決的 記憶體參照要求之複數佇列。在用於標示何時服務是被授 權的中斷旗標之外,FBUS界面28支援對於MAC裝置支援的 每一埠的傳送與接收旗標。FBUS界面28也包括完成從FBUS 進來封包的標頭處理之控制器28a。控制器28a設法得到封 包標頭並且完成於SRAM 16b中的微程式可編程序的來源/ 終點/協疋雜凑查詢(H a s h e d 1 ο 〇 k u p )(使用於位址平滑 核心處理器2 0存取共享資源。核心處理器2 q具有經由 匯流排32至SDRAM控制器26a '至匯流排界面24與至SRAM控 制為2 6 b。然而’為了存取微程式引擎2 2 a - 2 2 f以及移轉位 於任何微程式引擎22a-22f中的暫存器,核心處理器2〇經
594562
由A SB轉澤裔30跨過匯流排34而存取微程式引擎22a — 22f。 ASB轉譯器30可以實際上存在於FBUS界面28,但是邏輯上 是有區別的。ASB轉譯器3〇完成在FBUS微程式引擎移轉暫 存器位置與核心處理器位址(亦即ASB匯流排)之間的位 址轉澤以便心處理态2 0可以存取屬於微程式引擎2 2 a — 2 2 f 的暫存器。 雖然微程式引擎22可以使用暫存器組以交換資料如以 下所a兒明’便條式記憶體2 7也被提供以允許微程式引擎寫
出資料至記憶體而作為其他微程式引擎讀取。便條式記憶 體27是連接至匯流排34。 處理器核心2 0包括精簡指令集運算(R丨sc )核心5 〇, 精,指令集運算(RISC)核心50實現於五級管線而完成一 運算凡或兩運算元的單一週期位移於單一週期中,提供乘 法支援與三十二位元桶形位移支援。此RISC核心5〇是標準 Strong Arm®的架構,但是為了效能原因而被實現於五級 官線。處理器核心2 0也包括十六仟位元組指令快取 kilobyte instruction cache ) 52,八仟位元組資 料快取(8-kil〇byte data cache ) 54與預先擷取資料串
緩,區(prefetch stream buffer ) 56。核心處理器20 完 成算術運算平行於記憶體寫入與指令擷取。核心處理器2〇 ^由ARM所定義的ASB匯流排與其他功能單元接合。asb匯 流排是三十二位元雙向匯流排32。 " 參照第3圖,範例的微程式引擎22f包括控制儲存70, 其包括儲存微程式的RAM。微程式是可由核心處理器2〇所
594562 五、發明說明(8) 載入。微程式引擎22f也包括控制器邏輯72。控制器邏輯 72包括指令解碼器73與程式計數器(pr〇grain Counter: PC )單元7 2a-72d。四個微程式計數器72a-72d是保留於硬 體中。微程式引擎22f也包括内容事件切換邏輯74。内容 事件邏輯7 4接收來自每一個共享資源的訊息(例如, SEQj—EVENT一RESPONSE ; FBI—EVENT—RESPONSE ; SRAM—EVENT一RESPONSE ; SDRAM—EVENT—RESPONSE ;與 ASB—EVENT—RESPONSE),共享資源例如SRAM 26a,SDRAM 26b,或處理器核心20,控制與狀態暫存器等等。這些訊 息提供被要求的功能是否已經完成的資訊。基於由執行緒 所要求的功能是否已經完成與兩信號通知完成,執行緒需 要等待該完成信號,以及假如執行緒被賦予運算的能力, 接著執行緒被放置於可適用執行緒名冊中(未顯示)。微 私式引擎22f可以具有四個可適用執行緒的最大值。 除了局部至執行中的執行緒的事件信號之外,微程式 引擎22a-22f利用總體的信號發送狀態。具有信號發送狀 態,執行中的執行緒可以播送信號狀態至所有的微程式引 擎22a-22f。接收要求可適用(Receive Request
Available )信號,在微程式引擎22a — 22f中的任何與所有 執行緒可以分支於這些信號發送狀態上。這些信號^送狀 態可以被使用以決定資源的可適用性或者是否資源是到期 而可以服務。’ 、 内容事件邏輯74具有對於四個執行緒的仲裁。在一實 施例中’仲裁是循環赛機制。其他技術可以被使同,包社
594562 五、發明說明 g) ,先;^排序或者權重公正排序。微程式引擎也包括執 ^ 盒資料路徑76 (execution box data path),執行盒 ^料路位76包括异術邏輯單元(arithmetic i〇gic unit 76a 與般用途暫存器組(general-purpose register =V^7613。异術邏輯單元76a如同移位函數般地完成算術 〃邏輯函數。算術邏輯單元包括條件程 J說明的指令所使用。暫存器組76b具有相當大數目的皮一乂 斟:ί暫存15,—般用途暫存器是被開窗以至於它們是相 址的。微程式引擎⑵也包括寫入移轉 80 : 了、走;*、、項取移轉暫存器堆疊80。這些暫存器78與 80也疋被開献以至於它們是相對地與絕 入:轉暫存器堆疊78是其中寫入資料至 ; 暫存器堆疊8°是用於從共享資源傳回資 26a Ϊ同時發生或隨後,來自例如SRAM控制器 供至事件仲裁器?4,其了貝二之 可適用或已經被送出的執行緒。移 I貝付疋 兩者;連接至執行盒與80 “第4圖,微程式引擎資料路 (5-stage mlcro-pipeHne ) 82。 倣吕綠 的查詢82a’暫存器列位址的形成82b::i;=n; 元讀取82c,ALU移位或比較運算咖,*社暫存/列的運算 及藉由假設暫存器是實現為暫存器列(而咖『二
1057-^410-PF nrd 第13頁 寫回8 2 e。藉由提供寫回資料旁路進入ai^ ,存器的 594562
式引擎可以完成同時發生的暫存器列讀取與寫入, 地隱藏寫入運算。 其完全 ,支援於微程式引擎22a-22f中的指令集支援條件分 。最差狀況的條件分支潛伏時間(不包括跳躍)笋 當分支決定是由前一微程式控制指令所指定的條件^ 1 的結杲。潛伏時間顯示於以下第1表中: 第1表
1 2 3 4 5 6 7 8 微儲存査詢 nl cb n2 XX bl bl b3 b4 暫存器位址產生 nl Cb XX XX bl b2 b3 暫存器縱列査詢 Nl cb XX XX bl b2 ALU/位移器/cc nl cb XX XX bl 寫Θ M2 nl cb XX -—. XX 其中nx疋預先分支微程式字組(ηι設定cc,s ) 條件分支,bx是後分支微程式字組以及χχ是被 2, 式字組 的微程 如第1表所示,直到週期4時nl的條件碼被設定,、 分支決定可以被做出(在此狀況中導致分支路径被杳$及 週期5中)。微程式引擎帶來2週期分支潛伏時間損^珣於 為其必須終止在管道中的運算n2與n3 (該2微程式^矣’因 接位於分支後),在分支路徑開始以運算1^裝滿"管’曾且直 前。假如分支不發生,沒有微程式字組被終止/以;二二 594562 五、發明說明(11) 常地繼續。微程式引擎具有幾個機制以減少或消除實際的 分支潛伏時間。 微程式引擎支援可選擇的被延遲分支。可選擇的延遲 分支是當微程式引擎允許在分支之後的1或2微程式指令發 生於分支生效之前(即分支的效應在時間上是被延遲地 )。因此,假如有用工作可以被發現而填充在分支微程式 字組之後被浪費的週期,於是分支潛伏時間可以被隱藏。 1週期延遲分支顯示於第2表中,此處n2被允許執行於cb之 後,但是於bl之前: 第2表
1 2 3 4 5 6 7 8 微儲存査詢: nl cb n2 XX bl b2 b3 b4 暫存器位址產生 nl cb nl XX bl b2 b3 暫存器縱列査詢 nl cb n2 XX bl b2 ALU/位移器/cc nl cb n2 XX bl 寫ΕΪ nl cb n2 XX 2週期延遲分支顯示於第3表中,此處n2與n3兩者被允 許完成在至Μ的分支之前。要注意的是2週期分支延遲僅 被允許在當條件碼被指定於在分支之前的微程式字組。
594562 五、發明說明(12) 第3表 1 2 3 4 5 6 7 8 9 微儲存査詢 nl cb n2 n3 bl b2 b3 b4 b5 暫存器位址產生 nl cb n2 n3 bl bl b3 b4 暫存器縱列查詢 nl cb n2 n3 bl b2 b3 ALU/位移器/cc nl cb n2 n3 bl bl 寫回 nl cb n2 n3 bl 微程式引擎也支援條件碼估算。假如做出分支決定的 條件碼是在分支之前設定2或者更多微程式字組,然後1週 期的分支潛伏時間可以被消除’因為分支決定可以在早於 1週期之前被做出,如同第4表中。 一 第4表
1 2 3 4 5 6 7 8 微儲存査詢 nl nl cb XX bl bl b3 b4 暫存器位址產生 nl n2 cb XX bl b2 b3 暫存器縱列査詢 nl n2 cb XX bl hi ALU/位移器/cc nl n2 cb XX bl 寫® nl n2 cb XX 在此例子中,η 1設定條件碼以及n2不設定條件碼。因 而,分支決定可以於週期4做出(而不是週期5 ),而消除
1057-3410-PF.ptd 第16頁 594562 五、發明說明(13) 週期的分支潛伏時間。在第5表中的例子中,1週期分支 延,與條件碼的提前設定被相互結合而完全地隱藏分支潛 伏^間。亦即,條件碼(cc’ s )被設定於1週期延遲分去 之前的2個週期。 第5表 1 2 3 4 5 6 7 8 微储存査詢| N1 cb n2 n3 bl b2 b3 b4 暫存器位址產生 nl n2 cb n3 bl b2 b3 暫存器縱列査詢 nl n2 cb n3 bl b2 ALU/位移器/cc nl n2 cb n3 bl 寫® nl n2 cb n3 在條件碼不能被提前設定的狀況中(它們被設定於八 ▲支之前的微程式字組中)’微程式引擎支援分支二二而$ 試減少1週期的暴露的保留分支潛伏時間。藉由,,猜測π分 支路徑或者循序路徑,在明確地知道哪一路徑被^行之β 前,微程式定序器預先擷取被猜測路徑的1週期/假如猜 測正確,1週期的分支潛伏時間被消除如第6表中所•叹示。月 594562 五、發明說明(14) 第6表 猜測分支發生/分支發生 1 2 3 4 5 6 7 8 微儲存査詢 nl cb nl bl bl b3 b4 b5 暫存器位址產生 nl cb XX bl hi b3 b4 暫存器縱列査詢 nl cb XX bl bl b3 ALU/位移器/cc nl cb XX bl bl 寫回 nl cb XX bl 假如微程式碼猜測分支發生不正確時,微程式引擎依 然只有浪費1週期,如第7表中 第7表 積測分支發生/分支不發生
1 2 3 4 5 6 7 8 微儲存査詢 nl cb nl XX nl n3 n4 n5 暫存器位址產生 nl cb nl XX n2 n3 n4 暫存器縱列査詢 nl cb nl XX n2 n3 ALU/位移器/cc nl cb nl XX n2 寫回 nl cb nl XX 無論如何,當微程式碼猜測一個分支是不發生時,潛 伏時間損失是不同地分佈。如同在第8表中,對於猜測分
1057-3410-PF.ptd 第18頁 594562 五、發明說明(15) 支不發生/分支是不發生時是不浪費週期。 第8表 1 2 1 3 4 5 6 7 S 微儲存査詢 nl cb nl n2 n3 n4 n5 n6 暫存器位址邊立 nl cb nl n2 n3 n4 n5 暫存器縱列查詢 nl cb nl n2 n3 n4 ALU/位移器/cc nl cb nl n2 n3 寫® nl cb nl n2 無論如何,如同在第9表中,對於猜測分支不發生/分 支是發生時有2浪費的週期。 第9表
1 2 3 4 5 6 7 8 微儲存査詢 nl cb nl XX bl b2 b3 b4 暫存器位址產生 nl cb XX XX bl bl b3 暫存器縱列査詢 nl cb XX XX bl bl ALU/位移器/cc nl cb XX XX bl 寫回 nl cb XX XX 微程式引擎可以結合分支猜測與1週期分支延遲而進 一步地改善結果。對於猜測分支發生與1週期延遲分支/分 支是發生是在第10表中。
1057-3410-PF.ptd 第19頁 594562 五、發明說明(16) 第10表 1 2 3 4 5 6 7 8 微儲存査詢 nl cb n2 bl bl b3 b4 b5 暫存器位址產生 nl cb n2 bl bl b3 b4 暫存器縱列査詢 nl cb n2 bl b2 b3 ALU/位移器/cc nl cb n2 bl b2 寫回 nl cb nl bl 在以上狀況中,2週期的潛伏時間是藉由n2的執行以 及藉由正確地猜測分支方向而被隱-屬^。 假如微程式碼猜測不正確,如以下所示,對於猜測分 支發生1週期延遲分支/分支不發生,1週期的潛体時間維 持浪費,如同在第11表中。 第11表 1 2 3 4 5 6 7 δ 9 微儲存査詢 nl cb n2 XX n3 n4 n5 n6 n7 暫存器位址產生 nl cb n2 XX n3 n4 n5 n6 暫存器縱列査詢 nl I cb ! nl XX n3 n4 n5 ALU/位移器/cc nl cb n2 XX n3 n4 寫SJ nl cb n2 XX n3 假如微程式碼正確地猜測分支不發生,然後管線循序
1057-3410-PF.ptd 第20頁 594562 五、發明說明(17) 地流通於正常未受到擾亂的狀況。假如微程式碼不正確地 猜測分支不發生’微程式引擎再次浪費1週期的無產出執 行,如第12表中所示。 第12表 精測分支不發生/分支發生。 1 2 ] 3 Γ 4 5 6 7 1 8 9 微儲存査詢 nl cb nl XX bl bl b3 b4 b5 暫存器位址產生 nl cb n2 XX bl b2 b3 b4 暫存器縱列査詢 nl cb n2 XX bl b2 b3 ALU/位移器/cc nl cb n2 XX bl hi 寫回 nl cb n2 XX bl 其中nx是預先分支微程式字組(nl設定cc,s cb是條件分支 bx是後分支微程式字組 XX是被終止的微程式字組 間, 的結 在跳躍指令的狀況中,招致3額外週期的潛伏時 因為分支位址是未知的直到跳躍位於ALU級中的日 尾(第13表)。 4
1057-3410-PF.ptd 第21頁 594562
第13表 1 2 3 4 5 6 7 8 9 微儲存査詢 N1 jp XX XX XX jl J2 J3 J4 暫存器位址產生 nl jp XX XX XX jl J2 j3 暫存器縱列査詢 nl jp XX XX XX jl J2 ALU/位移器./cc nl jp XX XX XX jl 寫回 nl jp XX XX XX 弟D圖 佩狂: 參 指令, 支援分 類分支 使用作 中的位 在此實 指定於 通 中處理 算。此 可以從 支程式 BR 指令, --Μ · ·…一π %,刀、叉 例如分支於條件程式碼之上。此外,微程式?丨擎也 支於任何特定位元被設定或清除的分支指令。此種 指令允許程式設計師具體指定暫存器的哪_位元被 為分支控制位元。指令格式包括具體指定在長字組 ,位置的位元位置襴位(bit —p〇siti〇n Heid)。 =中的有效位元位置是位元〇 : 3丨。分支目標是且 指令中的標籤。 /、 =分支指令需要處理器位移位元進入控制路輕,1 二,^來自ALU的條件程式碼,以及完成分支運,、 二採2 t 5許分支程式碼的可觀察性。因此,分支 ς = 2貧料路徑被控,Μ 理器 碼進入控制路徑。 雅㈤刀 當由浐—BSET是分支至特定標籤上的指令之分支 田°曰7所具體指定的暫存器特定位元是被清除或
594562 五、發明說明(19) 設定時。這些指令設定條件程式碼。 格式:br—bclr[reg,bit —position,label#], opt i ona1 — token br一bset[reg, bit—position, label#], opt i ona1_token 欄位reg A是保留運算元的内容相關移轉暫存器或一 般用途暫存器的位址。攔位bit_p〇sition是具體指定在長 字組中的位元位置的數字。位元〇是最低有效位元。有效 的bit_position數值是0至31。欄位label#是相對應分支 至指令位址的符號標藏。數值〇pti〇nal_token可以具有幾 種數值。由程式設計師根據編製程序考慮而選擇數值。記 號(token)可以是: 延遲1 (defer 1),在完成分支運算之前,執行在分 支指令以後的指令。 延遲2 (defer 2),在完成分支運算之前,執行在分 支指令以後的2個指令。(在一些實行中不被允許與猜測 分支(guess一branch )。) 延遲3 (defer 3),在完成分支運算之前,執行在分 支指令以後的2個指令。(在一些實行中不被允許與猜測 分支(guess—branch ) 〇 ) 另一記號(token )可以是ff猜測分支 (guess—branch ),,,其導致分支指令預先擷取用於’’分支 發生’'條件的指令而不是下一個循序的指令。此記號猜測
1057-3410-PF.ptd 第23頁 594562 五、發明說明(20) 分支(guess—branch )可以與延遲記號一起被使用,例如 延遲1而改善效能。在一些結構中這或許是不允許與延遲2 或延遲3。 參照第6圖,兩種存在的暫存器位址分隔是本地可使 用暫存’以及可被所有微程式引擎使周的總體可使用暫 存器。一般用途暫存器(GPRs)被實現為兩分隔儲存所 (A儲存所與b儲存所),其位址是一字組接一字組為才姐 地相互插入以致於A儲存所暫存器具有lsb = 〇,以及B儲存 =暫存器具有lsb = l。每一儲存所有能力完成同時讀取與 寫入兩不同字組於其儲存所内部。 一 =過儲存所A與B,暫存器組76b也被組織成為32個暫 四:窗口76b"6b3 ’對於每一執行緒是相對地可 的。因此,執行緒〇將找尋其暫存器〇於77&之卜 ί 1」Γ緒1將找尋其暫存器0於7技之上(暫存二 執行緒2私找尋其暫在哭Q於^ γ 執杆缺q4 了 … 上(暫存器64 ), ΪΓβ Λ ,存器0於77d之上(暫存器96)。相掛 存與位置但是存取暫存器的不同窗口 = =控制儲 用雙咖S於微程式引擎22f中,:成二同功能。 與儲存所定址的使用提供必需的讀取頻寬自口定址 廷些開窗暫存器不必從内容開關 =,3於内容調換縱列或堆疊推存資 〇週:耗用的:容切換具有對於從-内容改ίί:消 U週期耗用時間土 I主另一内交ίΛ 町间相對暫存器定址劃分暫在哭μ ‘ Μ谷的 仔器儲存所成為 1057-3410-PF.ptd 594562 五、發明說明(21) __ 跨過一般用途暫存5§沾 取任何相關於窗口起::址寬度的窗口。相對定址允許存 架構中,㊣中藉由提窗口。絕對定址也被支援於此 對暫存器或許可以被任二f f的精確位址,任何一者的絕 取決於微程式字組的::緒:f取。 可以發生於兩種模式。兩二了般用途暫存器78的定址 式中,暫存器位址的定址β =:疋絕對與相對。在絕對模 源欄位中(a6-a0或b6-b〇 接地具體指定於7位元來 第14表 ’如第14表中所示:
-4---^ u» α^—± 暫存器位址被直接地具體指定於8朽- Λ . 疋^位A目的攔位中 (d7-d0 )第 1 5 表·
594562 五、發明說明(22) 第15表 7 6 5 4 3 2 1 0 AGPR: d7 d6 d5 d4 d3 d2 dl dO d7=0, d6=0 BGPR: d7 d6 d5 d4 d3 d2 dl dO d7=0? d6=l SRAM/ASB: d7 d6 d5 d4 d3 d2 dl dO d7=l,d6=0, d5=0 SDRAM: d7 d6 d5 d4 d3 d2 dl dO ¢17=1,(16==(^(^5==1 假如<a6:a5> = l,l,<b6:b5> = l,l,<d7:d6> = l,l,接 著較低位元被詮釋為内容相關位址欄位(說明於下文中 )。當非相關A或B來源位址被具體指定於A,B的絕對欄位 中,只有SRAM/ASB與SDRAM位址空間的較低一半可以被定 址。實際上,讀取絕對SRAM/SDRAM裝置具有有效位址空 間;無論如何,因為此限制不應用至目的襴位,寫入 SRAM/SDRAM依然使用完整位址空間° 在相對模式中,定址一個特定位址是在内容空間内部 由5位元來源欄位(a4-aO與b4-bO)第16表所定義的偏移 量:
1057-3410-PF.ptd 第26頁 594562 五、發明說明(23) 第16表 7 6 5 4 3 2 1 0 AGPR: a4 0 context a3 a2 al aO a4=0 BGPR: b4 1 context b3 b2 bl bO b4=0 SRAM/ASB: ab4 0 ab3 context b2 bl abO ab4=l,ab3=0 SDRAM: ab4 0 ab3 |contextj b2 bl abO ab4=l,ab3=l 或者如同由6位元目的欄位中(d5-d0)第17表所定 義: 第17表 7 6 5 4 3 2 1 0 AGPR: d5 d4 context D3 d2 dl dO d5=0?d4^0 BGPR: d5 d4 context B3 d2 dl dO (β=0,όΦ=0 SRAM/ASB: d5 d4 d3 Context d2 dl dO d5=l,dM),d3=0 SDRAM: d5 d4 d3 context d2 dl dO (!5=1,άΦ=0,(Β=1 假如<d5:d4> = l,1,則目的位址不定址於一有效暫存 器,因此,沒有目的運算元被寫回。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作更動與潤飾,因此本發明之保護範圍當 視後附之申請專利範圍所界定者為準。
1057-3410-PF.ptd 第27頁
Claims (1)
- 替換頁 9^7 Ά1 曰丨案號89117907_?3年工月7曰 修正本_ 六、申請專利範圍 1. 一種電腦程式產品,實作於一可執行的資訊載體 中,用以使一資料處理裝置執行一分支指令,將一特定暫 存器中之一位元指定為一分支控制位元,以及在當該位元 被設定或清除時,將一指令串分支至一目標指令。 2. 如申請專利範圍第1項所述之電腦程式產品,進一 步地包括: 一位元位置欄位,用以指定一暫存器中一長字組中的 該分支控制位元的一位元位置。 3. 如申請專利範圍第1項所述之電腦程式產品,進一 步地包括: 一分支目標欄位,其具體指定為一標籤。 4. 如申請專利範圍弟1項所述之電腦程式產品’進一 步地包括: 可程式化之一選項記號,在分支至該目標指令之前, 先行執行緊隨該分支指令後的i個指令。 5. 如申請專利範圍第1項所述之電腦程式產品,進一 步地包括: 可程式化之一選項記號,在分支至該目標指令之前, 先行執行緊隨該分支指令後的i個指令,其中i係為一、二 或三。 6. 如申請專利範圍第1項所述之電腦程式產品,其中 該暫存器是保留運算元的内容相關移轉暫存器或一般用途 暫存器。 7.如申請專利範圍第1項所述之電腦程式產品,進一 步地包括:1057-3410-PFl.ptc 第28頁 5|f6!替換頁拳:Γ月7』 盡H 89117907 曰 修正 六、申請專利範圍 可程式化之一選項記號,非用以指出下一個循序指 令’而是用以指出為一分支發生(branch taken)條件預 先擷取的一猜測分支(g u e s s — b r a n c h )。 、 8·如申請專利範圍第1項所述之電腦程式產品,進_ 步地包括: _ 可程式化之一第一選項記號,在分支至該目標指令之 刚’先行執行緊隨該分支指令後的i個指令。 、t第一遠項記號,非用以指出下一個循序指令,而是 f二2,為~分支發生(branCh taken)條件預先操取的 月〆、刀支(guess —branch ) 〇 該暫9存:! 專利ϊ圍第1項所述之電腦程式產品’其中 的。w用於決定該分支運算之位元,係具有可選擇性 分支2發H專,範圍第1項所述之電腦程式產品,其中 的一位元的結果而=根據評估一處理11中之一資料路徑中 \1 · 一種運作處理器的方法,包括: 定位元;以^疋使用作為分支控制位元的特定暫存器的特 完成:ΐΐ;定暫存器的該特定位元是被設定或者清除, 位元2置如是申^7專括H圍第η項所述之方法,其中該特定 13 /\ 暫存器中的長字組中。 括:· °申請專利範圍第η項所述之方法,進一步地包1057-341〇-PFl.ptc 第29頁 I正替換頁 _ 案號 89]17Qn7 六、f言f專利圍 分支至具體指定作為在 位上的指令。 伯7 T 曰 修正 的標籤的分支目標攔 1 4 ·如申請專利範 位元是由程式設計師所具體指員定所述之方法’其中該特定 括广·”請專利範圍第U項所述之方法,進一步地包 根據評估其由程式設 分支運算之前,執行在 的4項兄號,在完成 刀克心令執行以後的i個數目指 哭是1伴6留如運申曾請專Λ範圍第11項所述之方法,其中該暫存 口…運异兀的内容相關移轉暫存器或一般用适 1 7 ·如申請專利範圍第1 1 令 般用途暫存 括: 項所述之方法,進一步地包 預先^^式:"師所設定並且其具體指定猜測分支 = nch Prefetch)用於該”分支發生"擷取分支發生指令。 仏盾“令的選項記號’預先 I8.如申請專利範圍第11項所述之方法,進一步地包括·· 士根據評估其由程式設計師所設定的第一選項記號,在儿成刀支運异之4,執行在該分支指令執行以後的丨個 目指令;以及根據其由程式設計師所設定並且其具體指定猜測分支 預先#貞取(gUes s_branch prefetch)用於該"分支發生” m 1057-3410-PFl.ptc 第30頁 _ k 號 891]7卯7_ 六 1 2--I 你 Γ£ 條件的該指令而不是該下一 預先擷取分支發生指令。 序指令的第二選項記號, 1 9 ·如申請專利範圍第】〗 、 允許程式設計師選擇該特 ,所。述之方法,其t該指令 該分支運算。 存為的哪一位元使用於決定 20·如申請專利範圍第 暫存器堆疊 算術運算單元 程式控制貯存 處理器的資料路徑中的位皱所述之方法,其中根據在 2】· 一種處理器,包括:、^、估而發生分支評估。 元 評估該暫存器堆疊 該特定位元被指定 2特定該暫存器中的特定位 其中該特 進—步地 特定該暫存器的該】為分支控制位元;以及 分支指令所指定的分支運j蜱兀是被設定或清除,完成由 2 2 .如申請專利 定位元是在包括於—二= 項所,二 &如中請專利範^暫存$的長子組中 包括: Ν ^ 2 1項所述之處理器 【支:申?專位利範其= 定位元是由程式設計師;t所述之處理裔’ I中該特 25·如申請專利範圍第21H°考 fiiiiSiSiiii—^轉暫存益或一^^^ 1057-3410-PFl.ptc 第31頁1057-3410-PF1.pic 第32頁
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15196199P | 1999-09-01 | 1999-09-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW594562B true TW594562B (en) | 2004-06-21 |
Family
ID=22540994
Family Applications (11)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW089117903A TW559729B (en) | 1999-09-01 | 2000-09-01 | Instruction for multithreaded parallel processor |
TW089117904A TW475148B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for processor architecture |
TW089117900A TW486666B (en) | 1999-09-01 | 2000-10-18 | Register set used in multithreaded parallel processor architecture |
TW089117902A TW571239B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for multithreaded processor |
TW089117911A TW548584B (en) | 1999-09-01 | 2000-10-18 | Fast write instruction for micro engine used in multithreaded parallel processor architecture |
TW089117906A TWI221251B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for processor |
TW089117905A TW569133B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for processor |
TW089117910A TW486667B (en) | 1999-09-01 | 2000-10-18 | Memory reference instructions for micro engine used in multithreaded parallel processor architecture |
TW089117901A TWI220732B (en) | 1999-09-01 | 2000-10-18 | Local register instruction for micro engine used in multithreaded parallel processor architecture |
TW089117912A TW546585B (en) | 1999-09-01 | 2000-10-18 | Method of operating a processor and computer program product |
TW089117907A TW594562B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for processor |
Family Applications Before (10)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW089117903A TW559729B (en) | 1999-09-01 | 2000-09-01 | Instruction for multithreaded parallel processor |
TW089117904A TW475148B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for processor architecture |
TW089117900A TW486666B (en) | 1999-09-01 | 2000-10-18 | Register set used in multithreaded parallel processor architecture |
TW089117902A TW571239B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for multithreaded processor |
TW089117911A TW548584B (en) | 1999-09-01 | 2000-10-18 | Fast write instruction for micro engine used in multithreaded parallel processor architecture |
TW089117906A TWI221251B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for processor |
TW089117905A TW569133B (en) | 1999-09-01 | 2000-10-18 | Branch instruction for processor |
TW089117910A TW486667B (en) | 1999-09-01 | 2000-10-18 | Memory reference instructions for micro engine used in multithreaded parallel processor architecture |
TW089117901A TWI220732B (en) | 1999-09-01 | 2000-10-18 | Local register instruction for micro engine used in multithreaded parallel processor architecture |
TW089117912A TW546585B (en) | 1999-09-01 | 2000-10-18 | Method of operating a processor and computer program product |
Country Status (10)
Country | Link |
---|---|
US (1) | US7421572B1 (zh) |
EP (7) | EP1236092A4 (zh) |
CN (7) | CN1184562C (zh) |
AT (2) | ATE475930T1 (zh) |
AU (11) | AU7340700A (zh) |
CA (7) | CA2386562A1 (zh) |
DE (2) | DE60044752D1 (zh) |
HK (8) | HK1046049A1 (zh) |
TW (11) | TW559729B (zh) |
WO (8) | WO2001016713A1 (zh) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7546444B1 (en) | 1999-09-01 | 2009-06-09 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
US7681018B2 (en) | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US7292586B2 (en) | 2001-03-30 | 2007-11-06 | Nokia Inc. | Micro-programmable protocol packet parser and encapsulator |
US6785793B2 (en) | 2001-09-27 | 2004-08-31 | Intel Corporation | Method and apparatus for memory access scheduling to reduce memory access latency |
US7360217B2 (en) * | 2001-09-28 | 2008-04-15 | Consentry Networks, Inc. | Multi-threaded packet processing engine for stateful packet processing |
US7069442B2 (en) * | 2002-03-29 | 2006-06-27 | Intel Corporation | System and method for execution of a secured environment initialization instruction |
US7437724B2 (en) * | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
GB2409062C (en) | 2003-12-09 | 2007-12-11 | Advanced Risc Mach Ltd | Aliasing data processing registers |
US7027062B2 (en) * | 2004-02-27 | 2006-04-11 | Nvidia Corporation | Register based queuing for texture requests |
US9038070B2 (en) | 2004-09-14 | 2015-05-19 | Synopsys, Inc. | Debug in a multicore architecture |
GB0420442D0 (en) * | 2004-09-14 | 2004-10-20 | Ignios Ltd | Debug in a multicore architecture |
SE0403128D0 (sv) * | 2004-12-22 | 2004-12-22 | Xelerated Ab | A method for a processor, and a processor |
US8028295B2 (en) | 2005-09-30 | 2011-09-27 | Intel Corporation | Apparatus, system, and method for persistent user-level thread |
US7882284B2 (en) * | 2007-03-26 | 2011-02-01 | Analog Devices, Inc. | Compute unit with an internal bit FIFO circuit |
US7991967B2 (en) * | 2007-06-29 | 2011-08-02 | Microsoft Corporation | Using type stability to facilitate contention management |
US9384003B2 (en) * | 2007-10-23 | 2016-07-05 | Texas Instruments Incorporated | Determining whether a branch instruction is predicted based on a capture range of a second instruction |
US9207968B2 (en) * | 2009-11-03 | 2015-12-08 | Mediatek Inc. | Computing system using single operating system to provide normal security services and high security services, and methods thereof |
CN101950277B (zh) * | 2010-09-13 | 2012-04-25 | 青岛海信信芯科技有限公司 | 用于微控制单元的数据传输方法与装置以及数据传输系统 |
GB2486737B (en) * | 2010-12-24 | 2018-09-19 | Qualcomm Technologies Int Ltd | Instruction execution |
US8880851B2 (en) * | 2011-04-07 | 2014-11-04 | Via Technologies, Inc. | Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline |
US8645618B2 (en) * | 2011-07-14 | 2014-02-04 | Lsi Corporation | Flexible flash commands |
EP2798464B8 (en) | 2011-12-30 | 2019-12-11 | Intel Corporation | Packed rotate processors, methods, systems, and instructions |
CN102833336A (zh) * | 2012-08-31 | 2012-12-19 | 河海大学 | 分散分布式信息采集与并发处理系统中数据分包处理方法 |
US10140129B2 (en) * | 2012-12-28 | 2018-11-27 | Intel Corporation | Processing core having shared front end unit |
CN103186438A (zh) * | 2013-04-02 | 2013-07-03 | 浪潮电子信息产业股份有限公司 | 一种提高磁盘阵列数据重构效率的方法 |
CN103226328B (zh) * | 2013-04-21 | 2015-06-24 | 中国矿业大学(北京) | 采集次数控制模式下的多线程数据采集系统同步控制方法 |
US20150127927A1 (en) * | 2013-11-01 | 2015-05-07 | Qualcomm Incorporated | Efficient hardware dispatching of concurrent functions in multicore processors, and related processor systems, methods, and computer-readable media |
KR102254099B1 (ko) | 2014-05-19 | 2021-05-20 | 삼성전자주식회사 | 메모리 스와핑 처리 방법과 이를 적용하는 호스트 장치, 스토리지 장치 및 데이터 처리 시스템 |
CN103984235B (zh) * | 2014-05-27 | 2016-05-11 | 湖南大学 | 基于c/s结构的空间机械臂控制系统软件架构及构建方法 |
US20160381050A1 (en) | 2015-06-26 | 2016-12-29 | Intel Corporation | Processors, methods, systems, and instructions to protect shadow stacks |
US10394556B2 (en) | 2015-12-20 | 2019-08-27 | Intel Corporation | Hardware apparatuses and methods to switch shadow stack pointers |
US10430580B2 (en) | 2016-02-04 | 2019-10-01 | Intel Corporation | Processor extensions to protect stacks during ring transitions |
US10838656B2 (en) | 2016-12-20 | 2020-11-17 | Mediatek Inc. | Parallel memory access to on-chip memory containing regions of different addressing schemes by threads executed on parallel processing units |
US10387037B2 (en) * | 2016-12-31 | 2019-08-20 | Intel Corporation | Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependencies |
PL3812900T3 (pl) | 2016-12-31 | 2024-04-08 | Intel Corporation | Systemy, sposoby i aparaty do obliczania heterogenicznego |
CN107329812B (zh) * | 2017-06-09 | 2018-07-06 | 腾讯科技(深圳)有限公司 | 一种运行协程的方法和装置 |
CN112463327B (zh) * | 2020-11-25 | 2023-01-31 | 海光信息技术股份有限公司 | 逻辑线程快速切换的方法、装置、cpu芯片及服务器 |
TWI769080B (zh) * | 2021-09-17 | 2022-06-21 | 瑞昱半導體股份有限公司 | 用於同步動態隨機存取記憶體之控制模組及其控制方法 |
US20230205869A1 (en) * | 2021-12-23 | 2023-06-29 | Intel Corporation | Efficient exception handling in trusted execution environments |
Family Cites Families (140)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3373408A (en) | 1965-04-16 | 1968-03-12 | Rca Corp | Computer capable of switching between programs without storage and retrieval of the contents of operation registers |
US3478322A (en) | 1967-05-23 | 1969-11-11 | Ibm | Data processor employing electronically changeable control storage |
US3577189A (en) * | 1969-01-15 | 1971-05-04 | Ibm | Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays |
BE795789A (fr) | 1972-03-08 | 1973-06-18 | Burroughs Corp | Microprogramme comportant une micro-instruction de recouvrement |
US3881173A (en) | 1973-05-14 | 1975-04-29 | Amdahl Corp | Condition code determination and data processing |
IT986411B (it) | 1973-06-05 | 1975-01-30 | Olivetti E C Spa | Sistema per trasferire il control lo delle elaborazioni da un primo livello prioritario ad un secondo livello prioritario |
FR2253415A5 (zh) * | 1973-12-04 | 1975-06-27 | Cii | |
US3913074A (en) | 1973-12-18 | 1975-10-14 | Honeywell Inf Systems | Search processing apparatus |
US4130890A (en) | 1977-06-08 | 1978-12-19 | Itt Industries, Inc. | Integrated DDC memory with bitwise erase |
US4392758A (en) | 1978-05-22 | 1983-07-12 | International Business Machines Corporation | Underscore erase |
JPS56164464A (en) | 1980-05-21 | 1981-12-17 | Tatsuo Nogi | Parallel processing computer |
US4400770A (en) | 1980-11-10 | 1983-08-23 | International Business Machines Corporation | Cache synonym detection and handling means |
CA1179069A (en) | 1981-04-10 | 1984-12-04 | Yasushi Fukunaga | Data transmission apparatus for a multiprocessor system |
US4471426A (en) * | 1981-07-02 | 1984-09-11 | Texas Instruments Incorporated | Microcomputer which fetches two sets of microcode bits at one time |
US4454595A (en) | 1981-12-23 | 1984-06-12 | Pitney Bowes Inc. | Buffer for use with a fixed disk controller |
US4477872A (en) | 1982-01-15 | 1984-10-16 | International Business Machines Corporation | Decode history table for conditional branch instructions |
US4569016A (en) | 1983-06-30 | 1986-02-04 | International Business Machines Corporation | Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system |
JPS6014338A (ja) * | 1983-06-30 | 1985-01-24 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 計算機システムにおける分岐機構 |
US4606025A (en) | 1983-09-28 | 1986-08-12 | International Business Machines Corp. | Automatically testing a plurality of memory arrays on selected memory array testers |
US4808988A (en) | 1984-04-13 | 1989-02-28 | Megatek Corporation | Digital vector generator for a graphic display system |
US4868735A (en) | 1984-05-08 | 1989-09-19 | Advanced Micro Devices, Inc. | Interruptible structured microprogrammed sixteen-bit address sequence controller |
US4742451A (en) | 1984-05-21 | 1988-05-03 | Digital Equipment Corporation | Instruction prefetch system for conditional branch instruction for central processor unit |
US5187800A (en) | 1985-01-04 | 1993-02-16 | Sun Microsystems, Inc. | Asynchronous pipelined data processing system |
US5045995A (en) | 1985-06-24 | 1991-09-03 | Vicom Systems, Inc. | Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system |
US4754398A (en) * | 1985-06-28 | 1988-06-28 | Cray Research, Inc. | System for multiprocessor communication using local and common semaphore and information registers |
US4755966A (en) | 1985-06-28 | 1988-07-05 | Hewlett-Packard Company | Bidirectional branch prediction and optimization |
US4777587A (en) | 1985-08-30 | 1988-10-11 | Advanced Micro Devices, Inc. | System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses |
US4847755A (en) | 1985-10-31 | 1989-07-11 | Mcc Development, Ltd. | Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies |
US5021945A (en) * | 1985-10-31 | 1991-06-04 | Mcc Development, Ltd. | Parallel processor system for processing natural concurrencies and method therefor |
US4745544A (en) | 1985-12-12 | 1988-05-17 | Texas Instruments Incorporated | Master/slave sequencing processor with forced I/O |
US4724521A (en) | 1986-01-14 | 1988-02-09 | Veri-Fone, Inc. | Method for operating a local terminal to execute a downloaded application program |
US5297260A (en) | 1986-03-12 | 1994-03-22 | Hitachi, Ltd. | Processor having a plurality of CPUS with one CPU being normally connected to common bus |
US5170484A (en) | 1986-09-18 | 1992-12-08 | Digital Equipment Corporation | Massively parallel array processing system |
US4992934A (en) | 1986-12-15 | 1991-02-12 | United Technologies Corporation | Reduced instruction set computing apparatus and methods |
US5073864A (en) | 1987-02-10 | 1991-12-17 | Davin Computer Corporation | Parallel string processor and method for a minicomputer |
US5142683A (en) | 1987-03-09 | 1992-08-25 | Unisys Corporation | Intercomputer communication control apparatus and method |
US4866664A (en) | 1987-03-09 | 1989-09-12 | Unisys Corporation | Intercomputer communication control apparatus & method |
US5189636A (en) | 1987-11-16 | 1993-02-23 | Intel Corporation | Dual mode combining circuitry |
US4816913A (en) | 1987-11-16 | 1989-03-28 | Technology, Inc., 64 | Pixel interpolation circuitry as for a video signal processor |
US5055999A (en) * | 1987-12-22 | 1991-10-08 | Kendall Square Research Corporation | Multiprocessor digital data processing system |
US5220669A (en) | 1988-02-10 | 1993-06-15 | International Business Machines Corporation | Linkage mechanism for program isolation |
DE68913629T2 (de) | 1988-03-14 | 1994-06-16 | Unisys Corp | Satzverriegelungsprozessor für vielfachverarbeitungsdatensystem. |
US5056015A (en) | 1988-03-23 | 1991-10-08 | Du Pont Pixel Systems Limited | Architectures for serial or parallel loading of writable control store |
US5165025A (en) | 1988-10-06 | 1992-11-17 | Lass Stanley E | Interlacing the paths after a conditional branch like instruction |
US5202972A (en) | 1988-12-29 | 1993-04-13 | International Business Machines Corporation | Store buffer apparatus in a multiprocessor system |
US5155854A (en) | 1989-02-03 | 1992-10-13 | Digital Equipment Corporation | System for arbitrating communication requests using multi-pass control unit based on availability of system resources |
US5155831A (en) | 1989-04-24 | 1992-10-13 | International Business Machines Corporation | Data processing system with fast queue store interposed between store-through caches and a main memory |
US5113516A (en) | 1989-07-31 | 1992-05-12 | North American Philips Corporation | Data repacker having controlled feedback shifters and registers for changing data format |
US5168555A (en) | 1989-09-06 | 1992-12-01 | Unisys Corporation | Initial program load control |
US5263169A (en) | 1989-11-03 | 1993-11-16 | Zoran Corporation | Bus arbitration and resource management for concurrent vector signal processor architecture |
DE3942977A1 (de) | 1989-12-23 | 1991-06-27 | Standard Elektrik Lorenz Ag | Verfahren zum wiederherstellen der richtigen zellfolge, insbesondere in einer atm-vermittlungsstelle, sowie ausgangseinheit hierfuer |
US5544337A (en) | 1989-12-29 | 1996-08-06 | Cray Research, Inc. | Vector processor having registers for control by vector resisters |
US5247671A (en) | 1990-02-14 | 1993-09-21 | International Business Machines Corporation | Scalable schedules for serial communications controller in data processing systems |
JPH0799812B2 (ja) | 1990-03-26 | 1995-10-25 | 株式会社グラフイックス・コミュニケーション・テクノロジーズ | 信号符号化装置および信号復号化装置、並びに信号符号化復号化装置 |
US5390329A (en) | 1990-06-11 | 1995-02-14 | Cray Research, Inc. | Responding to service requests using minimal system-side context in a multiprocessor environment |
JPH0454652A (ja) * | 1990-06-25 | 1992-02-21 | Nec Corp | マイクロコンピュータ |
US5432918A (en) | 1990-06-29 | 1995-07-11 | Digital Equipment Corporation | Method and apparatus for ordering read and write operations using conflict bits in a write queue |
EP0463973A3 (en) * | 1990-06-29 | 1993-12-01 | Digital Equipment Corp | Branch prediction in high performance processor |
US5404482A (en) | 1990-06-29 | 1995-04-04 | Digital Equipment Corporation | Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills |
US5347648A (en) | 1990-06-29 | 1994-09-13 | Digital Equipment Corporation | Ensuring write ordering under writeback cache error conditions |
DE4129614C2 (de) * | 1990-09-07 | 2002-03-21 | Hitachi Ltd | System und Verfahren zur Datenverarbeitung |
JP2508907B2 (ja) * | 1990-09-18 | 1996-06-19 | 日本電気株式会社 | 遅延分岐命令の制御方式 |
DE69106384T2 (de) | 1990-10-19 | 1995-08-10 | Cray Research Inc | Skalierbares parallel-vektorrechnersystem. |
US5367678A (en) | 1990-12-06 | 1994-11-22 | The Regents Of The University Of California | Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically |
US5394530A (en) | 1991-03-15 | 1995-02-28 | Nec Corporation | Arrangement for predicting a branch target address in the second iteration of a short loop |
EP0522513A2 (en) | 1991-07-09 | 1993-01-13 | Hughes Aircraft Company | High speed parallel microcode program controller |
US5247675A (en) * | 1991-08-09 | 1993-09-21 | International Business Machines Corporation | Preemptive and non-preemptive scheduling and execution of program threads in a multitasking operating system |
US5255239A (en) | 1991-08-13 | 1993-10-19 | Cypress Semiconductor Corporation | Bidirectional first-in-first-out memory device with transparent and user-testable capabilities |
US5623489A (en) | 1991-09-26 | 1997-04-22 | Ipc Information Systems, Inc. | Channel allocation system for distributed digital switching network |
US5392412A (en) | 1991-10-03 | 1995-02-21 | Standard Microsystems Corporation | Data communication controller for use with a single-port data packet buffer |
US5392391A (en) | 1991-10-18 | 1995-02-21 | Lsi Logic Corporation | High performance graphics applications controller |
US5557766A (en) | 1991-10-21 | 1996-09-17 | Kabushiki Kaisha Toshiba | High-speed processor for handling multiple interrupts utilizing an exclusive-use bus and current and previous bank pointers to specify a return bank |
US5452437A (en) | 1991-11-18 | 1995-09-19 | Motorola, Inc. | Methods of debugging multiprocessor system |
US5357617A (en) | 1991-11-22 | 1994-10-18 | International Business Machines Corporation | Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor |
US5442797A (en) | 1991-12-04 | 1995-08-15 | Casavant; Thomas L. | Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging |
JP2823767B2 (ja) | 1992-02-03 | 1998-11-11 | 松下電器産業株式会社 | レジスタファイル |
KR100309566B1 (ko) | 1992-04-29 | 2001-12-15 | 리패치 | 파이프라인프로세서에서다중명령어를무리짓고,그룹화된명령어를동시에발행하고,그룹화된명령어를실행시키는방법및장치 |
US5459842A (en) | 1992-06-26 | 1995-10-17 | International Business Machines Corporation | System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory |
DE4223600C2 (de) | 1992-07-17 | 1994-10-13 | Ibm | Mehrprozessor-Computersystem und Verfahren zum Übertragen von Steuerinformationen und Dateninformation zwischen wenigstens zwei Prozessoreinheiten eines Computersystems |
US5274770A (en) | 1992-07-29 | 1993-12-28 | Tritech Microelectronics International Pte Ltd. | Flexible register-based I/O microcontroller with single cycle instruction execution |
US5442756A (en) | 1992-07-31 | 1995-08-15 | Intel Corporation | Branch prediction and resolution apparatus for a superscalar computer processor |
US5692167A (en) * | 1992-07-31 | 1997-11-25 | Intel Corporation | Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor |
US5481683A (en) * | 1992-10-30 | 1996-01-02 | International Business Machines Corporation | Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions |
US5463746A (en) | 1992-10-30 | 1995-10-31 | International Business Machines Corp. | Data processing system having prediction by using an embedded guess bit of remapped and compressed opcodes |
US5428779A (en) | 1992-11-09 | 1995-06-27 | Seiko Epson Corporation | System and method for supporting context switching within a multiprocessor system having functional blocks that generate state programs with coded register load instructions |
US5450603A (en) | 1992-12-18 | 1995-09-12 | Xerox Corporation | SIMD architecture with transfer register or value source circuitry connected to bus |
ATE188559T1 (de) | 1992-12-23 | 2000-01-15 | Centre Electron Horloger | Multi-tasking-steuerungsgerät mit geringem energieverbrauch |
US5404464A (en) | 1993-02-11 | 1995-04-04 | Ast Research, Inc. | Bus control system and method that selectively generate an early address strobe |
US5448702A (en) | 1993-03-02 | 1995-09-05 | International Business Machines Corporation | Adapters with descriptor queue management capability |
US6311286B1 (en) | 1993-04-30 | 2001-10-30 | Nec Corporation | Symmetric multiprocessing system with unified environment and distributed system functions |
WO1994027216A1 (en) | 1993-05-14 | 1994-11-24 | Massachusetts Institute Of Technology | Multiprocessor coupling system with integrated compile and run time scheduling for parallelism |
CA2122182A1 (en) | 1993-05-20 | 1994-11-21 | Rene Leblanc | Method for rapid prototyping of programming problems |
US5363448A (en) * | 1993-06-30 | 1994-11-08 | United Technologies Automotive, Inc. | Pseudorandom number generation and cryptographic authentication |
CA2107299C (en) | 1993-09-29 | 1997-02-25 | Mehrad Yasrebi | High performance machine for switched communications in a heterogenous data processing network gateway |
US5446736A (en) | 1993-10-07 | 1995-08-29 | Ast Research, Inc. | Method and apparatus for connecting a node to a wireless network using a standard protocol |
DE69415126T2 (de) | 1993-10-21 | 1999-07-08 | Sun Microsystems Inc., Mountain View, Calif. | Gegenflusspipelineprozessor |
DE69430352T2 (de) | 1993-10-21 | 2003-01-30 | Sun Microsystems Inc., Mountain View | Gegenflusspipeline |
TW261676B (zh) * | 1993-11-02 | 1995-11-01 | Motorola Inc | |
US5450351A (en) | 1993-11-19 | 1995-09-12 | International Business Machines Corporation | Content addressable memory implementation with random access memory |
US6079014A (en) * | 1993-12-02 | 2000-06-20 | Intel Corporation | Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state |
US5487159A (en) | 1993-12-23 | 1996-01-23 | Unisys Corporation | System for processing shift, mask, and merge operations in one instruction |
DE69420540T2 (de) * | 1994-01-03 | 2000-02-10 | Intel Corp., Santa Clara | Verfahren und Vorrichtung zum Implementieren eines vierstufigen Verzweigungsauflosungssystem in einem Rechnerprozessor |
US5490204A (en) | 1994-03-01 | 1996-02-06 | Safco Corporation | Automated quality assessment system for cellular networks |
US5659722A (en) * | 1994-04-28 | 1997-08-19 | International Business Machines Corporation | Multiple condition code branching system in a multi-processor environment |
US5542088A (en) | 1994-04-29 | 1996-07-30 | Intergraph Corporation | Method and apparatus for enabling control of task execution |
US5544236A (en) | 1994-06-10 | 1996-08-06 | At&T Corp. | Access to unsubscribed features |
US5574922A (en) | 1994-06-17 | 1996-11-12 | Apple Computer, Inc. | Processor with sequences of processor instructions for locked memory updates |
FR2722041B1 (fr) | 1994-06-30 | 1998-01-02 | Samsung Electronics Co Ltd | Decodeur de huffman |
US5655132A (en) * | 1994-08-08 | 1997-08-05 | Rockwell International Corporation | Register file with multi-tasking support |
US5640538A (en) | 1994-08-22 | 1997-06-17 | Adaptec, Inc. | Programmable timing mark sequencer for a disk drive |
US5717760A (en) * | 1994-11-09 | 1998-02-10 | Channel One Communications, Inc. | Message protection system and method |
CN1306394C (zh) * | 1994-12-02 | 2007-03-21 | 现代电子美国公司 | 有限游程转移预测的方法 |
US5610864A (en) | 1994-12-23 | 1997-03-11 | Micron Technology, Inc. | Burst EDO memory device with maximized write cycle timing |
US5550816A (en) | 1994-12-29 | 1996-08-27 | Storage Technology Corporation | Method and apparatus for virtual switching |
US5649157A (en) | 1995-03-30 | 1997-07-15 | Hewlett-Packard Co. | Memory controller with priority queues |
JP3130446B2 (ja) * | 1995-05-10 | 2001-01-31 | 松下電器産業株式会社 | プログラム変換装置及びプロセッサ |
US5592622A (en) | 1995-05-10 | 1997-01-07 | 3Com Corporation | Network intermediate system with message passing architecture |
US5541920A (en) | 1995-06-15 | 1996-07-30 | Bay Networks, Inc. | Method and apparatus for a delayed replace mechanism for a streaming packet modification engine |
KR0180169B1 (ko) * | 1995-06-30 | 1999-05-01 | 배순훈 | 가변길이 부호기 |
US5613071A (en) | 1995-07-14 | 1997-03-18 | Intel Corporation | Method and apparatus for providing remote memory access in a distributed memory multiprocessor system |
US5933627A (en) * | 1996-07-01 | 1999-08-03 | Sun Microsystems | Thread switch on blocked load or store using instruction thread field |
US6061711A (en) * | 1996-08-19 | 2000-05-09 | Samsung Electronics, Inc. | Efficient context saving and restoring in a multi-tasking computing system environment |
US6058465A (en) * | 1996-08-19 | 2000-05-02 | Nguyen; Le Trong | Single-instruction-multiple-data processing in a multimedia signal processor |
DE69717369T2 (de) * | 1996-08-27 | 2003-09-11 | Matsushita Electric Ind Co Ltd | Vielfadenprozessor zur Verarbeitung von mehreren Befehlsströmen unabhängig von einander durch eine flexible Durchsatzsteuerung in jedem Befehlsstrom |
JPH10177482A (ja) * | 1996-10-31 | 1998-06-30 | Texas Instr Inc <Ti> | マイクロプロセッサおよび動作方法 |
US5857104A (en) | 1996-11-26 | 1999-01-05 | Hewlett-Packard Company | Synthetic dynamic branch prediction |
US6088788A (en) * | 1996-12-27 | 2000-07-11 | International Business Machines Corporation | Background completion of instruction and associated fetch request in a multithread processor |
US6029228A (en) * | 1996-12-31 | 2000-02-22 | Texas Instruments Incorporated | Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions |
US6470376B1 (en) * | 1997-03-04 | 2002-10-22 | Matsushita Electric Industrial Co., Ltd | Processor capable of efficiently executing many asynchronous event tasks |
US5835705A (en) * | 1997-03-11 | 1998-11-10 | International Business Machines Corporation | Method and system for performance per-thread monitoring in a multithreaded processor |
US5996068A (en) * | 1997-03-26 | 1999-11-30 | Lucent Technologies Inc. | Method and apparatus for renaming registers corresponding to multiple thread identifications |
US5907702A (en) * | 1997-03-28 | 1999-05-25 | International Business Machines Corporation | Method and apparatus for decreasing thread switch latency in a multithread processor |
US6009515A (en) * | 1997-05-30 | 1999-12-28 | Sun Microsystems, Inc. | Digital data processing system including efficient arrangement to support branching within trap shadows |
GB2326253A (en) * | 1997-06-10 | 1998-12-16 | Advanced Risc Mach Ltd | Coprocessor data access control |
US6385720B1 (en) * | 1997-07-14 | 2002-05-07 | Matsushita Electric Industrial Co., Ltd. | Branch prediction method and processor using origin information, relative position information and history information |
US6243735B1 (en) * | 1997-09-01 | 2001-06-05 | Matsushita Electric Industrial Co., Ltd. | Microcontroller, data processing system and task switching control method |
US5926646A (en) * | 1997-09-11 | 1999-07-20 | Advanced Micro Devices, Inc. | Context-dependent memory-mapped registers for transparent expansion of a register file |
UA55489C2 (uk) * | 1997-10-07 | 2003-04-15 | Каналь+ Сосьєте Анонім | Пристрій для багатопотокової обробки даних (варіанти) |
US6567839B1 (en) * | 1997-10-23 | 2003-05-20 | International Business Machines Corporation | Thread switch control in a multithreaded processor system |
US6560629B1 (en) * | 1998-10-30 | 2003-05-06 | Sun Microsystems, Inc. | Multi-thread processing |
-
2000
- 2000-08-31 US US10/069,195 patent/US7421572B1/en not_active Expired - Fee Related
- 2000-08-31 EP EP00959717A patent/EP1236092A4/en not_active Ceased
- 2000-08-31 WO PCT/US2000/024006 patent/WO2001016713A1/en active Application Filing
- 2000-08-31 AU AU73407/00A patent/AU7340700A/en not_active Abandoned
- 2000-08-31 CN CNB008154376A patent/CN1184562C/zh not_active Expired - Fee Related
- 2000-08-31 CN CNB008154171A patent/CN100342326C/zh not_active Expired - Fee Related
- 2000-08-31 AT AT00961457T patent/ATE475930T1/de not_active IP Right Cessation
- 2000-08-31 AU AU73406/00A patent/AU7340600A/en not_active Abandoned
- 2000-08-31 EP EP00959714A patent/EP1236093A4/en not_active Ceased
- 2000-08-31 CN CNB008144966A patent/CN100474236C/zh not_active Expired - Fee Related
- 2000-08-31 WO PCT/US2000/023992 patent/WO2001018646A1/en active Application Filing
- 2000-08-31 AU AU70987/00A patent/AU7098700A/en not_active Abandoned
- 2000-08-31 CA CA002386562A patent/CA2386562A1/en not_active Abandoned
- 2000-08-31 WO PCT/US2000/023996 patent/WO2001016716A1/en active Application Filing
- 2000-08-31 CA CA002383532A patent/CA2383532A1/en not_active Abandoned
- 2000-08-31 CA CA002383528A patent/CA2383528C/en not_active Expired - Fee Related
- 2000-08-31 AU AU70984/00A patent/AU7098400A/en not_active Abandoned
- 2000-08-31 EP EP00959711A patent/EP1236088B9/en not_active Expired - Lifetime
- 2000-08-31 AU AU70990/00A patent/AU7099000A/en not_active Abandoned
- 2000-08-31 EP EP00959713A patent/EP1242869B1/en not_active Expired - Lifetime
- 2000-08-31 AU AU70979/00A patent/AU7097900A/en not_active Abandoned
- 2000-08-31 CA CA002383531A patent/CA2383531A1/en not_active Abandoned
- 2000-08-31 CA CA002386558A patent/CA2386558C/en not_active Expired - Fee Related
- 2000-08-31 CN CNB008154309A patent/CN1254739C/zh not_active Expired - Fee Related
- 2000-08-31 WO PCT/US2000/024000 patent/WO2001016714A1/en active Application Filing
- 2000-08-31 WO PCT/US2000/023994 patent/WO2001016722A1/en active Application Filing
- 2000-08-31 DE DE60044752T patent/DE60044752D1/de not_active Expired - Lifetime
- 2000-08-31 AT AT00959711T patent/ATE396449T1/de not_active IP Right Cessation
- 2000-08-31 CA CA002383526A patent/CA2383526A1/en not_active Abandoned
- 2000-08-31 WO PCT/US2000/023982 patent/WO2001016758A2/en active Application Filing
- 2000-08-31 AU AU73404/00A patent/AU7340400A/en not_active Abandoned
- 2000-08-31 AU AU70985/00A patent/AU7098500A/en not_active Abandoned
- 2000-08-31 DE DE60038976T patent/DE60038976D1/de not_active Expired - Lifetime
- 2000-08-31 CN CNB008151237A patent/CN1296818C/zh not_active Expired - Fee Related
- 2000-08-31 WO PCT/US2000/023983 patent/WO2001016715A1/en active Application Filing
- 2000-08-31 EP EP00961457A patent/EP1236094B1/en not_active Expired - Lifetime
- 2000-08-31 AU AU70986/00A patent/AU7098600A/en not_active Abandoned
- 2000-08-31 CN CNB008148740A patent/CN1271513C/zh not_active Expired - Fee Related
- 2000-08-31 EP EP00959712A patent/EP1236097A4/en not_active Withdrawn
- 2000-09-01 WO PCT/US2000/024095 patent/WO2001016698A2/en active Application Filing
- 2000-09-01 AU AU71012/00A patent/AU7101200A/en not_active Abandoned
- 2000-09-01 TW TW089117903A patent/TW559729B/zh not_active IP Right Cessation
- 2000-09-01 CN CNB008154120A patent/CN100351781C/zh not_active Expired - Fee Related
- 2000-09-01 EP EP00961484A patent/EP1242867A4/en not_active Withdrawn
- 2000-09-01 AU AU73429/00A patent/AU7342900A/en not_active Abandoned
- 2000-09-01 CA CA002383540A patent/CA2383540A1/en not_active Abandoned
- 2000-10-18 TW TW089117904A patent/TW475148B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117900A patent/TW486666B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117902A patent/TW571239B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117911A patent/TW548584B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117906A patent/TWI221251B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117905A patent/TW569133B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117910A patent/TW486667B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117901A patent/TWI220732B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117912A patent/TW546585B/zh not_active IP Right Cessation
- 2000-10-18 TW TW089117907A patent/TW594562B/zh not_active IP Right Cessation
-
2002
- 2002-10-21 HK HK02107606.9A patent/HK1046049A1/zh unknown
- 2002-11-07 HK HK02108083.9A patent/HK1046566A1/zh unknown
- 2002-11-07 HK HK02108082.0A patent/HK1046565A1/zh unknown
-
2003
- 2003-03-24 HK HK03102109.1A patent/HK1049902B/zh not_active IP Right Cessation
- 2003-05-15 HK HK03103439A patent/HK1051247A1/xx not_active IP Right Cessation
- 2003-06-03 HK HK03103923A patent/HK1051728A1/xx not_active IP Right Cessation
- 2003-06-03 HK HK03103924A patent/HK1051729A1/xx not_active IP Right Cessation
- 2003-06-03 HK HK03103925A patent/HK1051730A1/xx not_active IP Right Cessation
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW594562B (en) | Branch instruction for processor | |
EP1221105B1 (en) | Parallel processor architecture | |
US7424579B2 (en) | Memory controller for processor having multiple multithreaded programmable units | |
US6728845B2 (en) | SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues | |
EP1221086A1 (en) | Execution of multiple threads in a parallel processor | |
WO2001016702A1 (en) | Register set used in multithreaded parallel processor architecture | |
WO2000065435A1 (fr) | Systeme informatique | |
WO2001016697A9 (en) | Local register instruction for micro engine used in multithreadedparallel processor architecture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |