TW592013B - Solder bump structure and the method for forming the same - Google Patents
Solder bump structure and the method for forming the same Download PDFInfo
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- TW592013B TW592013B TW092124858A TW92124858A TW592013B TW 592013 B TW592013 B TW 592013B TW 092124858 A TW092124858 A TW 092124858A TW 92124858 A TW92124858 A TW 92124858A TW 592013 B TW592013 B TW 592013B
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Description
592013
發明所屬之技術領域· 本發明係有關於一播雷;# # _ a (bumDing n 種電子封裝製程中之凸塊製程 、Dump 1ng pr〇cess ),姓 σ ^ 塊离声之姓桃η & ; 特別疋有關於一種可增加焊接凸 鬼同度之結構及其形成方法。 先前技術: 缺之封ί技*是目前半導體積體電路製程中—不可或 外部電路i門2要功能在於保護積體電路及提供IC晶片與 :發展及電子產品之功能㈣將料料封裝技=發 展0 - f:刖電子封裝方式中,包含:球栅陣列、 曰曰片= ^、(C曰SP)、及覆晶(fUp_chip)等等。其 :、方法疋利用覆晶的封裝技術,其係於銲墊 、查上形成焊接凸塊(S〇lder bump)後,將焊接凸塊 連接到電路板上。而形成焊接凸塊的方法主要有三種:植 球技術(solder ball mounting)、印刷(printing)和 電鍵法(electroplating)。 ^為了進一步了解本發明之背景,以下配合第1 A到1 D圖 說明傳統上使用電鍍法形成焊接凸塊之方法。首先,請參 照第1A圖’提供-基底! 00,例如一石夕晶片,其上已形成 有二金屬焊墊102,例如鋁墊或鋼墊。接著,在基底1〇〇上 覆蓋一保護層1 04,例如一氮化矽層,並大體露出金屬焊 墊1 0 2。在保護層1 〇 4及露出的金屬焊墊丨〇 2表面順應性形
592013
成一金屬複合層l〇6 層之金屬疊層結構, 示之。 ’其通常為一附著層/阻障層/潤濕 此處為簡化圖式,僅以一單層結構表 >接下來,請參照第丨B圖,在金屬複合層丨〇 6上形成— 乾式光阻圖案層1〇8,其具有一開口 1〇9以露出金屬焊墊 1 〇 2上方之部分的金屬複合層1 〇 6,此開口 1 〇 9係欲形成焊 接凸塊之區域。接著,利用電鍍法在開口丨〇 9中形成一錫 塊1 10,其高度係取決於光阻圖案層108之厚度。
接下來,請參照第1 C圖,在去除光阻圖案層丨〇 8之 後,再以錫塊110作為蝕刻罩幕來去除未被錫塊11()覆蓋之 金屬複合層106而露出保護層104表面,餘留的金屬複合層 1〇63係作為凸塊底層金屬層(under bump metanu 曰 _ ) 。 y, 最後,請參照第ID圖,實施一回焊程序(ref 1〇w ) 使錫塊1 1 0外型因表面張力而變成為球狀或半球狀 凸塊11 0 a。 ^ 然而,焊接凸塊的高度影響著封裝元件之可靠度。隨 著封裝尺寸趨小化,如果焊接凸塊的高度太小,其抗疲^ 破壞特性會降低,而使接點壽命降低。再者,在晶片與電 :板的接合過程中’晶片和電路板之間的間隙無法有:地 進仃底膠填充(underf i n ),因而於其中產生孔洞。 〇因此,若能製備較高的焊接凸塊,則可以提高覆晶製 权的可靠度。而目前增加焊接凸塊之高度的方法, 加厚光阻圖案層的厚度或是藉由增加凸塊底層金屬層^尺
0646-10404TO:(Nl);ASEK768;spin.ptd
592013
寸來提高錫塊之容積來達成增加凸塊高度之目的。不幸 地’前者所採之方式並不利於微影程序之進行,而後者所 採之方式則會增加晶片使用面積而降低積集度。 •台灣專利第90,1 1 7,002號揭示一種覆晶^合元件凸塊 之製程方法,其利用兩反應光譜不同之光阻層來製備較高 之焊接凸塊。然而,此種方式在去除兩光阻層以進行回g 製私時’容易發生焊接凸塊坍塌,而無法有較增加其高 度另外’美國專利第6,229,220號揭示一種焊接凸塊'^士 構及其形成方法。請參照第2圖,其繪示出該專利所教= 之焊接凸塊結構剖面示意圖。此結構包含一已形成有焊塾 202及保護層204之晶片2 0 0。一阻障層20 6設置於焊墊2〇2 與焊接凸塊210之間。其中,焊接凸塊2 1()之材料係採用一 複合材料。亦即,凸塊下半部208為一高熔點材料而凸塊 上半部2 0 9則為一較低溶點之材料。當進行回焊製程時: 凸塊下半部208並不熔融以改善焊接凸塊2 1()坍塌,進而維 持其高度。然而,此種方式需採用兩種凸塊材質,製程較 為複雜且製作成本較高。 發明内容: 有鑑於此,本發明之目的在於提供一種新的焊接凸塊 之結構及其形成方法,其無須藉由增加凸塊底層金屬層之 尺寸或增加光阻層厚度,可避免積集度降低或不利於&影 程序之情形,且仍可增加焊接凸塊之高度,藉以提升焊= 凸塊之可靠度。
观013 五、發明說明(4) 明ΐ另一目的在於提供—種焊接凸塊之結構及其 加高凸塊結構,同時介電層可作電層來強化並 ^ (ul;:r!n 1) ^ ^ ^ ::上:之目的,本發明提供—種里焊接凸塊之形成方 片上方浐“θ供一晶片’其上已形成至少-焊墊,再在晶 ΐΠΐ一 t護層,㊣中保護層大體露出該焊墊。接下 在保塾上方形成_凸塊底層金屬層,並接著 ,且二i 序形成一介電層及-阻劑層,其中介電 一 = 口以露出凸塊底層金屬層且阻劑層具有-第一開口上方。接下來,在第-及二開口中 真導電材料之後,實施一迴焊程序,使導電材料轉Α 焊接凸塊。最後,去除阻劑層。&冑導電材枓轉為 其:,導電材料包含錫,且凸塊底層金屬層包含下列 之任:^鈦、鉻、鎳、釩、銅、紹、金、及其合金。 再者,介電層可由聚亞醯胺(polyimide)所組成, 而阻劑層可由濕式光阻或乾式光阻所組成。 再者,第一及第二開口可構成一上寬下窄之τ型開 D ° 構 層 又根據上述之㈣,本發明提供一種焊接凸塊之結 此結構包括· -晶片、一保護層、—凸塊底層金屬 一曰",層、及一蕈型凸塊。保護層設置於已形成至少 焊墊之曰曰片上,並大體露出焊墊。凸塊底層金屬層設置 於露出的焊墊上方。介電層設置於保護層上方並具有一開
口而露出凸塊底層金屬層。 覆蓋介電層。 蕈型凸塊設置於開口 中且部分 鎳 錫 其中, 飢、銅 凸塊底層金屬層包含下 、鋁、金、及其合金, 列之任一種 且蕈型凸塊 •欽、絡、 之材質包含 再者,介 再者,覆 度之15到20%。 電層可由聚亞醯胺所級成。 蓋介電層之蕈型凸塊的部分, 其厚度佔總厚 為讓本發明之上述目的 下文特舉較佳實施例,並配合所附圖‘::J:月=: 下: 、忭吁細說明如 Φ 實施方式: 之焊接凸塊之 以下配合第3 A到3E圖說明本發明實施例 形成方法。 首先,請參照第3 A圖,提供一基底3 〇 〇,例 片或其他半導體晶片,其上方可以形成任何所需的半導體 元件,例如MOS電晶體、電阻、邏輯元件等,以及覆蓋其 上的各種塗層與連接各半導體元件的内連線結構,不過此 處為了簡化圖式,僅以一平整的基板表示之。再者,基底 3^0表面已形成有一金屬焊墊3〇2,例如鋁墊或銅墊。二_ 著,在基底300上覆蓋一保護層3〇4,並大體露出金屬焊墊 302。此保護層304的材質例如為聚亞醯胺(p〇iyimide, PI )、或電漿增強型化學氣相沈積法(PECVI))所製成的
592013 五、發明說明(6) 氮化石夕(PE nitride)
之後,可藉由習知沉積技術,例如濺鑛法或化學氣相 沉積法,於保護層304和露出的金屬焊墊3〇2上形成一凸塊 底層金屬層(UBM)306,其通常為一金屬複合層,包含一 附著層、一阻障層、一潤濕層,此處為簡化圖式,僅以一 單層結構表示之。其中,附著層係用以增加金屬焊墊3〇2 及保護層3 0 4之附著力;阻障層係用以防止金屬原子的擴 月欠’满/嚴層係用以增進凸塊的潤濕及防止氧化。在本實施 例中,凸塊底層金屬層3 0 6之材質至少包含下列之任一 種:鈦、鉻、鎳、釩、銅、鋁、金、及其合拿。較佳地, 凸塊底層金屬層306可由鋁/鎳釩合金/銅所構成。接 著’藉由習知微影蝕刻製程部分去除凸塊底層金屬層 306,僅在金屬焊墊3 02上方留下凸塊底層金屬層3〇6並部 分覆盍保護層3 0 4,如圖所示。
接下來,凊參照第3 B到3 C圖,進行本發明之關鍵步 驟。首先,在保護層304及凸塊底層金屬層3〇6上方形成一 介電層308。之後,可藉由習知微影蝕刻製程在介電層3〇8 中形成一開口 309以露出凸塊底層金屬層3〇6,如第圖所 示。在本實施例中,介電層308可為一光敏性高分子材 料,例如聚亞醯胺(P I ),並可利用微影製程形成該開口 3 0 9。接著,在介電層3 0 8上形成一阻劑層3丨〇,例如乾式 光阻或是濕式光阻,同樣可藉由微影製程於其中形成一開 口 311。在本實施例中,開口 3〇9及開口 311之直徑可大體 相同或疋一上寬下窄之T型開口。較佳地,開口 3 〇 9及開口
592013
發明說明(7) 311係一T型開口 312,如第3C圖所示。 f 1,請參照第3B,到3C,圖,其繪示出形成開口312 之另一範例。首先,在保護層3〇4及凸塊底層金屬層3〇6上 方依序形成一介電層308及一阻劑層31〇,如第3β,圖所 不。此處,介電層308及一阻劑層31〇之材質可分別為聚亞 醯胺及乾式光阻。之後,可藉由一次或兩次的微影程序, 在’I電層3 0 8及-阻劑層3 i 〇中形成開口 3 J 2。較佳地,開 口 312係一T型開口 ,如第3C,圖所示。
如此一來’若需要在後續製程中製造高度較高的焊接 凸塊,可以在不增加光阻層厚度的情況下,藉由增加介電 層308的厚度來達成。再者,可藉由介電層3〇8來強化焊接 免、、Ό構使其此於後續製程中承受更大的剪應力。 接下來,印參照第3 D圖’可利用印刷於開口 3 1 2中填 ^導電材料314,其材質例如為錫鉛(SnPb )、無鉛接 合物Uead free s〇ider )或其他種類的接合物。
最後’請參照第3 E圖,可先移除阻劑層3丨〇,以露出 其下方的介電層308的表面。接著,實施一迴焊程序,使 導電材料314的外形因表面張力而變成一蕈型焊接凸塊 31 4 a,如圖所不。另外,亦可先實施一迴焊程序,以將導 電材料314,為一蕈型焊接凸塊31“。之後再移除阻劑層 10 °在本實施例中’此焊接凸塊314a受到周圍介電層 2支撐,因此在進行回焊程序時並不會坍塌,因而能維持 2接凸塊3 14a的高度。再者,介電層3〇8可作為後續底膠 填充時一部分的填充料,以減少後續填充用量。另外,焊
592013 五、發明說明(8) 接凸塊314a的容積可取決於介電層308及阻劑層310之厚 度,因此也無需藉由增加凸塊底層金屬層3〇6之尺寸來增 加焊接凸塊3 1 4 a的高度。亦即,只要控制上述開口 3 1 2的 尺寸及深度’即可在不影響凸塊底層金屬層306之尺寸下 控制焊接凸塊3 14a的高度而同時防止積集度降低。 同樣請參照第3 E圖,其繪示出根據本發明實施例之焊 接凸塊結構之剖面圖。此結構包括··一晶片3 Q 〇、一保護 層304、一凸塊底層金屬層306、一介電層308、及一蕈型 凸塊314a。保護層304係設置於已形成至少一金屬焊墊302 之晶片上,並大體露出金屬焊墊302。 凸塊底層金屬層306係設置於露出的金屬焊墊3〇2上方 並部分覆蓋保護層3 04,其材質至少包含下列之任一種: 鈦、鉻、鎳、釩、銅、鋁、金、及其合金。介電層3〇8係 设置於保護層304上方並具有一開口3〇9而露出凸塊底層金 屬層306,其材質可為一光敏性高分子材料,例如聚亞醯 胺。 蕈型凸塊3 14a係設置於開口 30 9中且部分覆蓋介電層 308,其材質例如為錫鉛(snPb)、無鉛接合物(lead free solder )或其他種類的接合物。再者,覆蓋介電層 308之蕈型凸塊3 14a的部分,其厚度佔總厚度之15到2〇%, 其可使凸塊3 1 4a與電路基板接合時,能提供足夠的坍塌 量。 相較於習知技術,本發明之焊接凸塊結構無須藉由增 加凸塊底層金屬層之尺寸或增加光阻層厚度,可避免積集
五、發明說明(9) 度降低或不利於 南度,藉以提升 焊接凸塊周圍之 使用兩種以上的 充料,以減少後 即’可具有較簡 雖然本發明 限定本發明,任 神和範圍内,含 田 當視後附之申請 微影程 焊接凸 介電層 凸塊材 續底膠 單的製 已以較 何熟習 可作更 專利範 序之情形’且仍可增加焊接凸塊之 塊之可靠度。再者,可藉由形成於 來強化並加高凸塊結構,因此無需 料,同時介電層可作為一部分的填 填充(underf i 1 1 )之填充量。亦 程步驟且降低製造成本。 ,汽施例揭露如上,然其並非 '技藝者,在不脫離本發明之 以!’因此本發明之保護範圍 w界定者為準。
0646-10404TWF(N1);ASEK768;s p i n.p t d
592013 圖式簡單說明 第1 A到1 D圖係繪示出傳統上使用電鍍法形成焊接凸塊 之流程剖面示意圖。 第2圖係繪示出一習知焊接凸塊結構之剖面示意圖。 第3 A到3E圖係繪示出根據本發明實施例之焊接凸塊之 形成方法剖面示意圖。 符號說明: 習知 1 0 0〜基底; 1 0 2〜金屬焊墊; 1 0 4〜保護層; 106〜金屬複合層; 106a〜凸塊底層金屬層; 1 0 8〜光阻圖案層; 1 0 9〜開口; 11 0〜錫塊; 11 0 a〜焊接凸塊; 200〜晶片; 202〜焊墊; 2 0 4〜保護層; 2 0 6〜阻障層; 2 0 8〜凸塊下半部; 2 0 9〜凸塊上半部; 2 1 0〜焊接凸塊。
0646-10404TWP(N1);ASEK768;spin.ptd 第14頁 592013 圖式簡單說明 本發明 3 0 0〜基底; 3 0 2〜金屬焊墊; 304〜保護層; 306〜凸塊底層金屬層; 3 0 8〜介電層; 3 0 9、3 11、3 1 2 〜開口 ; 31 0〜阻劑層; 3 1 4〜導電材料; 314a〜焊接凸塊。
0646-10404OVF(Nl);ASEK768;spin.ptd 第15頁
Claims (1)
- 592013 六、申請專利範圍 1 · 一種焊接凸塊之形成方法,包括下列步驟: 提供一晶片,其上已形成至少一焊墊; 在該晶片上方覆蓋一保護層,其中該保護層大體露出 該焊墊; 在該露出的焊墊上方形成一凸塊底層金屬層; 在該保護層上方依序形成一介電層及一阻劑層,其中 該介電層具有一第一開口以露出該凸塊底層金屬層且該阻 劑層具有一第二開口位於該第一開口上方; 在該第一及該二開口中的該凸塊底層金屬層上形成該 焊接凸塊;以及 去除該阻劑層。 2. 如申請專利範圍第1項所述之焊接凸塊之形成方 法,其中形成該焊接凸塊,更包括下列步驟: 在該第一及該二開口中填入一導電材料;以及 實施一迴焊程序,使該導電材料轉為該焊接凸塊。 3. 如申請專利範圍第2項所述之焊接凸塊之形成方 法,其中該導電材料包含錫。 4. 如申請專利範圍第1項所述之焊接凸塊之形成方 法,其中該凸塊底層金屬層包含下列之任一種:鈦、鉻、 錄、凱、銅、紹、金、及其合金。 5. 如申請專利範圍第1項所述之焊接凸塊之形成方 法,其中該介電層係由光敏性高分子材料所組成。 6. 如申請專利範圍第1項所述之焊接凸塊之形成方 法,其中該介電層係由聚亞聽胺(ρ ο 1 y i m i d e )所組成。0646-10404TWF(N1);ASEK768;spin.ptd 第16頁 592013 六、申請專利範圍 7·如申請專利範圍第1項所述之焊接凸塊之形成方 法’其中該阻劑層係由濕式光卩且或乾式光阻所組成。 8 ·如申請專利範圍第1項所述之焊接凸塊之形成方 法’其中該第一及該第二開口係構成一上寬下窄之T型開 9. 一種焊接凸塊結構,包栝: 一晶片,其上已設置有至少一焊墊; 一保護層,設置於該晶片上且大體露出該焊墊; 一凸塊底層金屬層,設置於該露出的焊墊上方;一介電層,設置於保護層上方並具有一閘口而露出該 凸塊底層金屬層;以及 一蕈型凸塊,設置於該開口中且部分覆蓋該介電層。 I 0 ·如申請專利範圍第9項所述之焊接凸塊結構,其中 該凸塊底層金屬層包含下列之任一種:鈦、鉻、鎳、釩、 銅、鋁、金、及其合金。 II ·如申請專利範圍第9項所述之焊接凸塊結構,其中 該蕈型凸塊之材質包含錫。 1 2 ·如申請專利範圍第9項所述之焊接凸塊結構,其中 該介電層係由光敏性高分子材料所組成。1 3 ·如申請專利範圍第9項所述之焊接凸塊結構,其中 該介電層係由聚亞醯胺(P〇 1 y i m i d e )所組成。 1 4 ·如申請專利範圍第9項所述之焊接凸塊結構,其中 覆蓋該介電層之該蕈型凸塊的部分’其厚度佔總厚度之1 5 到 2 0〇/〇。59201315.該焊墊 一種焊接凸塊之形成方法 供一晶片,其上已形成至少 該晶片上方覆蓋一保護層, 包括下列步驟: 一焊墊; 其中該保護層大體露出 在邊露出的焊墊上方形成一凸塊底層金屬層; 在該保護層及該凸塊底層金屬層上方依序形成一聚亞 酿胺層及一乾式光阻層; 依序圖案化該乾式光阻層及該聚亞醯胺層,以在其中 形成一開口而露出該凸塊底層金屬層;在該開口中的該凸塊底層金屬層上形成該焊接凸塊; 以及 去除該乾式光阻層。 、1 6·如申請專利範圍第1 5項所述之焊接凸塊之形成方 法’其中形成該焊接凸塊,更包括下列步驟: 在σ玄開口中填入一導電材料;以及 貫施一迴焊製程,使該導電材料轉為該焊接凸塊。 、1 7 ·如申睛專利範圍第1 6項所述之焊接凸塊之形成方 法,其中該導電材料包含錫。1 8·如申請專利範圍第1 5項所述之焊接凸塊之形成方 法,其中該凸塊底層金屬層包含下列之任一種:鈦、鉻、 鎳、^、銅?呂、金、及其合金。 、1 9·如申請專利範圍第丨5項所述之焊接凸塊之形成方 法,其中戎開口係一上寬下窄之Τ型開口。
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TW092124858A TW592013B (en) | 2003-09-09 | 2003-09-09 | Solder bump structure and the method for forming the same |
US10/936,569 US7250362B2 (en) | 2003-09-09 | 2004-09-09 | Solder bump structure and method for forming the same |
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TW092124858A TW592013B (en) | 2003-09-09 | 2003-09-09 | Solder bump structure and the method for forming the same |
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TW592013B true TW592013B (en) | 2004-06-11 |
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Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060102957A1 (en) * | 2004-11-12 | 2006-05-18 | Jhon-Jhy Liaw | SER immune cell structure |
JP2006173460A (ja) * | 2004-12-17 | 2006-06-29 | Renesas Technology Corp | 半導体装置の製造方法 |
US20060160346A1 (en) * | 2005-01-19 | 2006-07-20 | Intel Corporation | Substrate bump formation |
US20080036100A1 (en) * | 2006-05-17 | 2008-02-14 | Tessera, Inc. | Solder elements with columnar structures and methods of making the same |
JP2008210993A (ja) * | 2007-02-26 | 2008-09-11 | Nec Corp | プリント配線板及びその製造方法 |
US20080308932A1 (en) * | 2007-06-12 | 2008-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package structures |
US20090008764A1 (en) * | 2007-07-02 | 2009-01-08 | Hsin-Hui Lee | Ultra-Thin Wafer-Level Contact Grid Array |
US8779300B2 (en) * | 2007-07-19 | 2014-07-15 | Unimicron Technology Corp. | Packaging substrate with conductive structure |
TWI378544B (en) * | 2007-07-19 | 2012-12-01 | Unimicron Technology Corp | Package substrate with electrically connecting structure |
US7923845B2 (en) * | 2007-09-28 | 2011-04-12 | Oracle America, Inc. | Alignment features for proximity communication |
US20090091028A1 (en) * | 2007-10-03 | 2009-04-09 | Himax Technologies Limited | Semiconductor device and method of bump formation |
US7713860B2 (en) * | 2007-10-13 | 2010-05-11 | Wan-Ling Yu | Method of forming metallic bump on I/O pad |
US8901431B2 (en) * | 2010-12-16 | 2014-12-02 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
US8563416B2 (en) | 2011-07-29 | 2013-10-22 | International Business Machines Corporation | Coaxial solder bump support structure |
US9142520B2 (en) * | 2011-08-30 | 2015-09-22 | Ati Technologies Ulc | Methods of fabricating semiconductor chip solder structures |
US20150072515A1 (en) * | 2013-09-09 | 2015-03-12 | Rajendra C. Dias | Laser ablation method and recipe for sacrificial material patterning and removal |
KR20150073473A (ko) * | 2013-12-23 | 2015-07-01 | 에스케이하이닉스 주식회사 | 반도체 소자 및 제조 방법 |
TWI551199B (zh) | 2014-04-16 | 2016-09-21 | 矽品精密工業股份有限公司 | 具電性連接結構之基板及其製法 |
CN107204294A (zh) * | 2016-03-18 | 2017-09-26 | 联芯科技有限公司 | 一种倒装焊芯片的制作方法及裸芯片组件 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6388203B1 (en) * | 1995-04-04 | 2002-05-14 | Unitive International Limited | Controlled-shaped solder reservoirs for increasing the volume of solder bumps, and structures formed thereby |
DE19704579C2 (de) * | 1997-02-07 | 1998-12-17 | Storz Karl Gmbh & Co | Kupplung zum dichten Verbinden zweier schaftartiger medizinischer Instrumente |
US6070321A (en) * | 1997-07-09 | 2000-06-06 | International Business Machines Corporation | Solder disc connection |
US6372622B1 (en) * | 1999-10-26 | 2002-04-16 | Motorola, Inc. | Fine pitch bumping with improved device standoff and bump volume |
KR100440507B1 (ko) * | 2000-03-23 | 2004-07-15 | 세이코 엡슨 가부시키가이샤 | 반도체장치 및 그 제조방법, 회로기판 및 전자기기 |
KR100344833B1 (ko) * | 2000-04-03 | 2002-07-20 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그의 제조방법 |
US6630736B1 (en) * | 2000-07-27 | 2003-10-07 | National Semiconductor Corporation | Light barrier for light sensitive semiconductor devices |
US6578755B1 (en) * | 2000-09-22 | 2003-06-17 | Flip Chip Technologies, L.L.C. | Polymer collar for solder bumps |
US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
TW530402B (en) * | 2002-03-01 | 2003-05-01 | Advanced Semiconductor Eng | Bump process |
TWI244129B (en) * | 2002-10-25 | 2005-11-21 | Via Tech Inc | Bonding column process |
US6878633B2 (en) * | 2002-12-23 | 2005-04-12 | Freescale Semiconductor, Inc. | Flip-chip structure and method for high quality inductors and transformers |
-
2003
- 2003-09-09 TW TW092124858A patent/TW592013B/zh not_active IP Right Cessation
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2004
- 2004-09-09 US US10/936,569 patent/US7250362B2/en not_active Expired - Fee Related
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US7250362B2 (en) | 2007-07-31 |
US20050054154A1 (en) | 2005-03-10 |
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