TW564502B - High-k gate oxides with buffer layers of titanium for MFOS single transistor memory applications - Google Patents

High-k gate oxides with buffer layers of titanium for MFOS single transistor memory applications Download PDF

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Publication number
TW564502B
TW564502B TW091124519A TW91124519A TW564502B TW 564502 B TW564502 B TW 564502B TW 091124519 A TW091124519 A TW 091124519A TW 91124519 A TW91124519 A TW 91124519A TW 564502 B TW564502 B TW 564502B
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Taiwan
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layer
silicon substrate
minutes
buffer layer
temperature
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TW091124519A
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English (en)
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Ting Kai Li
Sheng Teng Hsu
Bruce Dale Ulrich
Lisa Horn Stecker
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Sharp Kk
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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Description

0) 0)564502 玖、發明說明 (發明說明ϋ明:#明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 相關專利申請 本專利申請書係關於：2001年6月5曰批准的美國專利案號 6,242,771之「供鐵電應用之Pb5Ge3On薄膜的化學氣相沈積 (Chemical Vapor Deposition of Pb5Ge3〇n Thin Film for Ferroelectric Applications)」；2000 年 1 月 24 曰申請的序號 09/489,857之「金屬有機化學氣相沈積（MOCVD)之方法及系統 與鍺酸鉛（PbsGesOn ; PGO)薄膜之退火（A Method and System for Metalorganic Chemical Vapor Deposition (MOCVD) and Annealing for Lead Germinate (PGO) Thin Films)」；以及「C車由 定向鍺酸錯膜及沈積方法（C-axis Oriented Lead Germinate
Film and Deposition Method)」，美國專利案號_， 批准日期_〇 發明領域 本發明係關於單一電晶體記憶體結構及鐵電非揮發性記 憶體裝置之積體製造技術。 發明背景 本發明係揭示一種金屬 '鐵電、氧化物及矽（Metal， ferroelectric，oxide and silicon ; MFOS)的單一電晶體 (one-transistor ; IT)記憶體裝置。為在MF〇S 1T裝置中獲得 良好的半導體特性，該氧化物不應與該鐵電材料或矽基板 反應，也不應擴散到該鐵電材料或矽基板中。沈積於該氧 化物上的該鐵電薄膜應具有一低介電常數、一小偏極化值 (Pr)及良好的鐵電特性以提供一高品質的記憶體電晶體。根 -6- (2) (2)564502
據此類要求，故選擇Pt/PG〇/閘極氧化物/si (MF〇s)作為單 毛曰日體§己憶體裝置的最好結構。但是，鐵電特性良好的c 軸疋向PGO(氧化鉛鍺（p^GegOu))薄膜卻難以沈積於閘極 氧化物之上，因為介面不匹配。為解決該問題，會在pG〇 薄膜與該閘極氧化物間使用一緩衝層。 C· J· Peng等人所著的「藉由準分子雷射刻除而定向的 鍺酸鉛薄膜（Oriented lead germinate, thin films by excimer laser ablation)」說明瞭鐵電薄膜之準分子雷射刻除領域的 早，工作。該文章發表於<應用物理通訊（Appl phys Lett)> ，卷60 ，頁 827-829 (1992)。 J.J.Lee等人所著的「在45〇c下使用^軸定向處理單軸 鐵 ％ Pb5Ge3〇H 薄膜（processing a uniaxiai ferr〇electric Pt^GesO" thin film at 450°C with c-axis orientation)」說明 瞭藉由溶膠-凝膠（sol-gel)製程製造鍺酸鉛薄膜，產生不會 裂的、c軸定向的薄膜。該文章發表於 <應用物理通訊 >，卷 60 ， I 2487-2488 (1992) 〇 H. Schmitt等人所著的「未摻雜及摻雜鐵電鍺酸鉛薄膜之 特性（Properties of undoped and doped ferroelectric lead germinate thin films)」說明瞭製造鍺酸鉛薄膜的反應濺射 技術。該文早發表於〈鐵電（Ferroelectrics)〉，卷56，頁 141-144 (1984)。 S.B.Krupanidhi等人所著_的「鐵電薄膜之脈衝準分子雷 射沈積（Pulsed exclmer laser deposition of ferroelectric thin Hlms)」說明瞭錯鈕酸鉛、钽酸鉍及鍺酸鉛之脈衝紫外 (3) (3)
線雷射刻除。發表於第三屆關於積體鐵電之國際討論會上 ，頁 100-115 (1991)。 發明概要 本發明揭示一種製造記憶體裝置的方法，其包含準備一 矽基板，在該矽基板上沈積一高k絕緣體層；在該高k絕緣 層上沈積一緩衝層；藉由金屬有機化學氣相沈積法在該緩 衝層上沈積一鐵電材料層；在該鐵電材料層上形成一上方 電極；以及完成藉由上述步驟所獲得的裝置。 本發明的一目標-是提供一種製造MF〇s單晶體記憶體裝 置的方法。 本發明的另一目標是製造在該基板及該鐵電之間夾入一 高k及緩衝層之MF〇s記憶體裝置以制止鐵電特性降低。 本發明的另一目標是使用金屬有機化學氣相沈積 (MOCVD)技術製造沈積在高k材料（如Zr〇2、Hf〇2&(Zrx， ΗΛ·χ)03)層上的高c軸定向PG0薄膜以用於一 pG〇 MF〇s 1T記憶體應用中，其中會使用一鈕緩衝層。 提供本發明的摘要及目標是為了快速理解本發明的本質 。藉由參考以下結合圖式對本發明的較佳具體實施例所作 的詳細說明，可更充分地認識本發明。 圖式之簡蕈說明 圖1為使用現地氧化退火·製程在鈕/Zr02上沈積的PGO 薄膜之X射線圖案。 ·- 圖2為使用現地氧化退火製程在鈕/Hf〇2上沈積的pG〇 薄膜之X射線圖案。 564502
(4) 圖3為鈕/Zr〇2層上的PGO MFOS結構之記憶體視窗。 圖4為鈕/Hf02層上的PGO MFOS結構之記憶體視窗。 圖5為上方電極進行電漿蝕刻後的具有鈕/Zr02之PGO MFOS記憶體單元的記憶體視窗。 圖6為上方電極進行傳統蝕刻後的具有钽/Zr02之PGO圖 案MFOS記憶體單元的記憶體視窗。 較佳具體實施例之詳細說明
為製造高品質的PGO MFOS記憶體單元，會將氧化鍺鉛 (Pb5Ge3On)(PG〇）薄膜沈積於具有一钽或Ti02緩衝層之高 k閘極氧化物（如Zr02及Hf02)上。此種在具有一鈕或Ti02 缓衝層的Zr02、Hf02或（Zrx，Ηίνχ)02上之高c軸定向的PGO 薄膜製造，已可藉由在單一記憶體應用中使用最佳金屬有 機化學氣相沈積（MOCVD)及兩步退火製程而達到。經測量 ，具有钽/Zr02及钽/Hf02的PGO MFOS之記憶體視窗係分別 大於2.2 V及3.5 V，此類視窗足以供單一電晶體應用。電漿 蝕刻對钽/Zr02及钽/1^02上形成的PGO薄膜之損害已得到 檢查，並減至最小化。 發明方法 本發明之方法包含製造具有PGO MFOS結構的單一電晶 體鐵電記憶體裝置，其包含形成于一高k閘極氧化物（如 Zr03及Hf02)層上之高c軸定向的PGO薄膜，其中該高k層及 該PGO薄膜間會形成一钽或Ti02緩衝層。該絕緣/緩衝夾層 可制止該氧化物侵入該鐵電或矽基板。 一 P型矽晶圓用作該MFOS單晶體記憶體應用之基板。該 564502 8一 _麵 矽晶圓係經過SC1 + SC2清洗；其中SC丨是55〇〇亳升去離子水 、1100毫升NH4OH及1100毫升h2〇2的混合物，而該SC2 = 是6000毫升去離子水、1000毫升HC1&1〇〇〇亳升的曰 合物；表面氧化物藉由高頻浸入蝕刻而移除。一： ，如冰、_2或（Zrx，Hfl-x)〇2薄膜，賤射於該石夕 ，大約厚2奈米至20奈米，最好係大約厚2奈米至8奈米。具 有該高k層的該矽晶圓在一大約5⑻?〇至55〇^：的純氧環境 下大約退火一分鐘至二十分鐘以達到完全氧化。一緩衝= ，如鈕或Τι〇2，藉由濺射而沈積于該高k閘極氧化物上，沈 積厚度大約為2奈米至1〇奈米。 一氧化物MOCVD反應器用以在絕緣/緩衝夾層上生長大 約厚200奈米至300奈米之〇軸定向的PG〇薄膜。一大約厚 1〇〇奈米的pt上方電極藉由電子束蒸發而沈積於該PG〇薄 膜上。然後，使用傳統技術完成該記憶體裝置。
5亥P GO薄膜藉由MOCVD而沈積，其中會使用一 p G〇先驅 物’其藉由將[Pb(thd)2](其中 thcKnHwOs)與[Ge(ETO)4] (其中£丁0=〇(：3115)(兩者的摩爾比率為5.〇至5.5:3)溶解到丁 基醚或四氫呋喃、異丙醇及四一二醇二曱醚（三者的摩爾比 率為8:2:1)的混合溶劑中而形成。該先驅溶液的濃度為H 摩爾/公升PGO。該溶液在大約i50°C至25(TC的溫度下以 〇·!毫升/分鐘至0.2毫升./分鐘的速度通過一泵注入一汽化 器’以形成先驅氣體。生長線的溫度大約介於165°C至245 °C間。該MOCVD在大約350°C至450°C的沈積溫度、大約5 ton*的氣壓及大約30%的氧分壓下實施。c軸定向的PGO 564502
⑹ 薄膜之退火製程條件包含在氧環境中、大約5〇〇°c至51〇。〇 的退火溫度下、使用快速熱處理（rapid thermal pr〇cessing ;RTP)技術、實施5分鐘至10分鐘作為第一退火步驟。第二 退火步驟在大約540°C至6001的溫度下、在氧環境中、在 一 RTP室或一退火爐中實施大約30分鐘至一小時。 使用X射線繞射識別該PG0薄膜的相位。使用極高解析 度的X射線光電子譜儀（XPS)分析該膜的組成。 使用一Keithley 182 CV分析儀測量該PG〇 ^^(^電容器的 電容。 , 結果 使用傳統技術沈積於Zr〇2及Hf〇2上的c軸定向pG〇薄膜 ，通常具有第二相位和隨機峰值，結果造成不良的鐵電特 性。根據本發明之方法，為在供MF〇s 1T記憶體應用之高&
甲極氧化物上沈積尚定向的pG〇薄膜，會將PG〇薄膜 積於具有一緩衝層（如鈕或丁丨02)高1<氧化層上。本發明之 去產生PGO薄膜，其係非結晶的並在高溫退火後會出額 軸定向峰值。使用現地氧化而沈積於該緩衝層上的 膜，表現出高c軸定向。使用Zr〇AHf〇2並具有一链緩亂 的本發明之方法’可產生適合於記憶體應用的刚㈣ 裝置。鈕層的最佳厚度係介於2奈米至1〇奈米間，而Μ 與動2的最佳厚度則係介於4奈米至料米間。 =及2為根據本發明之方法在各種溫度下沈積於具有 曰的〜〜及㈣2上之？(}〇薄膜的X射線圖案。對於1 0涛獏，_0薄膜的成核溫度大約為喊，而晶〗 -11- 564502 ⑺ _翻瞒 mm舰⑹二y 生長溫度則大於540°C。因此，兩步退火製程用於在一 Zr〇2 及Hf02高k層上生長高c軸定向的PG〇薄膜，其中在該高k 介電層上會形成一钽缓衝層。在第一步驟中，PGO c軸相位 成核發生於5 10°C的退火過程中，對於c軸相位晶粒生長， 在大約540°C至600°C間退火。使用該技術，會在該鈕緩衝 層上形成一堅固的c轴定向PGO薄膜，其中該緩衝層位於該 高 k Zr02&Hf02層上。 ,
為決定本發明之方法對於製造PG〇MFOS IT電晶體裝置 的適用性，會製造PGO MFOS，其中一個具有钽/Zr02層， 另一個具有钽/Hf02層。圖3及4分別為具有钽/Zr02及Hf〇2 的PGO MFOS結構之記憶體視窗。具有钽/Zr〇2及Hf〇2的 PGO MFOS之記憶體視窗分別為2.2 V及3.5 V，這足以供單 一電晶體記憶體應用。
為決定使用本發明之方法而由電聚#刻引起的損害數量 ，具有Pt/PGO/鈕/Zr02/Si結構的PGO MFOS記憶體單元之上 方電極會使用低功率傳統蝕刻製程及電漿蝕刻製程加以蝕 刻。圖5及6分別為測量的上方電極的電漿蝕刻及上方電極 的傳統低功率蝕刻後測量的具有钽/ΖιΌ2記憶體單元之 PGO MFOS的記憶體視窗。此類圖式說明瞭具有钽/Zr〇2記 憶體單元之PGO MFOS的記憶體視窗在Pt上方電極進行電 漿蝕刻後從2.2 V下降至1.8 V，該電壓仍然足以供單一電晶 體記憶體裝置使用。 總之，藉由使用最佳的MOCVD及新穎的兩步退火製程， 在具有一鈕或Ti02缓衝層的Zr02及1-丨「02上形成高c軸定向 -12- 564502 ⑻ 的PG〇薄膜供單一電晶體記憶體應用；經測量，具有钽/Z:r02 及钽/Hf02的PGO MFOS之記憶體視窗大於2.2V及3.5V，這 足以供單一電晶體記憶體應用；該電漿蝕刻及剝離製程引 起的對沈積於鈕/Zr02及鈕/Hf02上之PGO薄膜的損害會藉 由本發明之方法而減少。
因此，以上已揭露供MFOS單一電晶體記憶體應用的具有 钽缓衝層之高K閘極氧化物的製造方法。應明瞭可對本發明 作進一步的變化及更改，而不致脫離在隨附的申請專利範 圍中定義的本發明之範疇。
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Claims (1)

  1. 564502 拾、申邊專利範圍 1 · 一種製造一記憶體裝置之方法 a)準備一梦基板； 其包含下列步驟： c)在该鬲k層上沈積一緩衝層； 二)：由金屬有機化學氣相沈積法在該 鐵電材料層； 及彳訂層上/尤積 2. 3. 4. ，該鐵電材料層上形成一上 > 電極；以及 f)7C成藉由步驟a)至e)而獲得的裝置。 如申請專利範固第旧之方法，其中該準備 =驟a)包含選擇-P财基板晶圓；清”二 圓及從該P料基板晶圓移除表面氧化物。^基板阳 如申請專利範圍第！項之方法，其中 積-高k絕緣體層之步驟b)包含從由 二:尤 之材料群中選擇，材料;沈St ，且 ：板士 ’沈積的厚度大約為2奈米至20奈米 55ίΤΓ…二勺厚2奈米至8奈米；以及在大約5〇〇°C至 C的、屯乳環境中退火大約—分鐘至二十分鐘。:申π專利乾圍第!項之方法，其中該沈積一緩衝金屬 ^之步驟e)包含從由輕及叫所組成的緩衝層之群中 選擇一緩衝層；沈積該緩衝層，沈積的厚度大約為2夺 米至1 〇奈米。
    申明專利範圍第1頊之方法，其中該沈積一鐵電材料層 之步驟d)包含準備-PG0之先驅物，其藉由將[Pb(thd)2] 564502 請翻範圍 "，-·*、、、 、— A/ , 與[Ge(ETO)4](兩者的摩爾比率為5.〇至55:3)溶解到丁 基_或四氫σ夫喃、異丙醇及四一二醇二甲&|(三者的摩 爾比率為8:2:1)之混合溶劑中而形成，該先驅溶液的濃 度為〇·1摩爾/公升PG0。 6·如申請專利範圍第5項之方法，其中該沈積一鐵電材料 層之步驟d)進一步包含在大約為15〇它s25(^c的溫度下 將該先驅溶液以大約〇· i毫升/分鐘至〇·2毫升/分鐘的速 度通過一泵注入一汽化器中，以形成一先驅氣體；並在 大、力350C至450C的沈積溫度，大約5 torr的壓力及大約 3 0%的氧分壓下將該先驅氣體用泵抽入一化學氣相沈積 室中。 、 7·如申請專利範圍第6項之方法，其中沈積該鐵電材料層 的忒矽基板在一第一退火步驟退火，其在大約5〇〇。〇至 5 10°C的退火溫度下之氧環境中使用快速加熱製程技術 實施大約5分鐘至10分鐘；以及在一第二退火步驟退火 ’其在大約540°C至600°C的退火溫度下之氧環境中實施 大約 3 0分鐘至一小時。 8· 一種製造一PGO MF0S單一電晶體記憶體裝置之方法， 其包含： a) 準備一矽基板； b) 在該石夕基板上沈積一高k絕緣體層，其包含 bl)從由Zr02、Hf02或（Zrx，HfVx)〇2所組成之材料 群組中選擇一高k材料，— b2)將該高k材料層沈積於該矽基板上，沈積的厚 -2 -
    564502 度大約為2奈米至20奈米，最好係大約厚2奈米至8奈米； 以及 b3)在一大約500。〇至55〇。〇下的純氧環境中退火 該矽基板，退火時間大約為一分鐘至二十分鐘； .Ο在該高k絕緣層上沈積—緩衝層，其包含從由组及 τω2所組成的緩衝層之群中選擇一緩衝層；以及沈積該 緩衝層，沈積的厚度大約為2奈米至1〇奈米； 幻藉由金屬有機化學氣相沈積法在該緩衝層上沈積 · 一鐵電材料層； e) 在該鐵電材料層上形成一上方電極；以及 f) 元成藉由步驟a)至e)而獲得的裝置。 9.如申明專利範圍第8項之方法，其中該沈積一鐵電材料 層之步驟d)包含準備一 PG〇之先驅物，其藉由將 [Pb(thd)2]與[Ge(ETO)4](兩者的摩爾比率為5 〇至5 5:3) 溶解到丁基醚或四氫呋喃、異丙醇及四一二醇二甲醚 (一者的摩爾比率為8:2:丨）之混合溶劑中而形成，該先驅 溶液濃度為〇·1摩爾/公升PG〇 ; · 在大約為150°C至2501的溫度下以大約〇」毫升/分鐘 至0.2毫升/分鐘的速度通過一泵將該先驅溶液注入一汽 化為中’以形成一先驅氣體；並在大約350°C至450。(3的 沈積溫度、大約5 torr的壓力及大約30%的氧分壓下將該 先驅氣體用泵抽入一化學氣相沈積室中；以及 在一兩步驟退火製程中_退火該矽基板，其包含： 第一退火步驟，其在一大約5〇〇°C至5 10°C溫度下的 564502
    氧環境中使用快速加熱製程技術實施大約5分鐘至10分 鐘；以及 一第二退火步驟，其在一大約540°C至600°C溫度下 的氧環境中退火大約3 0分鐘至一小時。 ίο. 如申請專利範圍第8項之方法，其中該準備該矽基板之 步驟a)包含選擇一 p型矽基板晶圓；清洗該p型矽基板晶 圓及從該P型矽基板晶圓移除表面氧化物。 11. 一種製造一PGO MFOS單一電晶體記憶體裝置—之方法， 其包含： a) 準備一矽基板； b) 在該矽基板上沈積一高匕絕緣體層，其包含 匕1)從由21*02、沿〇2或（2^，财11)〇2所組成之材 料群組中選擇一高k材料， 同κ珂料層於該矽基板上于反入 約2奈米至20奈米，最好係大約厚2奈米至8奈米；以及 b3)在一大約500。〇：至55〇。〇的純氧環境中退火該 矽基板，退火時間大約為一分鐘至二十分鐘； • Ο在該高k絕緣層上沈積一缓衝層，#包含從由起及 Ti02所組成的緩衝層之群中選擇一緩衝層；沈㈣緩衝 層’沈積厚度為2奈米至1〇奈米； d)藉由金屬有機化睪氣4i 例卞虱相沈積法在該緩衝層上沈積 一鐵電材料層，包含 、 dl)準備'一 PGO之务~导庶私？ 甘一 "勿，稭由將[Pb(thd)71盘 [Ge(ETO)4](兩者的摩爾比率 一卜、 手卿比年為）.〇至W3)溶解到丁基醚 -4 ·
    或四氫σ夫喃、異丙醇及四一二醇二甲醚（三者的摩爾比率 為8:2:1)之混合溶劑中而形成，該PGO先驅溶液濃度為 〇·1摩爾/公升； d2)在大約為150°C至250°C的溫度下以大約01 至0.2 ml/min的速度通過一泵將該先驅溶液注入 一汽化器中，以形成一先驅氣體；並在大約35〇°C至450 c的沈積溫度、大約5 torr的壓力及大約30%的氧分壓下 將該先驅氣體用泵抽入一化學氣相沈積室中；以及 d3)在一兩步驟退火製程中退火該矽基板，其包含 第一退火步驟’其在一大約500 °C至510 °C溫度 的氧環境中使用快速加熱製程技術實施大約5分鐘至i 〇 分鐘；以及 一第二退火步驟’其在一大約540 °C至600 °C的 溫度的氧環境中實施大約30分鐘至一小時； e) 在該鐵電材料層上形成一上方電極；以及 f) 完成藉由步驟a)至e)而獲得的裝置。 如申請專利範圍第11項之方法，其中該準備該矽基板之 步驟a)包含選擇一 P型矽基板晶圓；清洗該p型矽基板晶 圓及從該P型矽基板晶圓移除表面氧化物。 12.
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