TW550770B - Optical integrated circuit element package and process for making the same - Google Patents

Optical integrated circuit element package and process for making the same Download PDF

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TW550770B
TW550770B TW091107808A TW91107808A TW550770B TW 550770 B TW550770 B TW 550770B TW 091107808 A TW091107808 A TW 091107808A TW 91107808 A TW91107808 A TW 91107808A TW 550770 B TW550770 B TW 550770B
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Taiwan
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substrate
chip
wafer
patent application
optical
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TW091107808A
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Su Tao
Kuo-Chung Yee
Jen-Chieh Kao
Chih-Lung Chen
Hsing-Jung Liau
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Advanced Semiconductor Eng
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Priority to US10/355,152 priority patent/US6693364B2/en
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/732—Location after the connecting process
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2924/01—Chemical elements
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Light Receiving Elements (AREA)
  • Optical Couplings Of Light Guides (AREA)

Description

550770 五、發明說明（1) 【發明領域】 本發明係關於一種光學積體電路元件之封裝構造，尤其 係關於一種具有光學積體電路元件之球格陣列 array ; BGA)封裝構造。 【先前技術】 隨著光-電技術的進步，已有越來越多的光—電元件，例 如光源發散元件（light emitting device)或感光元件 (photosensitive device )，廣泛地用於各類不同的光 學產品裡，諸如掃描器，電腦條碼讀取機，數據通訊系統 等…。而在一般的光-電應用上，係將積體電路晶片型式 之光-電元件，置於一封裝結構中，且該封裝結構具有一 透明密封之窗口 （window )，利用光學原理，光束穿過該 封裝結構之透明密封窗口，使得該感光元件得以感應光學 訊號’或從光源散發元件產生之光束得以藉由該窗口發散
* * ° RWT 先前的技術中已有許多關於積體電路晶片型式之光-元件之封裝構造，如2000年4月18日頒於Webb之美國專利 第6, 051，848號，發明名稱為”包含一光學傳輸晶粒之光學 元件封裝構造（Optical device packages containing an optical transmitter die)'，，其揭示一種光學裝置，包 含一光學傳輸晶粒以及一封裝結構，該封裝結構具有封閉 (encapsulate )該晶粒之模造（moid )材料。然而，該 封裝結構之製造步驟係為黏晶，打線，封膠，彎腳成形之 傳統方式，其所佔的體積太大，製造上耗時且昂貴。
L I麵
P〇l-178.ptd 第6頁 550770 五、發明說明（2) 再者’積體電路晶片產生之熱量如 封裝構造逸散出去，一直是吾人所關 電T單元低外型（low-profile ： 夕日日片核組（mul tich ip module )已 勢。 因此’對於光學元件之封裝業者， 學=件之封裝構造，符合低外型的要 組装之半導體構件，並且能夠以較低 【發明概要】 本發明之主要目的係提供一種光學 構造，符合低外型的要求，具有高密 的散熱性，並能夠以較低的成本製造 本發明之次要目的在於提供一種光 裝構k之製造方法，其中該封裝構造 具有高密度的組裝結構，良好的散熱 成本製造。 為達上述目的，本發明提供一種光 裝構造，包括：一基板，具有複數個 ball )位於该基板之一表面上、複數 鲜锡球、一外蓋加裝於該基板之另一 以裸露出該外蓋；一上部晶片，具有 熱間隙填充料（thermal gap fill) $蓋上；一底部晶片，具有複數個銲 曰曰片之該衩數個凸塊，以及複數個凸 何有效且迅速地從該 心的。又，為了能夠 >要求，更高密度之 成為現今之發展的趨 便有需要提供一種光 求，能夠提供高密度 的成本製造。 積體電路元件之封裝 度的組裝結構，良好 〇 學積體電路元件之封 符合低外型的要求， 性，並能夠以較 ·.一〜^… 學積體電路元件之封 銲錫球（solder 個銲墊電性連接至該 表面、以及一開口用 複數個凸塊，且藉由 黏著於該開口處之該 塾電性連接於該上部 塊電性連接至該基板
550770 五、發明說明（3) --- 之該複數個銲墊；一光學透明填充料，位於該底部晶片以 及該上部晶片間；以及一密封塑料，密封地填充於該底 晶片與該基板間之空隙。 一 本發明另提供一種光學積體電路元件封裝構造之製造方 法’其包括步驟：提供一基板，具有複數個銲錫球 (solder ball )位於該基板之一表面上、複數個銲墊電 性連接至該銲錫球、一外蓋加裝於該基板之另一表面、以 及一開口用以裸露出該外蓋；提供一上部晶片，具有複數 個凸塊2提供一底部晶片，具有複數個銲墊以及複數個凸 塊；將該上部晶片連接至該底部晶片，且該上部晶片之複 數個凸塊電性連接至該底部晶片之複數個銲墊；於該底部 ，片以及遠部晶片間注入一光學透明填充料；將該底部 曰曰片連接至忒基板，且讜底部晶片之複數個凸塊電性連接 至4基板之複數個銲墊，其中該上部晶片與該外蓋間填充 一熱間隙填充料（thermal gap fi 1 1)。 ' 如則所述，根據本發明之該光學元件封裝構造係為一 g 強，熱之球袼陣列（Thermo Enhance Ball Grid Array)封 表、口巧v、有光學元件之晶片係藉由熱間隙填充料與一散 熱外蓋相接觸’藉此提供了一迅速散熱之路徑。又，於根 據=發明之封裝構造中，該具有光學元件之晶片係以覆晶 P 1 P )方式封裝’省去傳統打線（w i r e b ο n d i n g )之步驟’藉此降低製造成本，並可達到高密度的組裝結 構。 為了讓本發明之上述和其他目的、特徵、和優點能更明
550770
實施例 並配合所附圖示， 顯特徵，下文特舉本發明較佳 作詳細說明如下。 【發明說明】 2…本f:可表現為不同形式之實施例，但附圖所示者 及；下文—w兒明者係為本發明可之較佳實施例，並請了解 本文所揭示者係考量為本發明之一範例，且並非意圖用以 將本2明限制於圖示及/或所描述之特定實施例中。 現咕參考第1圖所示，根據本發明之較佳實施例之一光 學積體電路元件之封裝構造1，包含一基板1〇、一上部晶 片（upper chip ) 20、一底部晶片（1〇wer chip ) 3〇、以 及一外蓋6 0。 該基板1 0具有一第一表面丨丨具有複數個銲錫球 (solderballs ) 14、一第二表面12用以與該外蓋60相結 合、以及一矩形之開口13(見於第2圖中）。 该上部晶片20具有一光—電元件，諸如垂直凹穴表面 射雷射驅動器（Vertical Cavity Surface Emitting 二 Laser Driver ; VCSEL Driver)晶片或光學接收器晶片。 該上部晶片20之主動表面（active surface)上具有複數個 凸塊（bump ) 35(見於第3a圖中）與該底部晶片30之主動表 面上之複數個銲墊25(見於第3a圖中）電性連接。該底部晶 片30係包括一光學透明基板（optical-transparent substrate ) 42，其上可形成多種主動元件，諸如該光電 元件之驅動電路、類比訊號與數位訊號之轉換電路、以及 電子式可清除程式化唯讀記憶體（EEPR0M )。該透明基板
P01-178.ptd 第9頁 550770 五 、發明說明（5) 42可為鋼石（sapphire ;亦稱為藍寶石）基板、玻璃基 板、石英、以及透明的塑膠基板。該上晶片2〇之凸塊35係 由金（Au)或銲錫（s〇ider)構成。該底部晶片30具有複 數個凸塊26(見於第4b圖中），用以電性連接至該基板10之 该第一表面11上之複數個銲墊16(見於第4b圖中）。精於本 技藝者將可瞭解該凸塊3 5、2 6係分別成形於該上部晶片2 〇 之鲜塾24及該底部晶片30之銲墊15上（見於第4a及柚圖 中）。如第1圖所示，該底部晶片3〇覆蓋買該基板1〇之該開
一光學透明填充料（opticabtransparent underfiu )40係注入於該底部晶片3〇與該上部晶片2〇間，用以阻擋 f氣渗透導致短路。一密封塑料38係密封地填充於該底部 曰曰片3 0之周圍與該基板丨〇之開口丨3之周圍間之空隙。一熱 間隙填充料（thermal gap fin ) 50係填充於該上部晶片 2 〇與该外盍6 0之間。該外蓋6 〇 一般係由良好的熱傳導金屬 材料所製造，諸如銅、鋁等，且該熱間隙填充料5 〇具 好，導熱性，藉此使該上部晶片2〇所產生的熱量能夠 的藉由該外蓋6 0散發。
一精於本技藝者將可瞭解，根據本發明之該光學積體電路 元件之封裝構造1可用以與多個光學元件相聯結，諸如光 纖、導波管（waveguide )、反射鏡或透鏡，藉此使該基 板上之該電氣訊號可與該光學元件上之光學訊號交互作 現請參考第2-5圖，其顯示根據本發明之製造方法。如
550770 五、發明說明（6) 第2圖所示，一基板10具有一第一表面11具有複數個銲錫 球（solderballs) 14、一第二表面12用以與該外蓋60相 結合、以及一矩形之開口 1 3。又，該基板1 〇另包括複數個 銲墊1 6位於該基板10之第一表面11。該基板1〇 一般係以玻 璃纖維強化B T (b i s m a 1 e i m i d e -1 r i a z i n e )樹脂製成之印刷 電路板。 現請參考第3及3a圖，一上部晶片20之主動表面上具有 複數個銲墊2 4，其上形成複數個凸塊3 5。該底部晶片3 〇之 主動表面上有複數個銲墊2 5，該凸塊3 5係以熱壓銲 (thermal compression )加工，接合至該底部晶片3〇之 相對應的銲墊25，並且電性連接。一光學透明填充料4〇係 填充於該上部晶片20與該底部晶片30間之間隙，用以防止 水氣的滲入，並增加該凸塊3 5之抗疲勞壽命。較佳者，該 光學透明填充料40之射率範圍在1· 4〜1· 6之間。 人 再請參考第4及4a圖，該底部晶片30之周邊具有複數 銲墊1 5 ’其上形成複數個凸塊2 6。該凸塊2 6係藉由熱#隹翠 加工，電性’連接至&該基板1()上之銲墊16。精於本^藝者 亦可瞭解，一密封塑料38係密封地填充於該底部晶片之 ，圍與該基板1 〇之開口丨3之周圍間之空隙。同時，於該上 ，晶片20的背面塗佈一熱間隙填充料5〇，用以黏著至=外 =60，即完成根據本發明之該光學積體電路元件之封^構 孰 請注意，精於本技藝者將可瞭解，該外蓋6〇通常係 良好之金屬材料所製造，且可藉由任何加工，諸如黏月
550770 五、發明說明（7) 著，力π裝至 片3 0力口裝至 片可塗佈該 上部晶片1 0 該基板60。 此外，精 明基板具有 上之光電元 如前所述 造，具有良 的由該外盖 雖然前述 須瞭解到各 施例，而不 理之精神及 於很多形式 改。因此， 為用以說明 應由後附中 不限於先前 於本技 一開口 件能夠 ，根據 好的散 散發。 的描述 種增添 會脫離 範圍。 、結構 本文於 本發明 請專利 的描述 該基板10上。再者，該外亦可於該底部晶 該基板10之後，再加裝於該基板10。該上部晶 熱，隙填充料50，而於加裝至該基板1〇時，該 亦精由該熱間隙填充料5〇黏著至該開口 13處之 Ϊ者將可瞭解，該底部晶片30之光學透 窗（open window )，使該上部晶片2〇 透過該開口窗接收或發散光線。 本發明之該光學積體電路元件封裝構 熱性，能夠使該晶w裕立丄再 之茨片所產生的熱量迅速 '匕已揭示本發明之較佳實施例，必 、修改：取代可能使用於本發明 如所附""利範圍 斤 熟悉該技藝者將可體合士政旧不嗌月土 、佈置、比例、材料、元鲒 ，而非用以限制本發:；；有：t，應!皮視 範圍所界定，纟涵蓋复 么明的犯圍 。 盒其合法均等物，並
P01-178.ptd 第12頁 550770 圖式簡單說明 【圖示說明】 第1圖··係為根據本發明之一較佳實施例之一光學積體 電路元件之封裝構造之剖面視圖。 第2圖：係為根據本發明之該實施例之一基板之剖面視 圖。 第3圖··係為根據本發明之該實施例之一上部晶片連接 至下部晶片之剖面視圖。 第3a圖：係為第3圖中區域3a的局部放大視圖。 第4圖：係將第3圖中該上部晶片及該下部晶片之結合體 連，至第2圖中之該基板上。 第4a圖：係為第4圖中區域4a的局部放大視圖。 圖號說明 P01]78.ptd 光學積體 電路元件之封裝構造 基板 第一表面 12 第二表面 13 開口 鲜錫球 15 銲墊 16 銲墊 上晶片 25 銲墊 24 銲螯 凸塊 30 底部晶片 連接元件 35 凸塊 光學透明填充料 熱間隙填充料 鋼蓋 mil 第13頁

Claims (1)

  1. 550770 六、申請專利範圍 1 · 一種光學積體電路元件之封裝構造，包括： 基板’具有複數個銲鍚球（s 0 1 d e r b a 1 1 )位於該基 板之一表面上、複數個銲墊電性連接至該銲錫球、一外蓋 加裝於該基板之另一表面、以及一開口用以裸露出該外 蓋； 一上部晶片’具有複數個凸塊，且藉由一熱間隙填充料 (thermal gap f i 11 )黏著於該開口處之該外蓋上； 一底部晶片，具有複數個銲墊電性連接於該上部晶片之 該複數個凸塊，以及複數個凸塊電性連接至該基板之該複 數個銲墊； 一光學透明填充料，位於該底部晶片以及該上部晶片 間；以及 一密封塑料，密封地填充於該底部晶片與該基板間之空 隙。 2 ·依申請專利範圍第1項之光學積體電路元件之封裝構n 造，其中該上部晶片具有光-電元件。 3.依申請專利範圍第1項之光學積體電路元件之封裝構 造，其中該上部晶片為一垂直凹穴表面發射雷射驅動器 (Vertical Cavity Surface Emitting Laser Driver ； VCSEL Driver)晶片。 4·依申請專利範圍第i項之光學積體電路元件之封裝構
    P01-178.ptd 第14頁 550770 學接收器晶片 六、申請專利範圍 造’其中該上部晶片為一光 板，具有電路元 5·依申請專利範圍第1項之光學接麟+ 一 造，其中該底部晶片係為一光學透明義路兀件之封裝構 件。 土 6 ·依申睛專利範圍第5項之光學積體雷敗$杜封# M 造，其中該光學透明基板係為—c件之封裝， 板。 现貞石（sapphi re )基 7 ·依申請專利範圍第1項之井風拉遍 造，其中該光學透明填充料之電路元件之封裝構 之間。 具兄卄之折射率範圍係介於1.4至1. 8驟T種光學積體電路元件封裝構造之製造方法，其包括步 該：板之一表面：(s〇ider ban)位於 外蓋加裝於該基板之另】；墊電性連接至該銲錫球、-外蓋； 表面、以及一開口用以裸露出該 提供一上部晶片，具有複數個凸塊； 底部晶片，具有複數個銲墊以及複數個凸塊·， Λ ^雪Γ曰曰片連接至戎底部晶片，且該上部晶片之複數個 凸鬼電性連接至該底部晶片之複數個銲墊； 個 P〇M78.ptd 第15頁 550770
    於該底部晶片以及該上部晶片間注入一光學透 料； 異充 將該底部晶片連接至該基板，且該底部晶片之複數 塊電性連接至該基板之複數個輝墊，其中該上部晶片與 外蓋間填充一熱間隙填充料（thermal gap fill)。曰，、該 9 ·依申請專利範圍第8項之製造方法，其中該上部晶 有光-電元件。 10·依申請專利範圍第8項之製造方法，其中該上部晶片 為一垂直凹穴表面發射雷射驅動器（Vertical Cavity Surface Emitting Laser Driver ;VCSEL Driver)晶片。 11·依申請專利範圍第8項之製造方法，其中該上部晶片 為一光學接收器晶片。 ^__ 门 ml 12·依申請專利範圍第8項之製造方法，其中該底部晶片 係為一光學透明基板，具有電路元件。 13·依申請專利範圍第丨2項之製造方法，其中該光學透明 基板係為一藍寶石（sapphire )基板。 14·依申請專利範圍第8項之製造方法，其中該光學透明 填充料之折射率範圍係介於1. 4至1. 6之間。
    P0M78.ptd 第16頁
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