TW544787B - Method of forming self-aligned contact structure with locally etched gate conductive layer - Google Patents
Method of forming self-aligned contact structure with locally etched gate conductive layer Download PDFInfo
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- TW544787B TW544787B TW091121343A TW91121343A TW544787B TW 544787 B TW544787 B TW 544787B TW 091121343 A TW091121343 A TW 091121343A TW 91121343 A TW91121343 A TW 91121343A TW 544787 B TW544787 B TW 544787B
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- 238000000034 method Methods 0.000 title claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000005530 etching Methods 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 30
- 125000006850 spacer group Chemical group 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 238000001459 lithography Methods 0.000 claims description 17
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 107
- 230000015572 biosynthetic process Effects 0.000 claims 6
- 239000000203 mixture Substances 0.000 claims 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims 1
- 235000014676 Phragmites communis Nutrition 0.000 claims 1
- 235000011114 ammonium hydroxide Nutrition 0.000 claims 1
- 239000011247 coating layer Substances 0.000 claims 1
- 239000012792 core layer Substances 0.000 claims 1
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 238000013467 fragmentation Methods 0.000 claims 1
- 238000006062 fragmentation reaction Methods 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000002360 preparation method Methods 0.000 claims 1
- 239000004576 sand Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 229940098465 tincture Drugs 0.000 claims 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000006117 anti-reflective coating Substances 0.000 description 3
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
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- 239000012535 impurity Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
544787 A7 B7 五、發明説明（1 ) 發明範疇 本發明係關於一種形成自我對準接觸窗結構之方法；特 定而言，本發明係為一種去除先前技藝在半導體製程中所 形成之閘極導體/位元線接觸窗（gate conductor/bitline contact，GC/CB )短路的缺點和增加較大的製程容許範圍 (process window )之方法。 發明背景 一般而言，金屬氧化物半導體（MOS)裝置係由金屬層、 氧化矽層及基板所構成。由於金屬與氧化物的黏著性不 佳，常使用多晶矽取代金屬以形成MOS裝置的閘極結構之 導電層。然而，多晶矽之缺點係在於其電阻較金屬為高， 雖然其可藉由雜質摻雜以降低電阻，然而所產生的導電性 仍無法作為MOS裝置中良好的導電層。一種常見的解決方 法是在多晶矽層上增加一層金屬矽化物，例如矽化鎢（WSi) 層，以改良閘極結構之導電性。 在先前技藝中，形成接觸窗結構的方法包括下列步騾： 形成介電層、形成接觸窗（contact window )以及形成金屬 層。在形成金屬層與基板間的金屬接觸（metal contact ) 時，最廣泛使用的方法是自我對準蝕刻方法。 圖1A至圖1C所示係為形成閘極結構之傳統方法，其過 程如下所述： 參考圖1A，首先準備一基板2;接著在基板2上形成複 數個分離之閘極結構，其中各個閘極結構包括一第一導電 層4、一第二導電層6、一絕緣層8以及一側壁間隔層 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
裝 訂
線 544787 A7 B7 五 發明説明（ (spacer) 1〇。在閘極形成後，形成一介電層12覆蓋整個基 板2 〇 參考圖1B，接著在介電層12上實行微影及蝕刻步驟以在 閑極結構之間移除一選定的部分直至基板2之上表面暴露 出來。該I虫刻步驟亦對絕緣層8及側壁間隔層1〇有效，因 為其餘刻率較慢，因此只有部分的絕緣層8及側壁間隔層 1〇亦被姓刻。結果，在閘極結構之間形成接觸窗2()，其可 自我對準至基板2上形成接觸區域之位置。如圖中所示， 接觸區域係形成於基板2的暴露表面處，其寬度為X。 參考圖1C，接著在整個該基板的上表面沈積一特定厚度 的金屬層14以覆蓋介電層12之暴露表面、閘極結構之側 壁間隔層10以及基板2。藉此在自我對準接觸窗2〇中於金 屬層14及基板2之間形成一寬度為X之金屬接觸。 月5述自我對準接觸之接觸電阻（contact resistance)值係與 金屬層14及基板2之間之接觸區域（也就是由寬度χ所標 示的區域）成比例。在蝕刻過程中可藉由延長蝕刻時間之 方法以增大接觸區域。然而如果蝕刻時間控制不當，該方 法會造成絕緣層8及側壁間隔層1〇被過度蝕刻，而使其下 万的第二導電| 6被暴露出來。第二導電層6被暴露出的 部分會在點16與金屬層14接觸而造成短路。 為了改善上述之傳統製程，先前技藝美國專利第 5,989,987號案提供-種形成自我對準接觸窗結構之改良方 法（請參考圖2Α至2D所示），該方法如下所示： 參考圖2Α，首先準備一基板2，其上依序為一第一導電
裝 訂
544787
層、4 ^一第二導電層6以及一絕緣層8，其中該第一導電層 為夕曰曰夕（P〇lysmcon)層或非晶碎（amorphous silicon) 層，接著藉由乾式蝕刻（dry etching)蝕刻至基板2之表面 以形成複數個分離的閘極結構。 參考圖2B，接著以厕4〇11，响和h2〇混和的蝕刻劑 (咖!虫刻第二導電層6。雖然該钱刻劑的目的係用於 蝕刻第二導電層6，但是也會以較慢速率蝕刻其下之第一 導電層4。蝕刻完成後，在各個間極結構上形成一側壁間 隔層10。 參考圖2C，接著在整個該基板的上表面形成一介電層 =覆盍所有閘極結構以及基板2之暴露表面。而後移 除介電層12在問極結構之間的選定部分直至基板2的上表 面被暴露出。 參考圖2D，接著在整個該基板的上表面沈積一特定厚度 的至屬層14以覆蓋介電層12之暴露表面、閘極結構之側壁 門隔層10以及基板2。藉此在自我對準接觸窗汕中於金屬 層14及基板2之間形成一金屬接觸。 上逑先前技藝美國專利第5,989,987號案所提供方法之優 在万、夕了個針對第二導電層6之蝕刻步驟，藉由此一 ，刻步驟造成第二導電層6之寬度較其上絕緣I 8為窄， y成車又大I程容許範圍（process window )以避免第二 導呢層6在點ι6處與金屬層14接觸而造成短路。 、然而，美國專利第5,989,987號案所提供之形成自我對準 接觸囱結構〈万法有下列缺點：⑴第二導電層6之姓刻
4 五、發明説明（ 步如為^面性餘刻，對於不會造成閘極導體/位元線 ^路的區域’第二導電I 6亦被#刻，由於第二導電層6 <兩«面積變小’造成間極導體 ::步:::成面第二導電層6與第-導電心^ 1：)=料少過多時，在後續製程則會造成剝離 發明概述 本發明之主要目的係在於提供形成具有局部蝕刻第一導 電層之自我對準接觸窗結構之方法，該等方法所形= 我對準接觸窗結構可形成較大製程容許範圍、第二=電= <截面積、電阻值並避免第二導電層與第一 $電層之間之 剝離現象。根據本發明第—實施例之方法包括： (1) 在一基板的整個上表面上沈積一第一導電層； (2) 在該第一導電層的整個上表面上沈積一第二導電層； (3) 在該第二導電層的整個上表面上沈積一絕緣層，·均 (4) 執行微影及蝕刻製程以形成複數個閘極結構； (5) 在整個該基板上沈積一光阻材料層，或先沈積一層抗 反射層（anti-refiective coating，ARC)後再沈積—光阻材料層； ⑹以位元線節點光罩（biMine c_act n〇de咖叫使用微影 製私或微影及蝕刻製程以移除在各個閘極結構用於形成位 元線接觸點之側之該光阻材料層或該光阻材料層及該抗反 射層形成至少含有一開口暴露部份閘極結構直至基板表 面； (7)使用對第二導電層之蝕刻率高於對該絕緣層及該第一 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 544787 A7 B7 五、發明説明（5 ) 導電層之蝕刻率的一蝕刻劑以蝕刻該暴露閘極結構用於形 成位元線接觸之側之該第二導電層； (8) 移除該光阻材料層或該光阻材料層及該抗反射層； (9) 在各個閘極結構的侧壁上形成一侧壁間隔層； (10) 形成覆蓋整個該基板之一介電層； (11) 藉微影及蝕刻製程移除在各個閘極結構之間用於形成 位元線接觸之側之介電層直至基板之表面被暴露出以形成 自我對準接觸窗；以及 (12) 形成覆蓋介電層的被暴露出之表面、閘極結構之側壁 間隔層的一金屬層，並在該金屬層和該基板之間被暴露出 之基板表面形成自我對準接觸。 根據本發明另一實施例之方法包括： (1) 在一基板的整個上表面上沈積一第一導電層； (2) 在該第一導電層的整個上表面上沈積一第二導電層； (3) 在該第二導電層的整個上表面上沈積一絕緣層； (4) 執行微影及蝕刻製程以形成複數個閘極結構； (5) 在整個該基板上沈積一光阻材料層，或先沈積一層抗 反射層（anti-reflective coating，ARC)後再沈積一層光阻材料 層； (6) 以位元線接觸窗光罩（bit-line contact mask)使用微影製 程或微影及蝕刻製程以在閘極結構間形成至少含有一圓形 開口暴露部份閘極結構直至基板表面； (7) 使用對第二導電層之蝕刻率高於對該絕緣層及該第一 導電層之蝕刻率的一蝕刻劑以蝕刻該暴露閘極結構之該第 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） )44787 A7 ---------B7 五、發明説明（6 ) 一·導電層； (8)移除Μ光阻材料層或該光阻材料層及該抗反射層； ()在各個閉極結構的側壁上形成一側壁間隔層； (10) 形成覆蓋整個該基板之一介電層； (11) 藉微影及蝕刻製程移除在各個閘極結構之間用於形成 位讀接觸之側之介電層直至基板之表面被暴露出以形成 自我對準接觸窗；以及 0%成覆蓋介電層的被暴露出之表面、閘極結構之側壁 間隔層的-金屬層’並在該金屬層和該基板之間被暴露出 之基板表面形成自我對準接觸。 氣式簡單說明 ，本1明係藉由實施例與其圖式而描述，以使本發明之技 術内各、特徵與功效易於瞭解，其中 圖1Α至圖1C係為形成自我對準接觸窗結構之傳統方 法； 圖2Α至圖2D係為先前技藝美國專利第5,989,987號案形 成自我對準接觸窗結構之方法； y 圖3A至圖3F係為根據本發明第一實施例形成自我對準 接觸窗結構方法之各步驟後所得之結構； 卞 、圖4A至圖4B係為根據本發明第一實施例形成自我對準 接觸窗結構的方法之流程圖； 、 、圖5A至圖5F係為根據本發明第二實施例形成自我對準 接觸窗結構方法之各步驟後所得之結構； 圖5G係為圖5F中第二導電層之俯視圖；以及
544787 A7 B7 五、發明説明（7 ) 圖6A至圖6B係為根據本發明第二實施例形成自我對準 接觸窗結構的方法之流程圖。 圖式元件符號說明 2 基板 4 第一導電層 6 第二導電層 8 絕緣層 10 侧壁間隔層 12 介電層 14 金屬層 16 點 20 自我對準接觸窗 22 光阻材料層 發明詳述 本發明之第一實施例係由圖3A至圖3F所示之結構以及 圖4A至圖4B流程圖所示之方法所表示。 首先準備一基板2，其上依序形成一第一導電層4、一第 二導電層6以及一絕緣層8。第一導電材料層4可為多晶 石夕（polysilicon)或非晶石夕（amorphous silicon)層，第二導電材料 層6可為金屬矽化物層，如矽化鎢（WSi)，絕緣層可為氮化 矽（SiN)層。接著，如圖4A所示，打開閘極導體（gate conductor, GC)遮罩（步騾401);接著實行蝕刻製程蝕刻至基 板表面以形成複數個閘極結構（步驟402)。 接著，如圖3A及圖4A所示，在整個該基板上沈積一光 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 544787 A7 B7 五、發明説明（8 P材料層2或先沈積一抗反射層（anti-reflective coating， ARC)(圖中未不出）後再沈積一光阻材料層22(步驟4⑽）。 接著’如圖3B及圖4A、4B所示，使用位元線接觸節點 遮罩（bit-line contact n〇de mask)以遮罩各個閘極結構無位元 線之側（步驟404);接著使用微影或微影及蝕刻製程以在閘 極結構欲形成位元線之細彡成開口直至暴露&基板表面（步 驟405)，該蝕刻製程可為乾式蝕刻；接著使用一種對第二 導電層6之蝕刻率高於對絕緣層8之蝕刻率的蝕刻 劑（例如 ΝΗ4〇Η，Η2〇2和％〇混和的蝕刻劑）以蝕刻第二導電層6未 被光阻材料層22遮罩之側（步驟4〇6)，該蝕刻可為等向性 (isotropic)蝕刻。 接著，如圖3C及圖4β所示，移除光阻材料層22以及抗 反射層（如果有的話）（步驟407)。 接著，如圖3D及圖4Β所示，在各個自我對準接觸窗結 構的側壁上形成一側壁間隔層1〇 (步驟4〇8)。該側壁間隔 層10可為氮化矽（SiN)層。 接著，如圖3E及圖4B所示，在整個該基板的上表面形 成一介電層（步騾409) ’·然後藉微影及蝕刻以移除該介電層 位於欲形成位元線接觸之部分以暴露出基板表面而形成自 我對準接觸窗（步驟410)。 接著’如圖3F及圖4B所示，接著在整個該基板的上表 面沈積一特定厚度的金屬層14,以覆蓋介電層12之暴露表 面、自我對準接觸窗結構之側壁間隔層1〇以及基板2。藉 此在自我對準接觸窗2〇中，以便於金屬層14及基板2之間 I .… , — 本紙痕尺度適用中國®豕標準(CNS) A4規格(210><297公^0 ~ " 一 544787 五、發明説明（ 形成一金屬接觸（步驟411)。 本發明之第二實施例係由圖5A至圖5F所示之結構以及 圖6A至圖6B流程圖所示之方法所表示。 =先準備一基板2，其上依序為一第一導電層4、一第二 導電層6以及—絕緣層8，第-導電材料層4可為多晶碎 (polysilicon)或非晶矽（&111〇1>沖〇則311。⑽)層，第二導電材料層 6可為金屬矽化物層，如矽化鎢(WSi)，而絕緣層可為氮化 (.)層，接著，如圖6 A所示，打開閘極導體（Gc)遮罩 (步I 601)，接著蝕刻至基板表面以形成複數個閘極結構 (步驟602)。 接著，如圖5A及圖6A所示，在整個該基板上沈積一光 阻材料層22，或先沈積一抗反射層（anti-reflective coating， ARC)(圖中未示出）後再沈積一光阻材料層22(步驟6〇3)， 而飾刻製程可為乾式蝕刻。 .接著，如圖5B及圖6A所示，以位元線接觸窗光罩卬小 ontact mask)使用微影或微影及蝕刻製程以在閘極結構 巧^成圓开y開口（步驟6〇4)。該等圓形開口的位置即為之後 自我對準接觸t之區域，請參考圖5g所示。祕刻製程可 2式㈣；接著使用—種對第二導電層6之蚀刻率高於 :絕緣層8之蚀刻率的餘刻劑（例如Νη4〇η，η处和邮混 勺蝕刻训）蝕刻第二導電層6未被光阻材料層22遮罩之 側（步驟6〇5)，該蝕刻可為等向性（isotropic)蝕刻。 接著，如圖5C及圖6B所示，移除光阻材料層22及抗反 射層（如果有的話）（步驟6〇6)。 -12- 本紙張尺 鮮 接著，如圖5D及圖 構的側壁上形成—側壁/，，各個自我對準接觸窗結 10可為氮切（SiN)層。M10(步驟607)，該側壁間隔層 成(圖步=及圖6B所示，在整個該基板的上表面形 層位於欲形成位元線接觸影及㈣製程移除該介電 成自我對準接觸窗（”1=分，以暴露出基板表面而形 接著，如圖5F及圖6B Μ 一 面沈積-特定厚度的全屬/^，接著在整個該基板的上表 面、自我對準接觸宵^ 以覆蓋介電層12之暴露表 ..,. 囱〜構之側壁間隔層10以及基板2。藉 準接觸窗2〇中於金屬層14及基板2之間形成-巫屬接觸（步驟610)。 〜
可：二:示為圖5F中第二導電層之俯視圖，由圖％中亦 了看到步驟6〇4中圓形開口之位置。 TT 之藝Ϊ國專利第5,989,987號案形成自我對準接觸 導雨展、、5〈在於本發明之方法對各個閘極導體之第二 的日虫^步驟僅針對各個閘極結構欲形成位元線接觸 的一側進行蝕刻，第二導泰 妖賙 -側未被I虫刻… 未用於形成位元線接觸的另 成自我對進3、、 ^ ，根據本發明所提供之方法可解決形 第5 989c! 結構之傳統方法以及先前技藝美國專利 ί，ΓΓ7號案形成自我對準接觸窗結構之方法之所有缺 605 It η 406 ^ ^ ^ ^ ^ ^ ^ 傳續、 、私㈢又蝕刻與形成自我對準接觸窗結構之 死万法比較可造成較大之接觸窗口而避免第二導電層6 544787 A7
在點16處與金屬層14接觸；(2)蝕刻第二導電層6僅蝕列 各個閘極結構欲形成位元線制的—側，對於*會造成閑 極導體/、位，線接觸窗短路的區域，第二導電層6不會被蝕 刻’由於第一導電| 6僅一侧截面積變小，因此閘極導體 之電阻值變化較小；_刻時第二導電層6與第—導電^ 4之接觸面積減少較小’因此在後續製程比較不會造成： 離現象。 本發明之特點及技術内容已充分揭示如上，任何熟習本 項技藝之人可依據本發明之揭示及教示而作各種不背離本 發明精神之替換或修飾。因此，本發明之保護範圍不應僅 限於所揭示之實施例，而應涵蓋這些替換及修飾。 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
Claims (1)
- 544787 申請專利範圍 l -種形成具有局部蝕刻導電層之閘極結構之 下列步驟·· 不决，包招 (1) 準備-料Μ基板，其切基板上 ==其::個_構包括形成』= 導私層，形成於該第一導電層上的— 電層以及形成於該第二導電層上的一絕緣層； 一 (2) 使用-光罩在該基板上形成至少含有—開 份閘極結構直至基板表面之一覆蓋I ; +各邵 —Γ==Γ層之㈣率心對該絕緣層及該第 該第電層率的—物㈣刻該暴露間極結構之 ⑷移除該覆蓋層；以及 (5)在各個閘極結構的侧壁上形成—側壁間隔層. 申請㈣第1项之《«局㈣料\層之閉 括下列步驟··在步驟（2)中形成該覆蓋層之方法包 (1)在孩基板上沈積一光阻材料層；以及 ⑼進行一微影製程。 申叫專利Id圍帛1项〈形成具有局部㈣導電層之閘 虽結構《万法，其中在步驟⑺中形成該覆 蓋層之方法包 括下列步驟： ⑻在居基板上沈和一杬反射層及一光阻材料層；以及 (b)進行一微影及蝕刻製程。 4.如申請專利麵1项之形成具有伽刻導電層之間 -15- 本紙張尺度適财® ®家鮮(CNS) A4規格(210 x 297公釐）544787 A8 B8極結構之方法， 罩。 其中在步驟（2)中該光罩為位元線節點光 5 ·如申請專利範圍第 極結構之方法，其 光罩。 1項《形成具有局部蝕刻I電層之閘 中在步驟(2)中該光罩為位元線接觸窗 6. 如申請專利範園 核結構之方法， 砂之一 〇 第1項（形成具有局部姓刻導電層之間 其中該第-導電層係選自多晶㈣非晶 7^申請專利_第丨項之形成具有局部㈣導電層之1 〇 ^ ^ , ^甲巧罘一導私層係為金屬矽化物層。 •如申請專利範圍第1瑁之诸 極-構之方、去L: 邵蚀刻導電層之1 、、Ά万法’其中步驟(3)之蝕刻係為等向性蝕刻。 • 0申晴專利範圍第1項之形成具有局部㈣導電層之 我對準接觸窗結構之方法 万汝具中步驟（3)之蝕刻劑係， H 4 ο Η ’ Η 2 〇 2 和 Η 2 0 混和物。 ι種形成具有局部·導電層之自我料接觸窗結構: 万法，包括下列步驟： 八一個半導體基板，其中該基板上形成有複數個 結構’其中各個間極結構包括形成於該基板 上的-第-導電層’形成於該第一導電層上的一第 電層以及形成於該第二導電層上的—絕緣層； (2)使用位元線節點 之側形成至少含有— 面之一覆蓋層； 光罩在各個閘極結構欲形成位元線 開口暴露邵份閘極結構直至基板表 -16 -裝 ()使用對第一導電層之姓刻率高於對該絕緣層及該第 、導電層义钱刻率的一蝕刻劑以蝕刻該暴露閘極結構用 於形成位凡線接觸之側之該第二導電層； ⑷移除該覆蓋層； (5)在各個閘極結構的側壁上形成一側壁間隔層； ⑹形成覆蓋整個該基板之一介電層； 人⑺使用微影及蝕刻製程以移除在各個閘極結構之間用 於形成位元線接觸之側之介電層直至基板之表面被暴露 出，藉此形成自我對準接觸窗；以及 ⑻形成覆蓋介電層的被蝕刻掉之表面及閘極結構之侧 f間隔層的—金屬層，並在該金屬層和該基板之間被暴 露出之基板表面上形成自我對準接觸。 u·如申請專利範圍帛1G項之形成具有局部㈣導電層之 自‘我對準接觸窗結構之方法，其中在步驟⑺中形成該覆 盖層之方法包括下列步驟： (1)在該基板上沈積一光阻材料層；以及 (ii)進行一微影製程。 12·如申請專利帛Π)項之形成具有局部触刻導電層之 f我對準接觸窗結構之方法，其中在步驟⑺中形成該覆 盖層之方法包括下列步驟： (a) 在該基板上沈積-抗反射層及一光阻材料層；以及 (b) 進行一微影及蝕刻製程。 如申請專利範圍帛1G項之形成具有局部蚀刻導電層之 自我對準接觸窗結構之方法，其中該第—導電層係選自 -17- 544787夕晶矽與非晶碎之一。 14. =專利刪！"之形成具有局部 屬砂化物層。 …弟-導電層係為金 15. ::請專利謂14项之形成具有局部蚀刻導電層之 矽化鵁層。 丨中孩金屬碎化物層係為 16:1請專利範圍帛10項之形成具有局部蝕刻導電層之 層。、對準接觸窗結構之方法’其中該絕緣層係為氮切 ΐ7·=申請專利範圍帛1G項之形成具有局部㈣導電層之 化^準接觸窗結構乏方法，其中該側壁間隔層係為氮 軏圍第喻形成具有局部蝕刻導電層之自 性I虫刻妾觸冒結構之方飞，其中步驟（3)之蚀刻係為等向 19. 如申μ專利㈣帛i Q項之形成具有局部㈣導電層之 ^我=準接觸窗結構之方法，其中步驟⑺之㈣劑係為 4〇H ’ H202和h2〇混和物。 20. Γ種形成具有局部㈣導電層之自我料接觸窗結構之 方法，包括下列步驟： 八⑴準備_個半導體基板，其中該基板上形成有複數個 刀離的閘極結構’其中各個閘極結構包括形成於該基板 上的一第一導電層，形成於該第一導電層上的一第二導 -18- 544787 圍範 利 專請 中 A BCD 電層以及形成於該第二導電層上的一絕緣層； () 元、、泉接觸窗光罩以在閘極結構間形成至少A 有一圓形開口暴露部份問極結構直至基板表面之一= 層此開口為之後自我對準接觸窗之區域； —對第二導電層之触刻率高於對該絕緣層及該, ,蝕刻率的一蝕刻劑以蝕刻該暴 孩第二導電層； ^再2 (4) 移除該覆蓋層； (5) 在各個閘極結構的側壁上形成-側壁間隔層； ⑹形成覆蓋整個該基板之一介電層； ⑺藉微影及姓刻製赶々 ^ ^ λ- - ^ 移除在各個閘極結構之間用 :泉接觸之側之介電層直至基板之表面被暴霉 出以形成自我對準接觸窗；以及 ⑯被暴蹈 ⑻形成覆盍介電層的被蝕刻掉之表面及閘極 壁間隔層的一金屬芦，允产、、入π W m + > 屬層並在孩金屬層和該基板之間被暴 路出之基板表面形成自我對準接觸。 2“二請專利範圍第2〇項之形成具有局部蚀刻導電層之 蓋層之方法包括下列^法，其中在步驟⑺中形成該覆 (1)在孩基板上沈積一光阻材料層；以及 ⑻進行一微影製程。 H請㈣範„ 2(^之形成具有局部㈣導電層之 蓄展對準2二結構之方法，其中在步驟（2)中形成該覆 盍層 < 万法包括下列步騾：-19-(a) 在該基板上沈積一抗反射層及一光阻材料層；以及 (b) 進行一微影及蝕刻製程。 曰 23·:申請專利卿20項之形成具有局部蚀刻導電層之 對準接觸窗結構之方法’其中該第—導電層係選自 夕晶矽與非晶矽之一。 24·如申請專利_ 20項之形成具有局部姓刻導電層之 ^我對準接觸窗結構之方法，其中該第二導電層係:金 屬矽化物層。 25. 如申請專利範圍第24項之形成具有局部蝕刻導電層之 自我對準接觸窗結構之方法，其中該金屬矽化物層係為 矽化鎢層。 ㈢，、 26. 如申請專利範圍第2〇項之形成具有局部蝕刻導電層之 自我對準接觸窗結構之方法，其中該絕緣層係為氮^ 層0 27·如申請專利範圍第2〇項之形成具有局部蝕刻導電層之自 我對準接觸窗結構之方法，其中該側壁間隔層係為氮化 矽層。 28. 如申請專利範圍第20項之形成具有局部蝕刻導電層之自 我對準接觸窗結構之方法，其中步騾（3 )之蝕刻係為等向 性蝕刻。 29. 如申請專利範圍第2 0項之形成具有局部蝕刻導電層之自 我對準接觸窗結構之方法，其中步驟（3 )之蝕刻劑係為 NH4〇H，H2〇2 和 H20 混和物。 -20- 本紙張尺度適用巾關家標準(CNS)八4規格_ X 297公董)' ----------
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| KR0136569B1 (ko) * | 1992-10-24 | 1998-04-29 | 김주용 | 고집적 반도체 소자의 콘택홀 형성 방법 |
| KR950011983B1 (ko) * | 1992-11-23 | 1995-10-13 | 삼성전자주식회사 | 반도체 장치의 제조방법 |
| JP3572850B2 (ja) * | 1997-02-12 | 2004-10-06 | ヤマハ株式会社 | 半導体装置の製法 |
| TW365697B (en) * | 1997-11-14 | 1999-08-01 | United Microelectronics Corp | Etching method of improving of self-aligned contact |
| US6448140B1 (en) * | 1999-02-08 | 2002-09-10 | Taiwan Semiconductor Manufacturing Company | Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess |
| KR100297738B1 (ko) * | 1999-10-07 | 2001-11-02 | 윤종용 | 챔퍼가 형성된 금속 실리사이드층을 갖춘 반도체소자의 제조방법 |
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| JP3449998B2 (ja) * | 2000-10-05 | 2003-09-22 | 沖電気工業株式会社 | 半導体装置におけるコンタクトホールの形成方法 |
| JP2004228405A (ja) * | 2003-01-24 | 2004-08-12 | Renesas Technology Corp | 半導体装置の製造方法 |
| JP2004289046A (ja) * | 2003-03-25 | 2004-10-14 | Renesas Technology Corp | キャパシタを有する半導体装置の製造方法 |
| US7005744B2 (en) * | 2003-09-22 | 2006-02-28 | International Business Machines Corporation | Conductor line stack having a top portion of a second layer that is smaller than the bottom portion |
-
2002
- 2002-09-18 TW TW091121343A patent/TW544787B/zh not_active IP Right Cessation
- 2002-12-27 US US10/330,522 patent/US6855610B2/en not_active Expired - Lifetime
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2005
- 2005-01-21 US US11/041,503 patent/US20050127453A1/en not_active Abandoned
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|---|---|
| US20040051183A1 (en) | 2004-03-18 |
| US6855610B2 (en) | 2005-02-15 |
| US20050127453A1 (en) | 2005-06-16 |
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