TW541538B - Independent asynchronous boot block for synchronous non-volatile memory devices - Google Patents

Abstract

A non-volatile memory device having a main memory that operates synchronously with the system clock and an asynchronous boot block. The boot block can be activated to operate asynchronously upon initial power up or can be switched from synchronous to asynchronous mode upon receipt of a command signal by control logic circuitry within the device.

Description

541538 V. Description of the invention (1) The technology in the present invention relates to an independent non-background immutable memory device, which includes flash memory (EEPROM) in its own device. The memory is asynchronous and the array reads the data from the array. Immutable device domain, used to store the system (BIOS), etc. The same way as the physical memory array, the disadvantage is that it requires signals and reads data, without having to set it will need to be relative to the operation. In the field of immutable semiconductor memory devices, in particular, a synchronous invariant memory device of a synchronous start block. The body device includes various semiconductor memory devices, and its data is maintained when the power is turned off. + Memory and electrical erasable programmable read-only memory of denatured memory devices and various other device configurations. In general, this type of note may be operated synchronously with a system clock of the device in order to record data and program / write data to the memory array. Often, it includes a special program. Access order. It is suitable to set the clock or memory to start the area such as the operation here. Therefore, the clock comes from the positive block of the read start setting, which is used as the system, and the temple start area is synchronized. The synchronization is ordered immediately after the start of the block. To do this, synchronize the main memory with the basic input block to store the device. Before moving the data, it must be activated to one of the dedicated memory areas. The input / output system will take the rest of the memory and use it to access the data. ‘Required clock Block access funding Start block Partially asynchronous US Patent No. 5,197,034 granted to Fandrich et al., Debunks — invariant memory, including a main block and — start block. The circuit device uses the coupling to receive a control signal as a control input for the control signal.

541538 V. Description of the invention (2) It is in the first voltage state, it is in another voltage state, it is the actual shutdown state. The beauty of Akaogi is granted to the invariant semiconductor memory or the normal flash memory, a first erasing unit, 1 to allow the startup block to be updated, and to generate a shutdown signal on the control signal day to switch the memory to the specified body. The unit array is divided into units. Therefore, the moving block quickly grants Le step access memory overlapping memory. This allows the startup routine to select the chip. The present invention synchronizes the access step invariance. The operation erase operation of an operation module of the present invention 'changes the beauty of flash memory and others. The memory access of the cube is selected by the slower startup unit, and it is still the national patent 5, memory device. For a second wipe, only. In the regulations, and start the operation mode list with the normal type national patent 5, law, which is bad, from a bit of memory. A part of the activation unit is considered to be a regular sync device after the device is initially turned on. Another object is to provide, which allows memorizing gymnastics No. 402, 3, 8 and 3, to disclose an electrically erasable, for selective use in the activation block type. The device has an array of memory cells, a division unit, and an operation. Specify the unit. When a first erasing unit implements the second erasing memory operation mode, the first erasing second erasing unit is suspended to implement the specified value of the erasing operation, so as to implement the change between enabling the flash memory. No. 5 02, 8 3 No. 5 'describes a method for the same integrated circuit microprocessor to read data through an early external memory device for efficient access. The circuit includes a storage site in Figure 13 of the patent of Le et al., And appears to be synchronized. One type has a startup block that can be programmed / erased non-operationally. The same type of synchronous invariant memory device allows the asynchronous start-up block to be active, or to allow self-synchronous operation to switch when commanded. _____

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541538 V. Description of the invention (3) Change to start asynchronously starting blocks Overview of the invention Many of the above purposes are achieved by a memory block and an independent asynchronous. At the initial start-up, and for the system configuration of the 5 memory controller. Synchronous invariable memory device package Allows asynchronous boot blocks to be started after synchronization. Synchronous mode is started, and then data is read from the boot block and command signals are issued. fThe best way of applying the present invention Please refer to FIG. 1. The random synchronization invariant memory block 2 3 of the present invention. A block of the memory circuit of the regular synchronous invariable memory area, which can include read, program, and erase line test amplifiers, and output buffer pins 21 and output pins 27 for the device 20 and output commands from it . The signal is transmitted between the asynchronous start block 25 and 32 to be inverted before being input to the asynchronous start block 3 5. An invariable memory device having a main boot block that operates in synchronization with the system clock. When the microprocessor / device operation of the device is used, this device can be used to construct a control logic circuit, which can be active at the beginning, or can be allowed. The boot block then switches to asynchronous mode. This allows without having to wait for the prescribed clock or read the volatile memory device 20, which is composed of a positive and an asynchronous start block 25 and the asynchronous start block 25 are both address inputs, X and y decoder, alternative, invariant memory array, sense. The memory device 20 includes a plurality of round-in commands and output commands to the memory number lines 31 and 33 in the main memory block 23-round commands. A start block start signal block 2 5 and input it into the regular master memory. Please sign as shown in Figure 2 ’asynchronous start block 25 receives a signal 41 to block 49

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y ^ ^ Divide and select 42, to confirm that the memory area 43 will be selected: ":,) for reading 'programming' and erasing operations. Start block 25 also ^ Tongue 1 'Bay 1 amplifier 45 and use The non-synchronized start block 25 is started by the output buffer 46 of the buffered output signal 50.-One way is to send and store temporary set of benefits "(11 Mode Register Set ") command, J: ff synchronous memory Command to start the asynchronous start block, and synchronize the invariant memory block. In this case, the mode operation is for programming and erasing, and the asynchronous mode = design and erasure can be saved. Take the asynchronous start_ instead of the regular master: yourself: η. = The second way of the asynchronous start block is to start the device at the device J ΐ?! Ν The startup block is active instead of the ghost of the synchronous invariant memory area. At times such as when you want to start a synchronized main memory block, you can send a command 1 to interrupt the asynchronous start block. The mode temporary port 7 is being suspended as a synchronous chip operation. Enter this command in operation mode, so some input pins cannot be aborted Herein, such as clock, row access (# 1 ^ 3), and the row access (CAS #) and the like, but may be set to a non-active state in the respective VIL or VIH at the inputs until it is used for input commands. In this way, although the chip is operating in the asynchronous start block mode, a synchronous command sequence for programming and erasing can still be issued and function. This can save a lot of time from designing a set of asynchronous logic for programming and erasing the asynchronous boot block.

541538

V. Description of the invention (5) Please use Cang Zhao 3 and 4 to show examples of control logic circuits used to start and stop the asynchronous start block. The circuit of FIG. 3 is an x-decoder in an asynchronous start block, and the circuit of FIG. 4 is an x-decoder in a synchronous main memory block. Referring to Fig. 3, the X-decoder logic circuit 60 includes a NAND (,, and) gate 65 'having a plurality of input terminals 61, 69 for receiving input signals A0-An. One of the input terminals 67 receives a BOOT —BLOCK —ENABLE signal. The output of the NAND gate 65 is inverted by an inverter 66 to generate an output signal 0 U T at an output terminal 68. Also in Fig. 4, a N A N D gate 7 5 receives many input signals AO -An. Input terminals 71, 79 include one of the input terminals.

BOOT_BLOCK_ENABLE signal. However, BOOT-BLOCK-ENABLE signals

Invert 72 before input to NAND gate 75. The output of NAND gate 75 is inverted by inverter 76 to produce an output 78. The "mode register set" command can be used to make the BOOT_BLOCK-ENABLE signal active or logic high, or it can be set to logic high after power-on to indicate the start of the asynchronous start block. If the asynchronous start block is not started The BOOT_BLOCK_ENABLEE signal will be in a logic low state. In Figure 3, only the BOOT_BLOCK_ENABLEE signal is in a logic high state, the output signal OUT will follow the logical combination of input A0 to input An. Otherwise, As long as the BOOT_BLOCK_ENABLE signal stays at a logic low state indicating that the asynchronous start block is not activated, the output will remain at a logic low state. Please refer to Figure 4 'X in the synchronous main memory block — decoder circuit area In block 70, if the BOOT_BLOCK —ENABLE signal is in a logic low state, the output signal OUT at terminal 78 will follow the logical combination of the input signal A0 to the turn-in signal An. This indicates that the asynchronous start block is not started, and it starts. Formally synchronize main memory blocks.

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Please refer to Fig. 5 for a diagram of the turn-out buffer circuit of the startup block and the main memory block. The output buffer control logic circuit 8 of the asynchronous start block is merged with the output buffer control logic circuit 90 of the synchronous main memory block, because the output of each buffer is 88, 98 at the output pin 1 0. Provide an output signal. The first logic block 80 is an output buffer of the asynchronous start block, which is composed of a first inverter 83 that receives a BOOT-BLOCK-ENABLE signal at the input terminal 87, and outputs at the inverter 83 The terminal 100m generates an intermediate control signal. A NOR ("NOR") gate 84 has a first input terminal, which is coupled to an output terminal whose phase is inverted to 83, and receives an intermediate control signal at the first input terminal hi. The NOR gate 84 receives the first input k number at a second input terminal 110. N 0 R gate 8 4 generates a first gate signal at N 0 R gate output 105.

A NAND gate 82 receives β〇〇τ —bl〇CK__ENABLE at a first input terminal 108.

A serial number 'and receives an input signal 81 at a second input terminal 81. A second gate signal is generated at the output 103 of the gate 82. The two gate signals are supplied to a gate of a CMOS (metal oxide semiconductor) inverter composed of a PMOS transistor 85 and an NMOS transistor 86. The PM0S transistor 85 receives the gate signal of the output 103 from the NAND gate 82, and the NMOS transistor 86 receives the gate signal of the output 105 from the NOR gate 84. The inverting line formed by the PM0S85 and the NMOS transistor 86 generates an output signal at the node 88, which is sent to the output pin 1 0 0. The control logic circuit g of the invariant memory device block includes an inverter 93 'which receives b00t__BLOCK_ENABLE k 3 tiger' at a first input terminal 97 and generates an intermediate control at its output terminal 1 q 2 signal. A N A N D gate 92 has a first input terminal 112 coupled to the output terminal of the first inverter 93

C: \ 2D-CODE \ 91-03 \ 90132547.ptd 541538 V. Description of the invention (7) Sub 1 0 2 and receive the intermediate control signal 1 0 2 and also receive the first input signal at a second input terminal 91 . The NAND gate generates a first gate signal at the NAND output 104. A NOR gate 94 receives a BOOT_BLOCK_ENABLE signal at a first input terminal 97, and receives an input signal at a second input terminal 91. The N 0 R gate 9 4 generates a second gate signal at its output 106. The first idle signal goes to the gate terminal of a PMOS transistor 95, and the second go signal goes to the gate terminal of a NMOS transistor 96. The PM0S transistor 95 and the NMOS transistor 96 form an inverter which generates an output at the node 98 which proceeds to the output pin 100. The above description input terminals 87 and 97 directly receive BOOT_BLOK_ENABLE: such as L number. Or, the input terminals 87 and 97 can also receive signals, which are the result of the logical combination of the BOOT — BLOCK —ENABLE signal and other logic control signals. When starting the asynchronous start block, BOOT_BL〇CK — the ENABLE signal will be at logic high, and will allow the input signal to control the logic circuit, so that the logic circuit will be closed when the BOOT_BLOCK_ENABLE signal is at logic high The output 100 is driven at the same time as 90, so the output buffer and the main memory block are suspended. When the asynchronous start block is not started, the b00t_block — ENABLE signal will be at a logic low value, so the output buffer of the asynchronous start block 80 will be suspended, and it will start to the synchronous master. Low signal in the output buffer of the memory block. Therefore, even if both output buffers drive the other output pads 100, only one output buffer will be allowed to drive the chip at any one time and the other buffer will be in a tri-state mode. This allows starting and aborting asynchronous start blocks even after the sync memory block has been operated.

C: \ 2D-CODE \ 91-03 \ 90132547.ptd Page 10 541538 Anti-invention description (8) Description of component number 20 Invariant memory device 21 Input pin 23 Regular synchronization invariant memory block 25 Asynchronous Start block number 27 Output pin 31 Signal line 32 Start block start signal 33 Signal line 35 Invert 41 Signal 42 Programming / erase selection 43 Memory area 44 Line selection 45 Sense amplifier 46 Test mode output buffer 4 7 X-decoder 48 y-decoder 49 block 50 output signal 60 X-decoder logic circuit 61 input terminal 65 NAND (', inverse and 丨,) gate 66 inverter ❿

C: \ 2D-CODE \ 91-03 \ 90132547.ptd Page 11 541538 V. Description of the invention (9) 67 Input terminal 68 Output terminal 69 Input terminal 70 X-decoder circuit block 71 Input terminal 72 Inverted 75 NAND Gate 76 Inverter 77 Input terminal 78 Output 79 Input terminal 80 Output buffer control logic circuit 81 Second input terminal 82 NAND Gate 83 First inverter 84 NOR (π or not) Gate 85 PMOS transistor 86 NMOS Crystal 87 Input terminal 88 Out of buffer 90 Output buffer control logic 91 Second fm input terminal 92 NAND gate 93 First inverter < 1

C: \ 2D-CODE \ 91-03 \ 90132547.ptd Page 12 541538 V. Explanation of the invention (ίο) 94 _Gate 95 PMOS transistor 96 NMOS transistor 97 input terminal 98 buffer output node 100 output pin 101 output Terminal 102 Output terminal 103 iA. ILi 104 NAND output 105 NOR gate output 106 Output 108 First input terminal 110 Second input terminal 111 First input terminal 112 First input terminal < 1

C: \ 2D-CODE \ 91-03 \ 90132547.ptd Page 13 541538 Brief Description of Drawings Figure 1 is a block diagram of a synchronous invariant memory device of the present invention. Figure 2 is a block diagram of an asynchronous boot block. Figure 3 is a circuit diagram of an X-decoder circuit block in the asynchronous start block. FIG. 4 is a circuit diagram of an X-decoder circuit in a main memory block. Figure 5 is a circuit diagram of the output buffer of the boot block and the main memory block

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Claims (1)

541538 1 · A kind of invariable memory, including: a memory array, including a synchronized main memory block and a moving block; v enable many controls and include 2. for moving and middle to one coupling 3. Block, and the first one indication 4. Such as the logic of the decoder 5 · If the pin is connected to the block input pin and many output pins, it is coupled to the memory array; The logic circuit is used to receive the address signal and the asynchronous control signal , A synchronous control signal of a clock signal; and a device for starting and interrupting the asynchronous starting block. Declaring the invariable memory of item 1 of the patent scope, wherein the device for starting and breaking the asynchronous starting block includes applying a first control signal $ to the first input pin of the control logic circuit, and the control logic 4 = means = start Or interrupt the output of the asynchronous start block. The first invariable memory of the patent scope of the application, wherein the control logic is included in the first X-decoder circuit area of the asynchronous start block, and the second χ-decoder circuit area of the synchronous main memory block. Block, the if decoder receives a first control signal, and each provides & the output of a respective asynchronous or synchronous block. a. 2 :: The output of the invariable memory block in the third item of the patent scope is the state of the first x-salmon Cheng Yiguang ^. The rotation of the first block of the decoder block is the opposite of the application of the patent application scope item 丨 does not receive the start signal or mode in two :, which in the input. 、 When it is temporarily stored as set h, start asynchronously. • I 6 · If the application mode of the 5th pin of Shen Qing's patent scope is temporarily stored, crying memory and sexual memory are temporarily stored. Asynchronous start block, and 541538 6. Scope of patent application Start synchronous main memory block. 7. For example, the invariable memory in the scope of the patent application, wherein the control logic includes a first logic block in a synchronized main memory block in an output buffer, and a non-synchronized start block. In a second logic block of an output buffer, the first and second logic blocks receive a first control signal and a first input signal, and generate an output at one of the output pins. 8. As in the invariable memory of item 7 of the scope of patent application, each of the first logic blocks includes: a first inverter that receives a first control signal at an input terminal and generates an intermediate control at an output terminal Signal; Φ a NAND gate, a first input terminal is connected to the output terminal of the first inverter, and an intermediate control signal is received at the first input terminal, and the NAND gate receives the first input signal at a second input terminal And generates a first gate signal at a NAND output; a NOR gate receives a first control signal at a first input, receives a first input signal at a second input, and generates a second gate at a NOR output Signal; and a CMOS inverter including a PM0S transistor, a gate coupled to the NAND output, a drain coupled to a voltage supply source, and a source coupled to one of the output pins, and a NMOS transistor The crystal has a gate coupled to the NOR output, a drain coupled to one of the output pins, and a source connected to a ground potential. The gate of the PMOS transistor receives the first gate signal, and the NMOS transistor The second gate receiving gate signal, the output generating one of those output pin. C: \ 2D-C0DE \ 91-03 \ 90132547.ptd Page 16 541538 VI. Application for patent scope 9 · Rushen's patent scope for 7 items of invariable memory, where each logical block includes: The phase inverter receives a first control signal at an input terminal and generates an intermediate control signal at an output terminal. The NOR, gate has a first input terminal coupled to the wheel output terminal of the first inverter, and An input terminal receives an intermediate control signal, the NOR gate receives a first input signal at a second terminal, and generates a first gate signal at a NOR output; a NAND gate receives a first at a first input Control signal and receiving a first input signal at a second input and generating a second gate signal at the NAND output; and CMOS inversion ☆ 'Includes a pmos transistor with a gate coupled to the NAND output' To a voltage supply source, and a source coupled to one of the output pins, and an NM transistor, a gate coupled to the output, a drain coupled to one of the output pins, and a The source is connected to a ground potential The gate of the PM0S transistor receives the first gate signal and the transistor of the NMOS transistor receives the second gate signal, and the output is generated at one of the output pins. I 〇 The invariable memory according to item 1 of the patent application, wherein the memory array is a flash memory type. II. The invariable memory of item 1 of the patent application scope, wherein the asynchronous boot block includes: a multi-address buffer, each having an input for receiving a boot block input signal ’and each generating a bit signal; 541538 6. The scope of patent application is generated; the decoder's each receive the address signal ... and produce # ^ ^ ^ ^ face array, which is electrically coupled to the X-decoder and y_ decoder, f select electricity ^ out 2 degenerate memory also Self-programming / erasing ^ When the remote receiver ^ is selected, and provides the memory output signal to a row selection circuit, and :: sense amplifier, power consumption to the row selection circuit, and many output buffers: " From Makou to a noon, multiple sense amplifiers, sense amplifiers, and output buffers receive the memory output signal and generate a startup block output signal. 1 2 · Invariant memory in the scope of patent claim 丨 1, The asynchronous startup block is operated separately from the synchronized main memory block. 1 3 ·-a kind of invariable memory, which includes:: $ memory array, including a synchronized main memory block and an asynchronous start block ' The startup block operates separately from the main memory block; many input pins and many output pins are coupled to the memory array; control logic circuit 7. Receives address signals, asynchronous control signals, and synchronization including a clock signal Control signal, the control logic circuit includes a first X-decoder circuit block in an asynchronous start region, and a second χ-decoder circuit block in a synchronous main memory block, the first and The second X-decoder circuit block receives a first control signal and each provides an output for instructing activation of a respective asynchronous or synchronous block; and a device for starting and interrupting the asynchronous starting block. 1 4 · For example, the invariable memory of item i 3 of the patent application scope, wherein the device for starting and interrupting the asynchronous starting block includes applying a first control signal C: \ 2D-CODE \ 91-03 \ 90132547.ptd Page 18 No. to a coupling to the control circuit provides an instruction to start or: 2 first input pins, control logic 15. Such as the application for a patent / off the asynchronous start block output. X-decoder block wheel 1 ^. 13 items of invariant memory, where the first is the opposite of the logical state. "、 One and the output of the second x-decoder block are lb • If the patent application input pin receives the invariant memory of the boot letter / item, which is in the start block of the input. K〆board register set When the signal is activated, the start asynchronous input pin is connected to the 0 ± invariable / memory. Among them, the auxiliary and start synchronization are synchronized. It: ;; interrupt the asynchronous start block logic and power. , S # π & the main memory block in Liaobu is an output buffer block, and the asynchronous start block is in the second block of the output buffer, the first and second logical blocks Connect a first control signal, one input signal and one output on one of the output pins. Page 9 19. As in the invariable memory of item 8 of the patent application scope, each of the first logic blocks includes: a first inverter, which receives a first control signal at an input terminal, and generates a Intermediate control signal; a N AND gate having a first input terminal coupled to the output terminal of the first inverter 'and receiving the intermediate control signal at the first input terminal, and the ^^ ⑽ gate receiving the first input terminal at the second input terminal An input signal, and a first gate signal is generated at the _NAND output; C: \ 2D-C0DE \ 91-03 \ 90132547.ptd 541538 C: \ 2D-CODE \ 91-03 \ 90132547.ptd Page 20 541538 6. Patent application scope: a drain is coupled to one of these output pins, and a source is connected to a ground potential. The PMOS transistor The gate receives the first gate signal, and the gate of the NMOS transistor receives the second gate signal, and generates the output at one of the output pins. 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