JP2003178591A - Memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory system in which a plurality of nonvolatile semiconductor memories are connected and which can be controlled as if it is one memory, and in which memory capacity is increased. <P>SOLUTION: In a memory system having a plurality of the nonvolatile semiconductor memories, each of nonvolatile semiconductor memories has a plurality of memory cells arranged almost in a matrix state, transfers data arranged in a selected row out of the memory cells in parallel to a plurality of data registers, outputs data in the data registers serially to the outside, successively repeats this operation and can perform page read-out. This device has an address input means, an input/output terminal, and an address control means, addresses comprise column addresses and row addresses, this column address is incremented in accordance with a read-out clock signal, and when the column address reaches the last column address in a page, the row address is incremented. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly to a memory system capable of reading and writing in page units.

[0002]

2. Description of the Related Art Recent EEPROM (Electrically Era)
sable & Programmable Read Only Memory), especially NAN
The D-type EEPROM is configured so that reading and writing can be performed in page units (256 bits to several K bits) in consideration of the fact that the current flowing in the memory cell is small during writing and erasing. As this NAND type non-volatile semiconductor memory, one having a storage capacity of 4 Mbits has already been put into practical use (1989-ISS).
CC An Experimental 4Mb EEROM with a NAND Structu
red Cell).

FIG. 22A shows a structure of two NAND bundles in which eight memory cells MC each having a floating gate structure are connected between a bit line and a source, which are selected at the time of reading. The select gates of the memory cells are set to the low level, and the select gates of the remaining seven memory cells in the NAND bundle are set to the high level. Bit line and N
The gate of the selection transistor T1 between the AND bundles (select line SL (1)) and the gate of the selection transistor T2 between the GND bundle and the NAND bundle (select line SL (2)) are set to a high level. In the non-volatile semiconductor memory having the NAND structure, the threshold value of the written memory cells is positively distributed as shown in FIG. 22B, but the writing is performed from the gate voltage (H level) of the non-selected transistors in the NAND bundle. The amount of electrons injected into the memory cell is controlled so that the subsequent threshold value becomes low. Therefore, if the threshold voltage of the selected memory cell is positive, no current flows between the bit line BL and GND and the bit line becomes high level. On the contrary, if the threshold voltage of the selected memory cell is negative, current flows between the bit line and GND, and the bit line becomes low level. Memory cell data is read by sensing the potential of the bit line.

Next, the write operation will be described. Figure 2
As shown in FIG. 3A, a high voltage (V _pp ) of about 20 V is supplied to the select gates of the selected memory cells from the row decoder, and the select gates of the other seven memory cells in the same NAND bundle are supplied to the select gates. An intermediate voltage (VPI) of about 10V is supplied. In addition, 0V is applied to all select gates of other NAND bundles.
Is supplied. NA including the memory cell selected at this time
The gate voltage of the select transistor between the ND bundle and the bit line is set to 12V, and the gate voltage of the select transistor between the NAND bundle and the source line is set to 0V. In this state, when the bit line is set to 0V, the N selected by the selection transistor
Drain, source of all memory cells in the AND bundle,
Since the potential of the channel is 0V, a potential difference of 20V occurs between the select gate of the selected memory cell and the channel, and electrons are injected from the substrate to the floating gate. At this time, a potential difference of 10 V occurs between the select gates and channels of the other seven memory cells in the same NAND bundle,
Since the oxide film thickness between the floating gate and the channel is set so that electrons are hardly injected at a potential difference of 0 V, "0" data is not written in the other seven memory cells. Further, if the bit line is set to a write-inhibit drain voltage (VDPI) of about 10V, the potential difference between the select gate and the channel of the selected memory cell becomes 10V,
Writing is not done. At this time, since no potential difference occurs between the select gates and channels of the other seven memory cells in the same NAND bundle, writing is not performed. Data is written by supplying 0V to the bit line when writing "0" data to the memory cell selected in this way, and by supplying a voltage of VDPI to the bit line when writing "1" data. .

Finally, the erase operation will be described. Figure 24
For erasing, the substrate is set to 20 V (V _pp ) and the select gate is set to 0 V, so that electrons in the floating gate are extracted to the substrate to perform erasing. At this time, the select line is set to 2 to relieve the gate stress of the select transistor.
It is set to 0V ( _Vpp ). Further, the bit line and the source line are set to OPEN so that the P-N junction portion in the memory array does not become the forward bias state, and the potential becomes approximately V _pp .

Since the current flowing through the bit line at the time of writing is small in the NAND structure semiconductor memory in which the writing is performed by the tunnel current as described above, it is possible to simultaneously write to several thousand memory cells.

FIG. 25 shows a 4M N currently in practical use.
FIG. 26 is a diagram illustrating an operation mode of an AND structure semiconductor memory, in which 512 bits × 8 (I / O) = 4096 bit lines are arranged in the column direction and 128 NAND bundles are arranged in the row direction as shown in FIG. × 8 bits = 1024
Book word lines are arranged. When writing to this memory, each data register connected to each bit line must have an I
After inputting data 512 times from the / O buffer circuit (FIG. 25 (b)), writing is collectively performed to 4096 bits (FIG. 25 (c)). Further, at the time of reading, a random read mode (FIG. 25 (d)) in which data in a memory cell is transferred to a data register and then specific column address data is read, and an in-page read mode in which only the contents of the data register are read (FIG. 25 (e)). ). When the row address (page address) is switched, it becomes a random read state, and it takes 10 μsec to read the data of the memory cell, but when the column address (in-page address) is switched, page reading becomes possible, and 70 nsec. High-speed reading is possible. FIG. 26 is a block system diagram of the semiconductor memory configured as described above. For each bit line, a sense amplifier circuit for determining the potential of the bit line and reading the data of the memory cell and a data for reading and writing are shown. The data register to be latched is connected. Further, the data register is configured so that data can be selectively output and input by the column decoder output selected corresponding to the column address. In addition, the row decoder circuit driven by the row address buffer includes a selected word line,
It is configured to supply the different voltages described above to the other seven word lines of the NAND bundle including the selected memory cell and the word lines of the other NAND bundle in the read, write, and erase modes, respectively. The read, write, and erase modes are controlled by command codes input from the I / O buffer circuit. Figure 27 shows the command data
As shown in (4), the chip operation is determined by the command register output which is captured in the command register by the clock of the external control signal NWE. FIG. 28 is a diagram showing the timing of random read (page read) and in-page read in the operation mode of FIG. 27. The access time (t _acc ) when the row address is switched is as slow as 10 μsec, but the column address Since the access time (t _pac ) when switching is performed is as high as 70 nsec, the average access time in the case of continuous reading of one page is (10 μsec +70
nsec × 511) /512=89.3 nsec, which enables high-speed reading. FIG. 29 shows the input waveform timing when batch writing is performed after serial data is input. First, when the command code [40] is input from the I / O buffer, the control circuit causes the chip to output 512
A byte serial data input mode is set, and a row address and 512 bytes of data are input by the clock of the external control signal NWE. When the 512th byte data is input, 4096-bit data write is automatically performed. After that, in order to check whether the data is written correctly, the user inputs the command [CO], recovers the high voltage supplied to the word line and the bit line at the time of writing, and increments the column address while performing the recovery operation. Perform a verify operation to read the data of the column address. When the read data is different from the data to be written, the user needs to input the command [40] again to write. In the conventional memory configured in this way, when reading / writing data of arbitrary length from an arbitrary address,
The external chip that controls the memory identifies the column address and row address of this memory and reads the data after 10 μsec when the page address changes, and reads the data after 70 nsec when the in-page address changes. You must access the EEPROM to do FIG. 30A shows three column addresses (A0 to A).
2) shows a program sequence of the memory control chip when reading continuous data from addresses 2 to 1F of the semiconductor memory configured by 7 row addresses (A3 to A8). The figure (b) shows the concept.
Since the memory cell data must be transferred to the data register during the first read, the access time is 10μ.
It becomes sec. Next, since only the column address is switched from the second address to the seventh address, the read operation is performed in 70 nsec while incrementing the column address. At the next address 8, the row address is switched, so it is necessary to transfer the memory cell data to the data register again, and the access time becomes 10 μsec. Further, from address 8 to address F, continuous reading of 70 nsec is performed.

As described above, in the conventional semiconductor memory, it is necessary to use the program in which the reading speed is changed in consideration of the number of bits in one page of the semiconductor memory to be used. Therefore, when the number of bits in one page of the semiconductor memory used changes, it is necessary to recreate the program of the memory control chip.

FIG. 31 (a) shows the program sequence of the memory control chip when writing is performed in the semiconductor memory having the column address and row address configuration as in FIG. As shown in the input waveform timing of FIG. 29, the conventional semiconductor memory has 1
After inputting data for a page, write operation starts.
Therefore, as shown in FIG. 31A, it is necessary to input dummy unnecessary data to addresses 0 and 1 even when writing data from addresses 2 to 7. For example, if one page is composed of 512 bits and only one bit of it is written, it is necessary to input unnecessary data of 511 bits. In addition, in the conventional semiconductor memory, it is necessary to read in the program verify mode in order to determine whether or not writing is normally performed after programming, and to determine whether to perform writing again by comparing with program data. As described above, when data is written to the conventional semiconductor memory, the program of the memory control chip becomes complicated, and the data writing time to the semiconductor memory is long.

As described above, the conventional reading / reading in page units
Since the writable semiconductor memory is configured as described above, when reading continuous data, the memory control chip determines whether to read within the same page address as the previous address or not. When different semiconductor memories are used, it is necessary to change the program of the memory control chip. Further, when using a large number of semiconductor memories having different numbers of bits per page, the memory control chip needs to individually manage the address length of one page of each semiconductor memory. Further, at the time of writing, it is necessary to input the data for one page even when writing the data length of one page or less, and the time required for writing becomes long.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to increase the memory capacity in such a memory system.

[0012]

According to another aspect of the present invention, there is provided a memory system having a plurality of non-volatile semiconductor memories, wherein each of the at least two non-volatile semiconductor memories is arranged in a matrix. Data having memory cells arranged in a selected row among the memory cells are transferred in parallel to a plurality of data registers, the data in these data registers are serially output to the outside, and this operation is sequentially repeated. A page-readable non-volatile semiconductor memory that returns, address input means for storing a read start address inputted from the outside, input / output terminals connected to the data register and the address input means, and The address stored in the address input means is incremented in response to the read clock signal The address control means and the read means for transferring the data of the memory cell to the data register after the output of one page of data from the data register is completed, and the read means, while the transfer is being performed by the read means, A busy signal output terminal for outputting a busy signal indicating that access is not possible to the outside, the address includes a column address and a row address, and the column address is sequentially incremented in response to the read clock signal, When the column address reaches the last column address in the page, the row address is incremented, the column address is set to the first column address in the next page, and the data reading of the next page is started. Has been
The busy signal output terminals of the at least two or more nonvolatile semiconductor memories and the input / output terminals of the at least two or more nonvolatile semiconductor memories are commonly connected.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block system diagram showing an embodiment of a non-volatile semiconductor to which the present invention is applied. For simplicity, a column address (in-page address) is A0 to A2, and a row address (page address) is A3 to A8, 1536. A bit semiconductor memory (512 bits × 3 I / O) is shown. The memory cell has an 8-NAND configuration similar to the conventional circuit of FIG.
The relationship between the bit line potential, the word line potential, and the gate potential of the select transistor during reading and writing of the memory cell is the same as in the conventional example. The external address is input via the I / O buffer circuit at the time of reading and writing, and A0 to A
The column address of 2 is stored in the column address buffer circuit,
Row addresses A3 to A8 are latched by the row address buffer circuit. The command circuit and the internal operation control circuit have external control signals CLE, ALE, NWP, NCE,
NWE and NRE are input from the respective input pins to determine the operation mode of the chip. In addition, a signal indicating whether the chip is accessible or not is sent from the control circuit.
It is output to the outside via the / Busy pin. FIG. 2 shows an operation mode of the chip determined by the control signal. The external control signal CLE determines the command input mode, and the external control signal ALE determines the address input mode. Further, the external control signal NCE is a chip select signal, and the external control signal NWE functions as a clock signal for fetching respective input data in the command input mode, the address input mode and the data input mode. Further, the external control signal NRE is a clock signal having an address increment function for reading consecutive addresses from the input address at the time of reading data and an output buffer enable function. In the semiconductor memory configured as described above, when a glitch occurs in the input data signal and an erroneous command is input, the memory is likely to be in a write or erase state and the stored data may be destroyed. Therefore, the semiconductor memory of this embodiment has a program / erase protection function that regulates the chip not to perform the write operation and the erase operation when the external control signal NWP is in the "L" state. As mentioned above, the Ready / Busy output terminal
Busy of "L" level when the chip is inaccessible
"H" when the signal is output and the chip is accessible
A level Read signal is output.

Next, the read operation of the nonvolatile semiconductor memory of this embodiment will be described. FIG. 3 is a diagram showing the input waveform of the control signal and the data output timing when continuous reading is performed from the column address N and the page address M.

First, in the address input mode of FIG.
At the same time as the column address and the page address are taken into the address buffer, the "L" level inaccessible signal indicating the busy state is output to the outside. At this time, as shown in FIG. 3B, the memory cell information connected to the selected word line is output to the bit line and latched in the data register circuit. When this latch operation is completed, an "H" level accessible signal indicating the Read state is output to the outside to notify the chip controller that the stored data can be read. Next, while incrementing the in-page address (column address) input by the clock of the external control signal NRE, the data is output to the outside with an access time of 70 nsec (Fig. 3-
(C)). Next, when the reading of the last address in the page is completed, the page address is incremented, and at the same time, the "L" level inaccessibility signal indicating the busy state is output to the outside, and the word line selected by the new page address is connected. The memory cell information is latched in the data register circuit (FIG. 3- (d)). Upon completion of this latch operation, an "H" level accessible signal indicating the Ready state is output to the outside, and the page address is incremented from the address 0 within the page (column address 0) in response to the clock of the external control signal RE. While outputting the data (Fig. 3- (e)). This continuous operation is repeated by the data length of the continuous data you want to read,
After the end of reading the final data, the external control signal NCE is set to the “H” level to end the series of read operations.

FIG. 4 is a circuit diagram showing an address buffer circuit configured to perform the address input and address increment operations described above. This address buffer circuit includes a binary counter using CMOS transfer gates TG1 to TG4, means for setting the inside of the binary counter to a logic level corresponding to an input address signal, and means for resetting the inside of the binary counter to a predetermined logic. Composed of. Dn is connected to the I / O input / output terminal and receives address information from the outside. The data latch control signal LPn is an internal control signal which becomes "L" level only for a predetermined period in response to the rising of the external control signal NWE in the address input operation mode, and I / O when LPn is "L" level. The address information of the input / output terminal includes NOR gate NOR1, inverter INV1, NAND gate NAND1, clocked inverter CINV1,
It is transferred to the internal nodes N2 and N4 of the binary counter via the clocked inverter CINV2. When LPn becomes "H" level after a predetermined period, the clocked inverters CINV1 and CINV2 are inactive, and the clocked inverters CINV3 and CINV4 are active, so that the address information is latched in the binary counter. A signal in phase with the latched address information is output to the internal address signal output terminal AiS of the address buffer circuit, and a signal in phase with the latched address information is output to the internal address signal output terminal AiSB. The input terminals Ai-1 S and Ai-1 SB of this address buffer circuit are connected to the internal address signal output terminals of the address buffer circuit immediately before this address buffer circuit. When the address signal changes by two cycles, the internal address signal of the address buffer circuit changes by one cycle. The internal address signal of each address buffer circuit is input to the corresponding decoder circuit, and the word line and the bit line corresponding to the internal address signal are selected similarly to the conventional circuit. The reset signal RST changes the internal address signal AiS to the “L” level and the internal address signal AiS.
A signal used to reset B to logic "H". When the reset signal RST changes from "L" to "H" to "L", the internal address signal is set to the predetermined logic level. .

FIG. 5 is a circuit diagram for explaining the operation of the address buffer circuit of the 1536-bit semiconductor memory composed of column addresses A0 to A2 and row addresses A3 to A8. The circuits of symbols ABUF0 to 8 in this circuit diagram show address buffer circuits corresponding to addresses A0 to A8, respectively, which are the same as the address buffer circuits in FIG.

A0-A2 address buffer circuit ABU
The address latch control signal LP1 is commonly input to F0 to 2, and the address buffer circuit ABUF3 of A3 to A5 is input.
5 to 5, the address latch control signal LP2 is input in common, and further, the address buffer circuits ABUF6 to A8 in A6 to A8 are input in common with the address latch control signal LP3. The data input / output terminals Dn of the address buffer circuits ABUF0, 3, 6 are commonly connected to the input / output terminals of the I / O0, and the data input / output terminals Dn of the address buffer circuits ABUF1, 4, 7 are commonly connected to the I / O1. Connected to input / output terminals. Further, the address buffer circuits ABUF2, 5,
The eight data input / output terminals Dn are commonly connected to the input / output terminals of the I / O2. Further, the reset signal input terminals of the address buffer circuits A0 to A2 clear the contents of the address register in the data register read mode which will be described later and a signal RST which becomes the "H" level for resetting the inside of the chip when the power is turned on. Therefore, an OR logic signal of the signal DATARPUL which becomes the “H” level is input.

The circuit operation of FIG. 5 will be described below in the case of the read mode operation of FIG. Since the address data is input from the data input terminal, if the external control signal NWE changes from "H" to "L" to "H" level, "H" →
The address latch control signal LP1 of a pulse changing from "L" to "H" level is generated. At this time, the other address latch control signals LP2 and LP3 are held at the logic "H". As a result, as described above, the data input / output terminal I / O
The address information supplied to 0, 1, 2 is latched in the address buffer circuits A0 to A2, and the internal address signal is set to the logic level corresponding to the input address information. Next, in order to input address data from A3 to A5, A3 is input to each I / O0 to I / O2.
When the address data from A to A5 is input and the external control signal NWE changes from "H" to "L" to "H" level,
The address latch control signal LP2 of a pulse that changes from "H" to "L" to "H" level is generated. At this time, the other address latch control signals LP1 and LP3 are held at the logic "H".

As a result, the data input / output terminals I / O0,
The address information of A3 to A5 supplied to 1 and 2 are respectively supplied to the address buffer circuits ABUF3 to AB.
The internal address signal is latched by UF5 and set to a logic level corresponding to the input address information. Finally, the address data from A6 to A8 is input to I / O0 to I / O2, and the external control signal NWE is set to "H" →
When changing from "L" to "H" level, "H" → "L"
The address latch control signal LP3 of a pulse changing to "H" level is generated, and the address data from A6 to A8 is latched in the address buffer circuits ABUF6 to ABUF8. In this way, the address information of A0 to A8 supplied to the I / O input / output terminals in the three steps of the NWE pulse is input to each address buffer.

FIG. 6 shows the above-mentioned address latch control signal LP.
It is a circuit diagram which shows the circuit which produces | generates 1-LP3. The shift registers symbolized here are shown in FIG.
9 represents the shift register circuit shown in FIG. This circuit is an LA which is at "H" level for a predetermined period in response to the rising of the external control signal NWE when inputting address data.
Receiving the TPULA signal, it forms negative logic data ratter pulse signals LP1, LP2, LP3. When the power is turned on and when the external control signal ALE changes from “H” to “L” level, the reset signal ARST is at “H” level for a predetermined period, so that the output of the first shift register is at “H” level,
The outputs of the second to fourth shift registers are initialized to "L" level. Next, at the time of address data input, when the positive logic LATPULA signal is output corresponding to the NWE clock of the first step, since the output signal of the first shift register is at the “H” level, the NAND gate N
Negative logic address latch control signal LP via AND2
1 is output. Further, the shift register advances by one stage in response to the fall of the pulse signal LATPULA, the output of the second shift register is at "H" level, and the outputs of the first, third and fourth shift registers are at "L". It becomes a level. Next, when the LATPULA signal is output again in response to the NWE clock in the second step, the output signal of the second shift register circuit is at the "H" level, so the address latch control signal of the negative logic is output via the NAND gate NAND3. LP2 is output. Further, the shift register advances one stage in response to the fall of the pulse signal LATPULA, and the output signal of the third shift register is at the “H” level,
The output signals of the first, second, and fourth shift registers are "L"
It becomes a level. Similarly, in response to the third step NWE clock, the address latch control signal LP3 is output via the NAND gate NAND4. N in the third step
When the address input is completed by the WE clock, the output signal of the fourth shift register becomes "H" level, and the CL of each shift register which is the output signal of the NOR gate NOR2.
The OCK input signal is held at "L" level. At this time, the CLOKB input signal of each shift register is held at "H" level by the NAND gate NAND5. Therefore, even if the NWE clock signals of the fourth and fifth steps are input and the pulse signal LATPULA is generated, the output signals of the first, second and third shift registers hold the "L" level, and the address latch control is performed. No signal is output.

In this way, when the address input ends with the 3-step NWE clock signal, the Busy signal is output in response to the level change of the third latch data control signal LP3, and the address buffer corresponding to the row address is output. The word line corresponding to the internal address signal of the circuit is selected. After a predetermined delay time (10 μsec), the control gate is connected to the selected word line.
The memory cell data for a page is read out via the bit line and latched in the data register.

Next, the read operation when the external control signal NRE is changed from "H" to "L" to "H" in order to read the contents of the data register will be described with reference to FIGS. The pulse signal PUL is a signal output when the external control signal RE is changed from “H” to “L” level in the serial read operation mode. The signal PUL and its inverted signal PULB are input terminals of the address buffer circuit A0. It is supplied to Ai-1S and Ai-1SB. However, when reading the first column address after inputting the address or when reading the first column address after the page address has been switched and the data register contents have been rewritten,
The pulse signal PUL is not output in response to the change of the ad / Busy signal from "L" to "H" level. When the external control signal NRE is changed from "H" to "L" level after the address is input (the column address = address 4 in FIG. 9) in the semiconductor memory configured as described above, the data register of the address 4 is changed. The contents are output to the I / O input / output terminal, and the I / O input / output terminal changes from the high impedance state to a predetermined level. At this time, since the pulse signal PUL is not generated as described above, the binary output signal (= internal address signal) of the address buffer circuit does not change. Next, when the external control signal NRE changes from "L" to "H" level, the I / O input / output terminal becomes a high impedance state. When the external control signal NRE changes from "H" to "L" level again, the pulse signal PUL is generated this time, so that the internal address signal A0S of the address buffer circuit ABUF0 changes from "L" to "H" level. Thereafter, the contents of the data register selected by this internal address signal (column address = 5) are output to the I / O input / output terminal. After that, the external control signal NRE is changed from "L" to "H"
When it changes to the level, the I / O input / output terminal becomes a high impedance state. Next, the external control signal NRE is "H" →
When it changes to "L" level, the pulse signal PUL changes the internal address A0S from "H" to "L" level, and in response to the change of A0S, the internal address signal which is the output signal of the address buffer circuit ABUF1. A
1S also changes from "L" to "H" level. In this way, the internal address determined by the internal address signals A0S, A1S, A2S is incremented by the signal PUL. External control signal NRE is "H" at the 4th step →
When the level changes to "L" level, all the internal column address signals become "H" level, so that the signal COLEND changes from "L" to "H" level. This signal COLEN
When D is "H" level, external control signal RE is "L"
→ When it changes to “H” level (4th step), the pulse signal PUL is output, the internal address is incremented, and the Ready / Busy signal changes from “H” to “L” level. In this way, the internal column address after the continuous reading from the address specified by the input address to the final address of the column is 0 by the clock of the external control signal NRE, and the row address ( Page address) is incremented. BU
In response to the output of the SY signal, the memory cell data whose gate is connected to the newly selected word line is transferred to the data register after a predetermined read time (10 μsec),
READY signal indicating that the chip is accessible
Output to the Ready / Busy output terminal. Chip is Read
When the clock external control signal NRE is input after the change to the y state to perform the read operation (fifth step), Ready
Since the / Busy signal is the first read operation after changing from "L" to "H" address, the signal PUL is not output,
The contents of the data register at column address 0
It is output to the O input / output terminal.

After this, when reading to the final address of the column by the clock of the external control signal NRE, the Busy signal is output again to the Ready / Busy output terminal as described above, and the memory cell data of the next page address is output. Are transferred to the data register. When reading the final address of the internal address, the signal COLEND is "L" →
The signal AEND changes from "L" to "H" level while changing to "H" level. After the last address is read, the next external control signal NRE is set so that the read operation is not performed. Therefore, when the signal AEND after reading the final address changes to "H" level, the READY signal remains held at the Ready / Busy output terminal, and the external control signal NRE changes from "L" to "H" level. However, the pulse signal PUL is not output. Further, since the BUSY signal is not output, the memory cell data is not transferred to the data register. in this way,
When reading is performed up to the final address of one chip, the address is incremented and the signal AEND is set so that the memory cell data at address 0 is not read.
Is in control.

FIG. 10 shows a program sequence of the memory control chip when continuous data reading is performed in the semiconductor memory configured as described above. In the semiconductor memory chip of this embodiment, if the chip is in an accessible state, it is possible to always read with the same access time (70 nsec), and a program for determining whether the column address (in-page address) is the final address is required. Not. Therefore, it is not necessary to change the memory control chip program even if a chip with an arbitrary in-page address length is used, and even if a large number of memories are used, it is possible to manage a large number of memories with a simple memory control chip program. There is. FIG. 11 shows a continuous example in the case where a large number of semiconductor memories configured in this way are used. By using the external control signal NCE as the highest address, this system can be used as a bit in one semiconductor memory. It becomes possible to manage like one semiconductor memory having a memory capacity larger than the capacity.

FIG. 12 is a diagram showing the input waveform of the external control signal and the data input timing when writing to the semiconductor memory described above. First, when the serial data input command 80H is input in the command data input mode, the chip enters the address input mode for inputting the program start address. In the address input mode, similarly to the read mode described above, the column address and the page address are fetched into the respective address buffer circuits at the three-step clock of the external control signal NWE, and each internal address signal is subjected to a predetermined logic corresponding to the input address data. Set to level. In the above-mentioned read mode, the Busy signal is output to the Ready / Busy output terminal and the memory cell data is transferred to the data register after the address information of the third step is input, but in the serial data input mode, the Ready / Busy output terminal Is configured to hold the Ready signal, and the read operation of transferring the memory cell data to the data register is not performed. When the serial data input command 80H is input, all the data in the data register are initialized to "H" level.

This operation will be described with reference to the data register circuit of FIG. 13 and the timing chart of FIG. FIG. 13 shows a data register circuit provided for each bit line, and includes clocked inverters CINV5 and CINV.
6 functions as a data latch, and the clocked inverter CINV5 functions as a sense amplifier when reading data. Further, the N-channel transistor whose gate is supplied with the signal PRE is used when precharging the data latch unit, and at this time, the bit line and the data latch unit are electrically disconnected by the N-channel transistor whose gate is supplied with the signal BLCD. . Further, this data register circuit is connected to a common bus line IOi / IOiB provided for each I / O via a column gate transistor whose gate receives a column decoder output signal CSLj. First, the serial data input command 80
When H is input from the I / O input output terminal, all the column gate transistors are turned off and the signal SENB,
RLCHB goes to "H" level and signals SEN, RLC
Since H changes to "L" level, the clocked inverters CINV5 and CINV6 are inactivated. At the same time, the precharge signal PRE changes to "H" level, so that the nodes BLj in all data registers are precharged to "H" level. After this precharge operation, the signal SEN changes from "L" to "H" level, and the signal RLCHB
Changes from "H" to "L" level and the node NBLj is set to "L" level. In this way the node BL
After the setting of j and NBLj is completed, the signal SENB changes from “H” to “L” and the signal RLCH changes from “L” to “H” level, and the above-mentioned setting data is latched in the data register circuit. . By this initializing operation, the nodes BLj of all the data registers become "H" level, and the data of all the data registers are set to "1". After that, when the address input operation ends, the signal SD
Since the IC changes from "L" to "H" level, the write data and its inverted data are transferred from the I / O input / output terminal to the common bus line IOi / IOiB. Next, while the external control signal NWE is at "L" level, the column decoder output signal CSL6 corresponding to the input column address (address 5) becomes "H" level. Buffer inverters BUF1 and BUF2 driving a common bus line
Since the current drivability of is set to be sufficiently larger than that of the clocked inverters CINV5 and CINV6, the latch content of the data register selected by the column decoder output signal CSL6 is rewritten to the write data on the common bus line. In this way, data is input from the addresses 5 to 7 by the clock of the external control signal NWE. As a result, the contents of the data register from the column addresses 0 to 4 are latched with the data "1" at the time of initialization. Therefore, the data input from the I / O input / output terminals are latched at column addresses 5 to 7. When the program command 10H is input in the command input mode after the data input mode, the chip writes data in the memory cell.

[0028] During the data writing, the power VBITH latch circuit is changed to VDPI potential of 10V from V _cc potential. At the same time, the potential of the signal BLCD is 0V to 12V.
As a result, the bit line and the latch circuit are electrically connected to each other, and as a result, the bit line whose data register data is "1" is set to the VDPI potential and the bit whose data register data is "0". The line is set to 0V.
Therefore, the data in the data register is connected to the bit line whose data is "0", electrons are injected into the floating gate of the memory cell selected by the word line, and "0" data is written in the memory cell. Ready during the above write operation
The Busy signal is output from the / Busy output terminal, and the READY signal is automatically output when a predetermined writing time elapses. Whether or not this writing operation is completed normally is 70H in the command input mode.
By inputting the flag read command of, the result of the automatic verification stored in the internal register can be read from the I / O input / output terminal. Such a flag read function is a function that has been put to practical use even in the conventional semiconductor memory, and therefore its explanation is omitted.

FIG. 15 shows a memory control chip program sequence when writing data from addresses 2 to 7 of the semiconductor memory configured as described above. By using the semiconductor memory of the embodiment of the present invention, it is possible to input data from an address in the middle of one page and automatically initialize the data before the start column address into predetermined data. It is not necessary to execute the dummy data input instruction shown in the conventional example of FIG. 31, and the programming time can be shortened.

Next, the address register read function of the semiconductor memory of this embodiment will be described. This function is latched in the address register while the internal address is normally latched after the address is input at the time of data reading and data writing, or while the internal address is being incremented by the external control signal NWE clock. It is used when you want to read the internal address information.

FIG. 16 is a diagram showing the input timing of the external control signal when the contents of the address register are read by the circuit of this embodiment. FIG. 17 is a circuit diagram of the output buffer circuit of the nonvolatile semiconductor memory device according to the present embodiment.
8 is the signals AREG1 to 3 and NAREG1 to 3 of FIG.
6 is a circuit diagram of an address register read control circuit for generating the signal of FIG. Symbols 1st shift register and 2nd-4th shift registers in FIG. 18 represent the shift register circuits of FIGS. 7 and 8, respectively. First, when E0H is input in the command input mode, the chip enters the register read mode, the signal ADDR in FIG. 18 changes from “L” to “H” level, and the positive logic pulse signal ARRST for a predetermined period causes Output nodes AS1, AS2, AS3, A of each shift register in FIG.
S4 is reset to "H", "L", "L", "L" level, respectively. If the chip is in the read mode before the register read mode, the control signal READ / NREAD of the clocked inverter CINV7 shown in FIG.
Of the common bus line IOoB detected by the current mirror circuit CM are transferred to the node OUT because they are at "H" / "L" level. Next, in the register read mode, the signal READ changes from "H" to "L" level and the clocked inverter CINV7 becomes inactive, but the node OUT has a current driving capability of clocked inverters CINV7-1.
Since the latch circuit LAT formed by the inverter set to be smaller than 0 is connected, the level of the node OUT is held at the level before the register read mode. Next, in order to read the contents of the address register, when the external control signal NRE is changed to "L" level, the level of the node ADR in FIG. 18 changes from "L" to "H" level, and the signal AREG1 changes to "L" level. The "H" level changes in response to the "H" level. Therefore, the clocked inverter CINV8 in FIG. 17 is activated and the node O
Data corresponding to the logic level of the internal address signal A0S is latched in the UT. The signal BUS in FIG. 17 is Ready
/ Busy Internal BU of opposite phase to the signal output to I / O terminal
Since it is the SY signal and the chip is in the accessible state in the register read mode, the signal BUS is at "L" level. Therefore, the external control signal NRE is "L".
When it changes to the level, the node OE changes from "L" to "H" level, and a signal in phase with the internal address signal A0S latched at the node OUT is output to the input / output terminal I / O0. At this time, the input / output terminals I / O0, 1 and 2 are configured to output signals having the same phase as the internal address signals A0S, A1S and A2S, respectively. The addresses A0 to A2 can be read simultaneously.
Next, when the external control signal NRE is changed from "L" to "H" level, the node ADR becomes "L" level and the clocked inverter CINV8 becomes inactive. Further, in response to the change of the external control signal NRE, a negative logic pulse signal AREGPUL is formed as shown in FIG.
The output node AS1 of the shift register 8 is "H" →
To "L" level, and the output node AS2 is "L" →
It changes to "H" level. Therefore, the signal AREG2 becomes "H" level by the change of the external control signal NRE from the "H" level to the "L" level in the second step, and the data corresponding to the logic level of the internal address signal A3S is passed through the clocked inverter CINV9. Are latched at the node OUT. At this time, the level of the node OE is also “L” →
Since it changes to "H", a signal having the same phase as the internal address signal A3S is output to the input / output terminal I / O0. At the same time, signals of the same phase as the internal addresses A4S and A5S are output to I / O1 and I / O2, respectively. When the external control signal NRE changes from “L” to “H” level in the second step, the pulse signal AREG
Due to PUL, the output node AS2 of the shift register circuit in FIG. 18 goes from "H" to "L" level, and the output node AS2
3 changes from "L" to "H" level. When the external control signal NRE changes from "H" to "L" level in the third step, the internal address signal A6S is generated in response to the signal AREG3.
A signal having the same phase as is output to the input / output terminal I / O0. At this time, signals having the same phase as the internal address signals A7S and A8S are output to the input / output terminals I / O1 and I / O2, respectively. External control signal R at the 3rd step
When E changes from "L" to "H" level, the output node AS4 of the shift register changes to "H" level.
The output level of the shift register does not change in response to the signal AREGPUL. Therefore, even if the external control signal NRE clock of the fourth step is input, the signals AREG1 to
3 does not become "H" level, and finally the signal having the same phase as the internal address A0S latched at the node OUT is output to the input / output terminal I / O0. If the register read command EOH is input again, the pulse signal ARR
The contents of the shift register are reset by ST, and the internal addresses A0 to A8 can be read again.

Next, the data register read function will be described. This function is used to confirm the contents of the data register after data input in write mode. FIG.
As shown in FIG. 6, when the register read command EOH is input in the command input mode, a positive logic pulse signal DATARPUL that clears the internal column address latched in the address buffer circuit of FIG. Therefore, as described in the above read operation, when the external control signal NRE is input by the clock, the contents of the data register input in the data input mode can be continuously read from the internal address 0 to the final column address. . However, in the read mode described above, when the last column address is read, it is automatically
Busy signal is output from ady / Busy output terminal,
In the register-read mode, in response to the level change of the signal ADDR described above, the Ready / Busy output terminal receives Re
The ady signal is held and the Busy signal is not output. Furthermore, when the last column address is read in the read mode described above, the
The address is incremented, but in the register-read mode, the row address is controlled not to be incremented by the signal ADDR. Therefore, even if the write operation is performed after confirming the contents of the data register in the data register read mode, the contents of the data register are normally written to the memory cell at the predetermined row address input before the data register read mode. Can be done.

Next, the operation of resetting the internal address register and the data register when the power is turned on in the semiconductor memory of this embodiment will be described. In this embodiment, the internal address register and the data register are reset by setting the external control signal NWP to "L" level when the power is turned on and setting the external control signal NWP to "H" level after the power is turned on. To be done. The external control signal NWP executes those modes in order to prevent noise from being generated in other external control signals and the chip from erroneously rewriting the contents of the data register and writing / erasing data in the memory cell. It is an external control signal provided to control whether or not it is possible. As shown in the operation mode table of FIG. 2, when the external control signal NWP is at "L" level, the chip is configured so that data input, program / erase, and data transfer operation from the memory cell to the data register are not performed. It To prohibit the data input operation, when the external control signal NWP is at "L" level, the signal PUL of FIG.
Is held at the "H" level so that the increment operation of the internal address is not performed, the generation of the precharge signal PRE for performing the reset operation of the data register circuit of FIG. 13 and the signals SEN / SENB, RLCH /
The data transfer and the latch operation of the data register may be prohibited from the common bus line of RLCH5 and CSLj.

FIGS. 21A, 21B and 21C are circuit diagrams of the program / erase command input circuit, which shows the signal CM.
DWES is an external control signal N in the command input mode.
In response to WE, the level changes from "H" to "L". Further, CMDWESB is a signal having a reverse phase of CMDWES. Therefore, when a predetermined command code is input to the I / O input / output terminal in the command mode, the control signal of the corresponding command input circuit becomes "H" level. Since the internal operation of program / erase is controlled by the output signals RROG / ERASE of the respective command circuits shown in FIG. 21, the signal RROG / ERASE is set to the “H” level by the internal signal WPSB in phase with the external control signal NWP. By prohibiting this, the program / erase operation is not performed when the external control signal NWP is at "L" level. Further, the data transfer operation from the memory cell to the data register is performed by detecting that the internal signal having a phase opposite to that of the signal output to the Ready / Busy output terminal changes from “L” to “H” level. , The aforementioned internal signal WP
By holding this signal at "L" level at SB, the data transfer operation is prohibited when the external control signal NWP is at L level. In this way, the external control signal NWP rewrites the contents of the data register and writes / writes data in the memory cell.
It is used to inhibit the erase operation and also used to initialize the contents of the internal address register and the data register when the power is turned on. Figure 21
(C) shows a reset pulse generation circuit, and when the external control signal NWP changes from "L" to "H" level, a positive logic reset pulse RST is generated. The reset signal RST is input to the address buffer circuits of FIG. 4, and the output signals AiS of all the address buffer circuits are "L" due to the positive logic reset signal RST.
It is reset to level and the internal address is reset to address 0. Further, since the reset signal ARST input to the data latch control signal generation circuit shown in FIG. 6 is also output in the positive logic corresponding to the reset signal RST, the level of the output node of the shift register of the data latch control signal generation circuit is also set. As described above, it is set to a predetermined level. Since the reset signal ARRST input to the address register read control circuit shown in FIG. 18 is also output corresponding to the reset signal RST, each output node of each shift register circuit is reset to the above-mentioned predetermined level. Further, the latch data of each data register is the reset signal RS.
It is reset to "1" data by T. This signal RS
The reset operation by T is the same as the data register initial setting operation after the data input command 80H is input in the data input mode, and the column gate transistor CSL is used.
Precharge operation by signal PRE when j is non-conducting, signal SEN / SENB and signal RLCH / RLCH
The latch operation by B is performed. In the non-volatile semiconductor device configured as described above, when the power is turned on, the external control signal NC
External control signal NWP even if E, CLE, and ALE are indefinite
By fixing the voltage to "L" level, the malfunction of writing / erasing can be prohibited, and by changing the external control signal NWP from "L" to "H" level after the power supply voltage reaches a predetermined level. It is possible to reliably reset the latch circuit inside the chip.

Next, still another embodiment of the present invention will be described. FIG. 32 shows an address buffer circuit, and the symbolized address buffer ABUF is the same as that of the first embodiment. In this embodiment, another stage of the latch circuit ACLi is connected to the output side of the column address buffers A0 to A2. The contents of this symbol notation are as shown in FIG. Latch control signal REP,
REPBs are signals having opposite phases. When REP becomes "H", the output signal A of the address buffers ABUF0 to ABUF2
It takes in 0 to 2 and holds data while REP is "L". In this way, the current address is stored in the latch circuit and the address data of the address buffer circuit itself is incremented in advance, whereby the time required for the increment of the address buffer circuit can be shortened.

FIG. 35 shows a circuit for transferring the data latched in the data register to the data output buffer. SDiB is a signal after the data latched in the data register is input to and amplified by the current mirror type sense amplifier through the bus lines IOi and IOiB in FIG. SDiB is input to the latch A when the signal CENA becomes "H", and CENA becomes "L".
Then, the latch A holds the data. Furthermore, CENB
When B becomes "H", data is transferred to the latch B, and CE
Latch B holds the data when NBB becomes "L". By using such a circuit, it becomes possible to fetch the data of the next address from the data register to the latch A while outputting the data of the latch B to the outside of the chip.

A case where the circuit of the present invention is applied to serial read will be described. FIG. 34 is a timing chart showing the operation of main signals for one cycle of random access and serial access. Signal PRE,
BLCD, SEN, SENB, RLCH, and RLCHB are the signals shown in FIG. 13, and are shown in FIG.
It changes as shown in FIG. After three-step address input or serial access, random read is entered and the state becomes Ready, the word line selected in the previous operation is deselected, and the word line to be accessed is selected. After that, the signal PRE becomes "H", and the bit line and the data register are precharged. At this time, BLCD is "H", and the bit line and the data register are connected. After that, PRE becomes “L”, and then the signal SEN becomes “L” → “H” →
When "L" and RLCHB change from "H" to "L" to "H", the "H" level is latched at the node BLj in the data register. After that, the signal RDENBR becomes "H", and a predetermined voltage is set to the control gate of the selected 8nd cell. After a predetermined time, signal S
When EN changes from "L" to "H" and SENB changes from "H" to "L", CINV5 in FIG. 15 is activated and the read data is sensed. After that, the RLCH changes from "L" to "H" and the RLCHB changes from "H" to "L", so that the sense data for one page is latched. Then, after a predetermined time, the data at the column head address is transferred from the data register to the output latches A and B in FIG. That is, in response to the signal CEN, the output gate CSLij of the data register corresponding to the head address is opened, and the data is transferred to the current mirror type sense amplifier. At the same time, change CENAB from "H" to "L" to "H"
By this, this data is transferred to the latch A. At this time, CENA changes from "L" to "H" to "L". CENBB is a signal that operates with a waveform substantially in phase with NRE, and CENAB is first "H" → "L" →
When changing to "H", the input gate of the latch B is open and the data is transferred to the latch B. At the same time,
The column address counters ABUF0 to ABUF2 are incremented once by PUL1 and the output thereof indicates the next address. However, since the REP remains at the "L" level, the internal address remains indicating the head address. Perform the above operation within the time of random access,
The Ready / Busy signal is set to "H" to notify the outside of the chip that the random read is completed. When serial access is subsequently performed, when the external control signal NRE becomes "L", the head address data is output from the latch B to the outside through the data output buffer. At the same time, the chip operates to transfer the data of the next address to the latch A. That is, in response to the clock input of the control signal NRE for outputting the data of the head address, the signal R
EP is output, and the data of the next address of ABUF0 to 2 is taken into the address output latches ACL0 to 2 (after that, the column address buffer is incremented by the signal PUL1 and the data of ABUF0 to 2 further indicates the next address). . Data of the next address is transferred to the latch A by the signals CEN and CENAB from the data register corresponding to the next address. After that, the control signal NR
When E becomes "H" and the output of the data of the head address is completed, CENBB also becomes "H", and the data of the address next to the latch A is transferred to the latch B. In this way, the data at address n is output in response to the clock input of the control signal NRE, and at the same time, the data at address n + 1 is transferred from the data register. Since the time is output through the data output buffer, the cycle time of data output can be shortened. In the present embodiment, the data in the address buffers ABUF0 to 2 indicate two addresses ahead of the data being output at that time, and the data in the address output latches ACL0 to ACL2 indicate one address ahead. Therefore, a signal for incrementing the row addresses A3S to A8S is required after the output of the data at the final column address is completed. As shown in FIG. 32, in this embodiment, the signal PUL2 is input as the input signal of the address buffer ABUF3. The signal PU is shown in FIG.
The circuit which outputs L2 is shown. When the serial access is performed by the NRE clock and the data of the address immediately before the column last address is output, the address output latches ACL0 to ACL2 indicate the column last address. Corresponding to this, a signal COLEND indicating that it is the last address of the column
Is output. When the clock of the control signal NRE is input to output the data of the final address of the column, a pulse signal is output to the node NA in response to the fall of NRE in the circuit of FIG. At this time, "H" is input to the other gate of the NAND1, so that the flip-flop F1 is set and the node NB becomes "H" level. When the control signal NRE becomes “H” after outputting the data of the final address, the PUL2 is output through the NAND2.
Until the flip-flop F1 is reset through the delay circuit delay3 until the PUL2
Keeps the "H" level. As for the delay time of the delay circuit delay2, COLEND is “H” one before the last address of the column.
Since it becomes the level, it is set so that the pulse output to the node NA is not picked up by the clock of the control signal NRE at that time. Thus, the output of the data of the final address is detected, PUL2 is output, the address buffers A3 to A8 are incremented, and the random access to the next page is performed.

Next, an example in which proper writing can be performed even when there is a defective bit line will be described.

FIG. 37 is a flow chart for explaining the internal preset operation after inputting the data input command in the chip of this embodiment. When writing is performed in this sequence, if there is a defective bit line in which the bit line wired with Al is short-circuited with the source line, there is a problem as described below.

That is, the column address of such a defective bit line is usually stored in the redundancy circuit by cutting the fuse or the like. When the address of the defective bit line is selected, the column redundancy bit line is selected instead of the defective bit line. However, the precharge operation and the initial data preset operation of the data register shown in FIG.
This is done for all bit lines regardless of the column address. Therefore, as shown in FIG. 13, the data register of the defective bit before being relieved by the redundancy circuit is preset to the write inhibit “1” data because the transistor whose gate receives the signal PRE becomes conductive. It In this case, the following problems occur. In the data latch circuit of FIG. 13, the power VBITH latch circuit of the data register from the external power supply V _cc, the power is supplied by a booster circuit built-in chip VDPI (10V), switches, and signal BLCD 0
It changes from V to 12V of the internal power supply. At this time, the node BL of the data register to which the above-mentioned defective bit line is connected
Since j is at the high level due to the preset operation described above, the P-channel transistor of the clocked inverter CINV6 is in the conductive state, and the power source VBIT
A leak current flows from H to the ground potential. Power supply VDP
Since I is the output of the booster circuit, the current supply capability is usually 1
It is as small as mA or less. Therefore, when a leak current flows through the defective bit line, the potential of the power supply VDPI drops below 12V. Along with this, the bit line potentials of other write inhibits also drop below 12V, which causes a problem of erroneous writing.

FIG. 38 is a flow chart showing the write operation of another embodiment of the present invention which has solved this problem. Further, FIG. 39 shows the sense amplifier of this embodiment.
It is a circuit diagram of a data register. In this embodiment, when a data input command is input, each bit line is charged via the N-channel transistor TrNl connected to each bit line. After a predetermined read time after charging the bit line, the signal BLCD is set to the high level to transfer the data on the bit line to the data register. During this predetermined time, all select lines are set to the non-selected state. Therefore, the level of the leaked bit line is lowered to the low level, and the level of the normal bit line without the leak of the bit line remains at the high level. The level of this bit line is latched in the data register. Such a bit line leak test is performed, and "0" data as write data is latched in the data register connected to the defective bit line regardless of the data of the memory cell, and the level of the node BLj in the data register is leveled. Preset to low level. Further, "1" data as write data is latched in the data register to which the normal bit line is connected, and the level of the node BLj in the data register is preset to the high level. As shown in FIG. 38, when the bit line leak test mode ends, write data is input to the data register from a predetermined address designated in the address input mode, and then writing is performed.

As described above, in this embodiment, at the time of writing, the content of the data register to which the defective bit line is connected is "0" data. Therefore, the P-channel transistor TrPl of the clocked inverter CINV6 in this data register is in a non-conductive state. Therefore, even if the write operation is started and BLCD becomes 12V, a leak current does not flow from the power source VBITH to the ground, and the voltage of VBITH does not decrease.

The data register preset operation by the bit line leak test may be performed, for example, when a reset command such as FF is input. That is, in this case, the FF reset command is executed before the writing is started, that is, before the data input command is input. As a result, the contents of the data register to which the defective bit line is connected are preset to "0" data, and the contents of the data register to which the normal bit line is connected are "1".
Preset to data. Then, the system may be configured to execute a data input command, input data from a predetermined address, and then perform a write operation.

As described above, according to the embodiment of the present invention, it is shown that the chip is inaccessible after the contents of the data register for one page are continuously read from the input address. The BUSY signal can be output to the outside of the chip, the row address can be automatically incremented, and the data in the memory cell can be transferred to the data register. Any data can be transferred without managing the address for one page outside the chip. Long memory data can be continuously read.

When data from a predetermined address designated by the input address to an arbitrary address is input, the contents of the data register of the address within the one page are automatically recognized as a predetermined value, so that one page Since writing can be performed without inputting data for one page when writing a smaller size, the time required for writing can be shortened. further,
Since the internal reset operation of the chip when the power is turned on is performed by the program / erase protect signal, the contents of the chip can be surely reset without using the power-on reset circuit.

[0046]

According to the present invention, since a plurality of nonvolatile semiconductor memories can be connected and controlled like one memory, the memory capacity can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory (memory system) of the present invention, in which a control circuit outputs Ready / Busy signals.

FIG. 2 is a diagram illustrating an operation mode of the semiconductor memory of the present invention, in which “Read / Busy” is set to “L” in “program erase” and “read (cell → register)” modes.

FIG. 3 is a timing chart of a read operation of the semiconductor memory of the present invention, in which a data register is being transferred from a cell (b).
And (d) are timing charts in "Busy" state.

FIG. 4 is a circuit diagram of an address buffer circuit of the present invention, showing a detailed circuit of a block ABUF in FIG. 5, in which an initial value can be directly set from a data input terminal I / On.

FIG. 5 is a circuit diagram of the address input means of the present invention,
The circuit diagram which comprises a binary counter.

6 is a circuit diagram of an address latch control signal generation circuit of the present invention, which is a latch pulse LP1 for latching an initial value in each group (upper / middle / lower) of a binary counter as the address input means of FIG. ~ A circuit diagram designed to generate LP3.

7 is a circuit diagram of a shift register circuit, showing details of a first shift register in FIG. 6;

8 is a circuit diagram of a shift register circuit, showing details of a second shift register in FIG. 6;

9 is a timing chart of internal signals for explaining the operation of the address input means of FIG.

FIG. 10 is a sequence diagram of a read control program for the semiconductor memory of the present invention.

FIG. 11 is a connection example when a large number of semiconductor memories of the present invention are connected and used, and an example in which control signals such as Ready / Busy are commonly connected.

FIG. 12 is a timing chart of the write operation of the semiconductor memory of the present invention, in which the column address, the row address, and the write data are fetched following the data input command 80H.

FIG. 13 is a data register circuit that initializes register data to “1” before data input.

FIG. 14 is a timing diagram of a write operation of the semiconductor memory of the present invention.

15 is a sequence diagram of a write control program of the semiconductor memory of the present invention, which is shown in FIG.
The sequence diagram in which the input of the dummy data, which was required in 1, is no longer necessary.

FIG. 16 is an operation timing diagram for explaining a register read operation of the semiconductor memory of the present invention, in which a command mode is set by a combination of control signals, a register read command E0H is fetched, and address data and register data are output. Timing diagram.

FIG. 17 is a circuit diagram (output buffer) of the output circuit of the semiconductor memory of the present invention.

FIG. 18 is a circuit diagram of an address register read control circuit of the present invention, which is a circuit diagram for generating a control signal for transferring an address from a binary counter to an output buffer.

19 is an internal signal timing chart for explaining an address register read operation of the output circuit of FIG.

FIG. 20 is a timing chart of the reset operation when the semiconductor memory of the present invention is turned on (see [0038]).

FIG. 21 is a command circuit and a reset signal generation circuit (see [0039]) for explaining a reset operation when the semiconductor memory of the present invention is powered on.

FIG. 22 is a diagram for explaining a memory cell operation in a NAND connection.

FIG. 23 is a diagram for explaining a memory cell operation, showing the correspondence between charge injection and data.

FIG. 24 is a diagram for explaining a memory cell operation (erase operation).

FIG. 25 is a view for explaining a conventional read operation.

FIG. 26 is a block diagram of a conventional non-volatile semiconductor device without ready / busy output.

FIG. 27 is a table illustrating operation modes of a conventional nonvolatile semiconductor device.

FIG. 28 is a timing diagram of a read operation of a conventional nonvolatile semiconductor device (see [0007]).

FIG. 29 is a timing diagram of a write operation of a conventional nonvolatile semiconductor device.

FIG. 30 is a control program sequence diagram for reading from a conventional nonvolatile semiconductor device.

FIG. 31 is a control program sequence diagram for writing a conventional nonvolatile semiconductor device, which is a sequence diagram when dummy data is required to be input.

FIG. 32 is another example of an address buffer circuit capable of pipeline operation.

FIG. 33 is a detailed diagram of a latch circuit (details of the ALCi block in FIG. 32).

34 is a timing chart of main signals in one cycle of random access and serial access in the address buffer circuit of FIG. 32.

FIG. 35 is a circuit for transferring data in a data register to a data output buffer (implementing pipeline operation).

FIG. 36 is a circuit for outputting a pulse signal PUL2 ([00
42]).

FIG. 37 is a write operation flowchart including a data register initialization operation of the present invention.

FIG. 38 is a write operation flowchart including an operation of initializing a data register by a bit line leak test of the present invention.

FIG. 39 is a circuit diagram showing an example of a sense amplifier / data register for realizing the bit line leak test of the present invention.

[Explanation of symbols]

101 Drain side select line 103 Source side select line 105 column address buffer 107 row address buffer 109 Command decoder 111 I / O terminal

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[Procedure amendment]

[Submission date] February 18, 2003 (2003.2.1
8)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012]

According to another aspect of the present invention, there is provided a memory system having a plurality of non-volatile semiconductor memories, wherein each of the at least two non-volatile semiconductor memories is arranged in a matrix. Data having memory cells arranged in a selected row among the memory cells are transferred in parallel to a plurality of data registers, the data in these data registers are serially output to the outside, and this operation is sequentially repeated. A page-readable non-volatile semiconductor memory for returning, address input means for storing a read start address inputted from the outside, a bus connected to the data register, and an output buffer connected to the bus An input / output terminal connected to the output buffer and the address input means; Address control means for incrementing the address stored in the memory in response to a read clock signal, and read means for transferring the data in the memory cell to the data register after the output of one page of data from the data register is completed. And a busy signal output terminal for outputting a busy signal indicating inaccessibility to the outside while the transfer is being performed by the read means, and the output is performed by the read clock signal in the first logic state. The buffer is enabled, and the data stored at the read start address is output in response to the first transition of the series of transitions of the read clock signal, and the address includes a column address and a row address. The address is sequentially incremented in response to the read clock signal. When the column address reaches the last column address in the page, the row address is incremented, the column address is set to the first column address in the next page, and the data reading of the next page is started. Further, it is configured such that the busy signal output terminals of the at least two or more nonvolatile semiconductor memories and the input / output terminals of the at least two or more nonvolatile semiconductor memories are commonly connected. R.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masamichi Asano             580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Semiconductor System Technology Center (72) Inventor Shigeyoshi Toku             580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Semiconductor System Technology Center (72) Inventor Toshio Yamamura             580-1, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Semiconductor System Technology Center F term (reference) 5B025 AC01 AD05 AD15 AE00

Claims (7)

[Claims] 1. In a memory system having a plurality of non-volatile semiconductor memories, each of at least two or more non-volatile semiconductor memories has a plurality of memory cells arranged substantially in a matrix, and among the memory cells, Page-readable nonvolatile semiconductor memory that transfers the data arranged in the selected row in parallel to multiple data registers, outputs the data in these data registers to the outside serially, and repeats this operation sequentially An address input means for storing a read start address inputted from the outside, an input / output terminal connected to the data register and the address input means, and a read clock for the address stored in the address input means. Address control means for incrementing in response to a signal, and the data register After the end of the data output for one page from the above, the read means for transferring the data of the memory cell to the data register, and a busy signal indicating that the access is disabled externally while the transfer is being performed by the read means. And a busy signal output terminal for outputting the column address, the address including a column address and a row address, the column address being sequentially incremented in response to the read clock signal, and the column address being the final address in the page. When the column address is reached, the row address is incremented, the column address is set to the first column address in the next page, and the data reading of the next page is started. The same busy signal output terminals of two or more nonvolatile semiconductor memories And a memory system in which the input / output terminals of the at least two or more nonvolatile semiconductor memories are connected in common. 2. The memory system according to claim 1, wherein the nonvolatile semiconductor memory is a NAND type memory. 3. The non-volatile semiconductor memory has a command latch enable terminal capable of taking in a command signal, and the command latch enable terminals of a plurality of the non-volatile semiconductor memories are commonly connected. The memory system according to claim 1 or 2. 4. The non-volatile semiconductor memory has an address latch enable terminal capable of taking in an address signal, and the address latch enable terminals of a plurality of the non-volatile semiconductor devices are commonly connected. The memory system according to any one of claims 1 to 3. 5. The non-volatile semiconductor memory has a write-inhibit terminal for setting write-inhibit, and the write-inhibit terminals of a plurality of the non-volatile semiconductor memories are commonly connected. Claims 1 to 4
The memory system according to any one of items 1. 6. The nonvolatile semiconductor memory has a write enable terminal to which a write enable signal is input as a clock signal that defines a command fetch timing in a command input mode, and the nonvolatile semiconductor device comprises a plurality of the nonvolatile semiconductor devices. 6. The memory system according to claim 1, wherein the write enable terminals are commonly connected. 7. The non-volatile semiconductor memory has 8-bit input / output terminals, and among the 8-bit input / output terminals of a plurality of the non-volatile semiconductor devices, corresponding ones are commonly connected. The memory system according to claim 1, wherein the memory system is a memory system.