KR100380285B1 - Flash memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory, wherein a logic circuit unit connected to two or more chip enable pins (CEB Pin), the two or more chip enable pins (CEB Pin) to generate a chip enable signal, and a ready / busy pin (R). / B Pin), and a program control unit connected to the ledge / busy pin to control the program operation of the unique number (ID), so that if the number of the chip enable pin is n to expand to 2 ⁿ It is. The logic circuit unit includes a chip enable buffer as many as the chip enable pins, a chip enable store cell as many as the chip enable pins, a comparator as many as the number of the chip enable pins, and a chip enable setting store cell. And one NAND gate, one NOR gate, one inverter, one AND gate, and one exclusive non-hap gate. The program controller includes one NMOS transistor, one NAND gate, and one inverter. The chip enable store cell and the chip enable setting store cell may include one NMOS transistor, one PMOS transistor, one flash memory cell, and three inverters, respectively, to reduce the number of control pins on the controller and control lines on the board. If the number of control pins of the controller is n, the flash memory having n number of chip enable pins can be freely added or deleted within 2n (n is the number of chip enable pins), so the memory can be easily expanded.

Description

Flash memory

The present invention relates to a flash memory, and more particularly, to a flash memory having a plurality of chip enable pins that can reduce the number of chip enable pins and the control line of the controller.

1 is a plan view pin-out of a conventional flash memory,

2 is a connection diagram of a conventional flash memory and a controller.

The conventional flash memory is configured to have only one chip enable pin (CEB Pin).

The conventional flash memory 10 is connected to the controller 1 in a 1: 1 manner through a chip enable pin (CEB Pin). That is, the number of control pins of the flash memory 10 is connected to the controller 1.

The controller 1 controls each flash memory 10 through a control pin. That is, in the initial state, the controller 1 outputs a 'high' state so that no flash memory 10 is selected, so that the elements in the flash memory 10 are turned off to reduce current consumption.

Thereafter, when the desired flash memory 10 is selected and a 'low' signal is supplied through a control pin, the selected flash memory 10 receives the 'low' signal through a chip enable pin (CEB Pin) to operate another function. Be prepared to do it.

However, the conventional flash memory having a single chip enable pin should be connected using the number of control pins of the flash memory when the controller is connected to the controller. When the circuit board having the predetermined number of control lines is formed, further memory expansion is performed. It has an impossible problem.

Accordingly, the present invention is to solve the above problems to provide a flash memory that can reduce the number of control pins connected to the controller and the flash memory and easy memory expansion.

Flash memory according to the present invention to achieve the above object is a logic circuit unit for generating a chip enable signal is connected to two or more chip enable pin (CEB Pin), the two or more chip enable pin (CEB Pin); And a ready / busy pin (R / B Pin) and a program control unit connected to the ready / busy pin to control a program operation of a unique number (ID). The logic circuit unit includes a chip enable buffer as many as the chip enable pins, a chip enable store cell as many as the chip enable pins, a comparator as many as the number of the chip enable pins, and a chip enable setting store cell. And one NAND gate, one NOR gate, one inverter, one AND gate, and one exclusive non-hap gate. The program controller includes one NMOS transistor, one NAND gate, and one inverter. Each of the chip enable store cell and the chip enable setting store cell includes one NMOS transistor, one PMOS transistor, one flash memory cell, and three inverters.

1 is a plan view pin-out of a conventional flash memory

2 is a connection diagram of a number of conventional flash memories and a controller;

3 is a plan view of a pin out of a flash memory having three chip enable pins (CEB Pin) according to the present invention.

4 is a circuit diagram of a logic circuit of a flash memory having a chip enable pin (CEB Pin) according to the present invention.

5 is a circuit diagram of a program control unit of a flash memory according to the present invention.

FIG. 6 is a detailed circuit diagram of the first, second and third chip enable store cells of FIG. 4. FIG.

FIG. 7 is a detailed circuit diagram of the chip enable setting store cell of FIG. 4. FIG.

8 is a connection diagram of eight flash memory controllers having three chip enable pins (CEB Pins) according to the present invention.

9 is a connection diagram of a flash memory ready / busy pin (R / B Pin) having three chip enable pins (CEB Pin) according to the present invention.

* Explanation of Signs of Major Parts of Drawings *

1: controller 10: conventional flash memory

100: flash memory 101 according to the present invention: first chip enable buffer

102: second chip enable buffer 103: third chip enable buffer

111: first chip enable store cell 112: second chip enable store cell

113: third chip enable store cell 114: chip enable setting store cell

121: first comparison unit 122: second comparison unit

123: third comparison unit

Hereinafter, a configuration and an operation of a flash memory having three chip enable pins will be described in detail with reference to the accompanying drawings.

3 is a top plan view of a flash memory having three chip enable pins (CEB Pins) according to the present invention.

The flash memory 100 having three chip enable pins (CEB Pin) pin according to the present invention is a first chip enable pin (CEB1 Pin), a second chip enable pin (CEB2 Pin) and a third chip The chip enable signal CE_in is connected to the enable pin CEB3 Pin, the first chip enable pin CEB1 Pin, the second chip enable pin CEB2 Pin, and the third chip enable pin CEB3 Pin. Ready / Busy which is connected to the logic circuit part generating R, B / R Pin and R / B Pin to control the program operation of ID. It comprises a pin (R / B Pin).

4 is a circuit diagram of a logic circuit of a flash memory having three chip enable pins (CEB Pin) according to the present invention.

The logic circuit unit may include first, second and third chip enable buffers 101 and 102 connected to the first, second and third chip enable pins CEB1 Pin and CEB3 Pin, respectively. (103), first, second and third chip enable store cells (111, 112, 113) in which a unique number (ID) is stored, and a chip enable setting store cell (114) in which a chip setting signal is stored. ) And the outputs of the first, second and third chip enable buffers 101, 102, 103 and the first, second and third chip enable store cells 111, 112, and 113. First, second, and third comparison units 121, 122, and 123 for receiving and comparing the unique numbers (IDs) stored in the first and second chips, and the first, second, and third chip enable buffers 101, respectively. First NOR gate (NOR1) that receives the outputs of (102) (103) and a first NAND gate that receives the outputs of the first, second, and third comparison units (121, 122, 123) (NAND1), the output of the first NOR gate (NOR1) and the chip setting scene of the chip enable setting store cell 114 Of the first AND gate AND1, the first inverter INV for inverting the output of the first NOR gate NOR1, the first AND gate AND1, and the first inverter INV. The first exclusive non-haptic gate EXOR1 receives the output and outputs the chip enable signal CE_in.

5 is a circuit diagram of a program control unit of a flash memory according to the present invention.

The program control unit of the flash memory 100 according to the present invention has a drain connected to a ready / busy pin (R / B Pin) and a ready signal indicating a program state of a unique number (ID) is applied to a gate. The source reads the first NMOS transistor NM1 grounded, the second inverter connected to the ready / busy pin R / B pin, INV2, and the program state of the unique number ID. ) And a second NAND gate NAND2 that receives the output of the second inverter INV2 and outputs a unique number program stop signal Stop_Pgm_ID.

FIG. 6 is a detailed circuit diagram of the first, second and third chip enable store cells of FIG. 4.

Each of the first, second, and third chip enable store cells 111, 112, and 113 may include a first PMOS in which an applied voltage VCC is applied to a source and an initial driving power Pwr_up is applied to a gate. The transistor PM1 and the drain thereof are in common with the drain of the first PMOS transistor PM1 and the second NMOS transistor NM2 to which a read / write signal RCL is applied to a gate thereof, and the drain thereof is the second NMOS transistor ( A first flash cell (Flash cell1) which is common to the source of NM2 and whose word line cell enable signal (CE_WL) is applied to the gate from a means for programming a normal cell in the flash memory (100) and the source is grounded; The fourth inverter INV3 having the drain of the first PMOS transistor PM1 connected to the input and the output of the third inverter INV3 are input and the output is fed back to the input of the third inverter INV3. INV4) and the output of the third inverter INV3 I to consist of the fifth inverter (INV5) for outputting a unique number (ID).

FIG. 7 is a detailed circuit diagram of the chip enable setting store cell of FIG. 4.

The chip enable setting store cell 114 includes a second PMOS transistor PM2 to which an applied voltage VCC is applied to a source, and an initial driving power supply Pwr_up is applied to a gate, and a drain thereof is the second PMOS transistor PM2. The third NMOS transistor NM3 having a common drain and a read / write signal RCL applied to its gate, and the drain is common with the source of the third NMOS transistor NM3, and has a gate in the flash memory 100. A second flash cell Flash cell2 to which the word line cell enable setting signal CE_set_WL is applied from the means for programming the normal cell and the source is grounded;

A sixth inverter INV6 having a drain of the second PMOS transistor PM2 connected to an input and an output of the sixth inverter INV6, and the output is fed back to an input of the sixth inverter INV6. 7 is composed of an inverter INV7 and an eighth inverter INV8 which inverts the output of the sixth inverter INV6 and outputs a chip setting signal.

8 is a connection diagram of eight flash memory controllers having three chip enable pins (CEB Pins) according to the present invention.

In the flash memory 100 according to the present invention, each of the first, second, and third chip enable pins (CEB1 Pin) (CEB2 Pin) (CEB3 Pin) is common to three control pins of the controller 11. Is connected.

9 is a connection diagram of a ready / busy pin (R / B Pin) of a flash memory having three chip enable pins (CEB Pin) according to the present invention.

The eight ready / busy pins (R / B Pin) of the flash memory 100 according to the present invention are applied in parallel with the applied voltage VCC through the resistor R.

The operation of an embodiment in which eight flash memory 100 having three chip enable pins according to the present invention is connected to the controller 11 on one substrate will be described in detail.

Referring to FIG. 8, when the controller 11 wants to select and operate a specific flash memory among the eight flash memories 100, the first, second and third chip enable pins (CEB1 Pin) (CEB2 Pin) (CEB3). A specific flash memory is driven by inputting a unique number (ID) previously assigned to the controller in Pin).

In order to select and drive the specific flash memory 100 as described above, since eight flash memories 100 are connected to the control pin in common, the flash memory 100 having three chip enable pins, respectively. ), It is necessary to input ID number.

The ID numbering operation is as follows. (With three chip enable pins)

The controller 11 outputs a 'low' signal through three control pins. The logic circuit unit receiving the 'low' signal through each of the first, second and third chip enable pins (CEB1 Pin) and CEB3 Pin (CEB3 Pin) has a chip enable signal CE having a 'low' level. in) to select all the flash memories 100 and give a command to program specific data in the controller 11.

The 'low' signal is operated through the first, second and third chip enable pins (CEB1 Pin) and CEB2 Pin (CEB3 Pin), respectively, to enable first, second and third chip enable buffers. After input to (101) (102) (103), it is output to the first, second and third comparators 121 (122) (123).

In addition, each of the first, second and third chip enable store cells 'turns on' the second NMOS transistor NM2 by the 'high' level read / write signal RCL, and then enables the word line cell. The first flash cell Flash cell1, which is in an initial state by applying the signal CE_WL, is output to the first, second, and third comparators 121, 122, and 123 having a 'low' level.

The first, second and third comparison units 121, 122, and 123 have the same selection signal of the controller 11 and the outputs of the first, second, and third chip enable store cells are equal to ' Outputs a low signal.

In addition, a 3-bit 'low' signal that selects all the flash memories connected together is output as a 'high' signal through the first NOR gate NOR1.

Thereafter, the chip enable setting store cell 114 turns on the third NMOS transistor NM3 by the 'high' level read / write signal RCL, and then the word line cell enable setting signal CE_set_WL is applied. When applied, the second flash cell Flash cell2 outputs a chip setting signal having a low level in an initial state.

Then, the 'high' signal, which is the output of the first NOR gate NOR1, and the chip setting signal of the 'low' level of the chip enable setting store cell 114 are input to the first AND gate AND1, and thus the 'low' signal. Outputs

The 'high' signal, which is the output of the first NAND gate NAND1, is a 'low' signal inverted through the first inverter INV and the exclusive logical sum together with the output 'low' signal of the first and gate AND1. After the input to the gate EXOR1, the enable signal CE_in having a 'low' level is output to selectively drive all the flash memories 100.

Then all the selected flash memories 100 start a program and the ready / busy pin becomes high. At this time, when one flash memory 100 completes a program, a ready signal is applied as 'high'. The ready signal of the 'high' level 'turns on' the first NMOS transistor NM1 so that all other ready / busy pins (R / B Pin) connected in common are 'low'. At this time, the flash memory 100 having the ready signal 'high' remains selected and the other flash memories 100 are the second inverter INV2 of each of the ready / busy pins. The NAND gate NAND2 outputs the program stop signal Stop_Pgm_ID of the 'high' level to cancel the selected state and initializes all the flash cells that were programmed to the original state.

The flash memory 100 selected in the above process is given a unique number ID by the controller 11. That is, each of the first, second, and third chip enable store cells 111, 112, and 113 is provided with an initial driving power supply Pwr_up at a low level, and thus, the first PMOS transistor PM1. Is turned on, the second NMOS transistor NM2 is turned on by the read / write signal RCL of the high level, and the first flash cell Flash cell1 is turned on by the word line cell enable signal CE_WL. Is a unique number (ID).

In this case, the chip enable setting store cell 114 is also supplied with a word line cell enable setting signal CEB_set_WL to store the setting completion signal of the “high” level in the second flash cell Flash cell2. Then, the 'high' signal, which is the output of the first NOR gate NOR1, and the chip setting signal of the 'high' level of the chip enable setting store cell 114 are input to the first AND gate AND1, and thus the 'high' signal. Therefore, since the output of the exclusive non-haptic gate EXOR1 outputs the 'high' level enable signal CE_in, it does not participate in the subsequent ID program process.

Through the repetition of the ID numbering operation as described above, all eight flash memories 100 are assigned a unique number ID. That is, a unique number (ID) is assigned to a plurality of flash memories by using a difference in time when a specific data is programmed.

When all 8 flash memories 100 are assigned a unique number (ID), the ready / busy pin (R / B Pin) is 'high' even after a certain time after the ID program command is issued from the controller 11. If it is in the state and does not go to 'low', it recognizes that the program to give ID is completed and returns to the normal operation mode.

Each flash memory 100 to which a unique number ID is assigned through the above operation selects a specific unique number ID from the controller 11 and outputs a selection signal through three control pins. The selection signal is first, second and third chip enable buffers 101 and 102 through respective first, second and third chip enable pins (CEB1 Pin) (CEB2 Pin) (CEB3 Pin). After input to the 103, it is output to the first, second and third comparison unit 121, 122, 123.

In addition, each of the first, second and third chip enable store cells 'turns on' the second NMOS transistor NM2 by the 'high' level read / write signal RCL, and then enables the word line cell. The unique number ID stored in the first flash cell Flash cell1 by applying the signal CE_WL is also output to the first, second, and third comparators 121, 122, and 123.

The first, second, and third comparators 121, 122, and 123 compare the selection signal of the controller 11 and the unique number ID to output a 'low' signal if they are equal to each other and to display a 'high' if different. 'Output signal. That is, the output of the first NAND gate NAND1 has a 'high' level only when the stored unique number ID and the selection signal are the same.

In addition, the first NOR gate NOR1 outputs a 'low' signal in all signals other than the 3-bit 'low' signal that is selected as the flash memory.

Thereafter, the chip enable setting store cell 114 turns on the third NMOS transistor NM3 by the 'high' level read / write signal RCL, and then the word line cell enable setting signal CE_set_WL is applied. It is applied to output the chip setting signal of the 'high' level to the second flash cell (Flash cell2).

Then, the 'low' signal, which is the output of the first NOR gate NOR1, and the chip setting signal of the 'high' level of the chip enable setting store cell 114 are input to the first AND gate AND1, and thus the 'low' signal. Outputs

The 'high' signal, which is the output of the first NAND gate NAND1, is a 'low' signal inverted through the first inverter INV and the exclusive logical sum together with the output 'low' signal of the first and gate AND1. After input to the gate EXOR1, the enable signal CE_in of the 'low' level is output to selectively drive the flash memory 100.

It is also possible to program a unique number (ID) of the flash memory 100 according to the present invention before connecting it to the controller 11.

Therefore, the flash memory having a plurality of chip enable pins according to the present invention can reduce the number of control pins of the controller and the control lines on the substrate. If the number of control pins of one controller is n, the flash memory has n number of chip enable pins. The memory can be added or deleted freely within 2n (n is the number of chip enable pins), so the memory can be easily expanded.

Claims (5)

Two or more chip enable pins, A logic circuit unit connected to the at least two chip enable pins to generate a chip enable signal; Ready / Busy Pin (R / B Pin), It is connected to the ready / busy pin and comprises a program control unit for controlling the operation of a plurality of flash memory according to granting a unique number (ID), And a number of the chip enable pins, wherein the number of the chip enable pins is connected to the n control lines and extends to 2 ⁿ flash memories. The logic circuit of claim 1, wherein the logic circuit part Two or more chip enable buffers respectively connected to the two or more chip enable pins; Two chip-enabled store cells storing a unique number (ID) of a flash memory, A chip enable setting store cell in which a chip setting signal is stored; Two comparison units for receiving and comparing the outputs of the two chip enable buffers and the unique numbers stored in the two enable store cells, respectively; A first nor gate receiving the outputs of the two chip enable buffers; A first NAND gate receiving the outputs of the two comparison units; A first AND gate to which an output of the first NOR gate and a chip setting signal of a chip enable setting store cell are input; A first inverter for inverting the output of the first NOR gate; And a first exclusive logic gate configured to receive the output of the first end gate and the first inverter and output a chip enable signal (CE in). The method of claim 1, wherein the program control unit A first NMOS transistor having a drain connected to a ready / busy pin (R / B Pin) and a ready signal indicating a program state of a unique number (ID) to a gate thereof, and a source of which is grounded; A second inverter connected to the ready / busy pin; A flash memory comprising a ready signal indicating a program state of the unique number ID and a second NAND gate receiving a output of a second inverter and outputting a unique number program stop signal Stop_Pgm_ID. The method of claim 2, wherein the plurality of chip enable store cells A first PMOS transistor to which an applied voltage VCC is applied to the source and an initial drive power Pwr_up is applied to the gate; A second NMOS transistor having a drain in common with the drain of the first PMOS transistor and having a read / write signal RCL applied to a gate thereof; A first flash cell Flash cell1 having a drain in common with the source of the second NMOS transistor and having a word line cell enable signal CE_WL applied from a means for programming a normal cell in a flash memory to a gate thereof, and a source of which is grounded; A third inverter having a drain of the first PMOS transistor connected to an input; A fourth inverter receiving an output of the third inverter and outputting the feedback to an input of the third inverter; And a fifth inverter configured to invert the output of the third inverter and output the inverted ID. The method of claim 2, wherein the chip enable setting store cell A second PMOS transistor to which an applied voltage VCC is applied to the source and an initial driving power supply Pwr_up is applied to the gate; A third NMOS transistor having a drain in common with the drain of the second PMOS transistor and having a read / write signal RCL applied to a gate thereof; A drain is common with the source of the third NMOS transistor, and a word line cell enable setting signal CE_set_WL is applied to a gate from a means for programming a normal cell in a flash memory, and a source is grounded with a second flash cell Flash cell2. , A sixth inverter having a drain of the second PMOS transistor connected to an input; A seventh inverter receiving the output of the sixth inverter and the output is fed back to the input of the sixth inverter; And an eighth inverter configured to invert an output of the sixth inverter to output a chip setting signal.