JP3838401B2 - Nonvolatile memory and system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile memory and a system, for example, a flash memory having a prewrite function, a single-chip microcomputer including the flash memory, and a technique particularly effective for improving the reliability thereof.
[0002]
[Prior art]
There is a so-called two-layer gate structure type memory cell that has a floating gate and a control gate, and whose threshold voltage is selectively increased or decreased according to the logical value of retained data. In addition, there is a flash memory whose basic component is a memory array in which such two-layer gate structure type memory cells are arranged in a lattice. Such a flash memory and a central processing unit are mounted on the same semiconductor substrate surface. There is a single-chip microcomputer.
[0003]
On the other hand, the data erase operation in the flash memory is performed in units of, for example, a predetermined block. As one means for improving the erase characteristics of the flash memory, all memory cells to be erased are written before the erase operation. It is becoming common to perform so-called pre-lighting.
[0004]
[Problems to be solved by the invention]
Prior to the present invention, the inventors of the present application have developed a single-chip microcomputer equipped with a flash memory, and have found the following problems in the process. That is, in this microcomputer, data processing by the central processing unit is performed in units of 32 bits, for example, and data is written into the flash memory in units of so-called sectors of 128 bytes, for example.
[0005]
In the microcomputer described above, the generation and verification of the write data to the flash memory, that is, the write confirmation process is performed by software by the central processing unit of the microcomputer, and the process is as shown in FIG. First, write data WD is generated in step S611, and then inverted write data WDI obtained by bit-inverting write data WD is generated in step S612. In the write data WD, the bit to be written is a so-called logic “0”, and in the inverted write data, the bit to be written is a so-called logic “1”. Further, in the flash memory, among the two-layer gate structure type memory cells constituting the memory array, the memory cell in the erased state retains data of logic “1”, for example, having a relatively high threshold voltage. It is assumed that the memory cell in the write state has a relatively low threshold voltage and holds data of logic “0”.
[0006]
In the microcomputer, after the retained data RD is read from the address to be written to the flash memory in the next step S613, the logical product data WDA of the inverted write data WDI and the read data RD is obtained in step S614. Calculated. Also, in step S615, rewrite data WDR is generated to invert the logical product data WDA and rewrite to the specified address, and in step S616, the rewrite data WDR is written to the specified address of the flash memory in the memory array. It is.
[0007]
When the series of write operations is completed, the held data RD is read again from the designated address in step S617, and the logical product data WDA of the inverted write data WDI and the read data RD is calculated in step S618, and then the step By S619, it is determined whether or not the logical product data WDA is all the bits “0”. If all the bits are “0”, the write operation is completed. If any of the bits is “1”, the process returns to step S613, and a series of write operations is repeated. As a result, bit-by-bit writing control is performed, and writing is repeated only for memory cells in the erased state. As a result, meaningless writing is repeated for the memory cell in the writing state, and the threshold voltage is prevented from becoming lower than necessary, and the writing / erasing characteristics of the flash memory can be improved.
[0008]
However, in the above flash memory, for example, after 128 bytes of writing operations in steps S613 to S616 are repeated, the determination operations in steps S617 to S619 are repeated, and after a relatively long time, the operations are performed twice in steps S613 and 617. The reading operation of the designated address is performed. For this reason, when a difference occurs in the logical value of the read data RD obtained by these read operations, an unintentional write operation is performed, and the required write time becomes long. In a so-called fluctuation region that fluctuates to logic “1” or “0”, for example, when the read result in step S613 is logic “0” and the read result in step S617 is logic “1”, an infinite loop state occurs and writing The process does not end indefinitely, which reduces the reliability of the flash memory and hence the microcomputer containing it.
[0009]
In order to deal with this, the inventors of the present application, as illustrated in FIG. 15, replaces the write processing in steps S613 to S616 with the write data WD provided in step S713 as a result of reading the designated address. I thought about how to write in a fixed manner regardless of. However, by using this method, the read operation of the designated address is performed once, and the above problem is solved. However, there are, for example, a 32-bit memory cell as a write unit in an erase state and a write state. When they are mixed, meaningless writing is repeated for memory cells that are already in a writing state, so that writing stress on these memory cells increases. In particular, in the flash memory adopting the pre-write method, the threshold voltage becomes lower than necessary due to the erasing process, and the threshold voltages of the memory cells to be erased become uneven. Decreasing to the erasing characteristic.
[0010]
An object of the present invention is to provide an effective data writing method in a flash memory or the like that adopts a prewrite system. Another object of the present invention is to improve the write / erase characteristics of a flash memory or the like mounted on a single chip microcomputer or the like and to enhance its reliability.
[0011]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0012]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in a nonvolatile memory such as a flash memory mounted on a single chip microcomputer or the like, based on logical product data of read data read from a specified address and bit inverted data of write data to be written to the specified address, The end of the write operation for the specified address is determined, and rewrite data to be rewritten to the specified address that has not been written is generated based on the same logical product data.
[0013]
Alternatively, based on logical product data of write data to be written to a specified address, or write history data obtained by bit-reversing rewrite data for a specified address that has not been written, and read data read from the specified address, The end of the write operation for the specified address is determined, and the rewrite data is generated based on the same logical product data.
[0014]
A series of processing related to the write operation of the flash memory or the like is applied to a flash memory or the like having a prewrite function for aligning information held in all memory cells to be erased before writing data.
[0015]
In the flash memory or the like, based on the logical product data of the write data to be written to the designated address and the bit inverted data of the read data read from the designated address, the absurd writing or dewriting to the already written bits of the designated address is performed. Identify and determine a pleat error.
[0016]
A series of processing relating to the writing operation of the flash memory or the like is realized by software by a central processing unit mounted on a microcomputer or the like.
[0017]
A series of processing related to the writing operation of the flash memory or the like is realized in hardware by a related circuit such as a flash memory.
[0018]
According to the above means, it is possible to determine the end of the write operation and generate rewrite data based on the read data obtained by one read operation, and in particular, the threshold voltage of the memory cell. Can suppress an infinite loop in the fluctuation region, suppress an unintentional increase in the time required for writing to the flash memory or the like, and improve the writing characteristics of the flash memory or the like.
[0019]
In addition, when the end of the write operation is determined based on the logical product data of the write history data and the read data, and the rewrite data is generated, the memory cell once in the write state is erased. However, since rewriting to such a memory cell can be prevented, an infinite loop, particularly when the threshold voltage of the memory cell is in the fluctuation region, is more reliably eliminated, and the time required for writing to the flash memory or the like is reduced. Unintentional increase can be surely prevented, and the writing characteristics of the flash memory or the like can be further improved.
[0020]
By applying a series of processing related to the write operation to a flash memory or the like having a prewrite function, it is possible to suppress the variation in threshold voltage after prewrite of the memory cell to be erased and improve the erase characteristics of the flash memory or the like. Can do.
[0021]
By determining the absurd writing based on the logical product data of the write data and the bit inverted data of the read data, it is possible to identify the absurdity of the write data for the memory cell already in the write state, and the memory to be written The depletion error of the memory cell coupled to the same bit line as the cell can be identified, and the reliability of data held in the flash memory or the like can be improved.
[0022]
A series of processing related to the write operation of the flash memory and the like is realized by software by the central processing unit, so that the central processing unit that is not used for normal processing is used while the flash memory is rewritten. Thus, the hardware amount of the flash memory can be reduced, the chip size of the microcomputer or the like can be reduced, and the cost can be reduced.
[0023]
A series of processing related to the write operation of the flash memory and the like is realized by hardware using a related circuit such as a flash memory, so that a relatively small amount of hardware is added and the central processing unit can be operated at a relatively high speed. During the processing, partial rewriting of the flash memory or the like can be performed.
[0024]
As described above, the reliability of a flash memory and the like and a single chip microcomputer including the same can be improved, and the speed, cost, and efficiency of processing can be improved.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a single chip microcomputer (system) to which the present invention is applied. Based on this figure, the outline and configuration of a single-chip microcomputer (hereinafter simply referred to as a microcomputer) of this embodiment and its features will be described first. The circuit elements constituting each block in FIG. 1 are not particularly limited, but are known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate field effect transistors). It is formed on the surface of a single semiconductor substrate such as single crystal silicon by an integrated circuit manufacturing technique.
[0026]
In FIG. 1, the microcomputer of this embodiment comprises a so-called stored program type central processing unit CPU and a clock generation circuit CPG. Among them, the central processing unit CPU is coupled with a flash memory FROM (nonvolatile memory), a static RAM (SRAM), a direct memory access controller DMAC and a bus controller BUSC via an internal bus IBUS, and is connected to the clock generation circuit CPG. Are coupled to a crystal oscillator XTAL having a predetermined natural vibration number via external terminals XTAL and EXTAL. The microcomputer is further supplied with a power supply voltage VCC and a ground potential VSS, which are main operation power supplies, from an external power supply device via external terminals VCC and VSS, respectively, and to the central processing unit CPU via external terminals STBYB and RESB. The standby signal STBYB (here, a so-called inverted signal that is selectively set to the low level when it is enabled is indicated by adding B to the end of its name, and so on) and the reset signal RESB respectively. Supplied. Note that the power supply voltage VCC as the main operating power supply is, for example, +5 V (volts).
[0027]
The central processing unit CPU of the microcomputer performs a step operation according to a control program stored in the flash memory FROM, performs various arithmetic processes, and controls and controls each part of the microcomputer. In this embodiment, the central processing unit CPU performs a series of processes related to rewriting of the flash memory FROM, which will be described in detail later.
[0028]
The clock generation circuit CPG, together with the external crystal oscillator XTAL, forms a clock signal having a predetermined frequency / phase corresponding to its natural frequency and supplies it to each part of the microcomputer. The flash memory FROM has a memory array in which a two-layer gate structure type memory cell having a control gate and a floating gate is arranged in a lattice as its basic component, and a control program and fixed program required for the step operation of the central processing unit CPU. Stores data etc. Needless to say, since the data held in the flash memory FROM can be rewritten, a system having various functions can be realized with the same microcomputer, and the development period for debugging and the like can be shortened. . The specific configuration, operation, write / erase processing procedure and features of the flash memory FROM will be described later in detail.
[0029]
A static RAM (SRAM) enables relatively high-speed access, and temporarily stores calculation results, control data, and the like of the central processing unit CPU. Further, the direct memory access controller DMAC supports data transfer between, for example, a static RAM (SRAM) and an external device without requiring the intervention of a central processing unit CPU. Further, the bus controller BUSC manages bus access to the internal bus IBUS and performs connection processing between the internal bus IBUS and the peripheral bus PBUS, that is, a device coupled thereto.
[0030]
Further connected to the peripheral bus PBUS of the microcomputer are a serial communication interface SCI, a timer circuit TIM, a digital / analog conversion circuit D / A, an analog / digital conversion circuit A / D, and 11 input / output ports IOPA to IOPK. . Among these, the serial communication interface SCI supports serial data transfer according to a predetermined algorithm with an external serial input / output device coupled to a predetermined port among the corresponding input / output ports IOPA to IOOPK. The timer circuit TIM performs time management according to the clock signal supplied from the clock generation circuit CPG.
[0031]
On the other hand, the digital / analog conversion circuit D / A converts digital data generated by the central processing unit CPU or the like into a predetermined analog signal and transmits it to an external input / output device. The analog / digital conversion circuit A / D converts an analog input signal input from, for example, various external sensors into a digital signal of a predetermined bit and transmits it to the central processing unit CPU or the like. Further, the input / output ports IOPIOPA to IOPK function as an interface circuit that exchanges signals between each part of the microcomputer and various devices provided outside.
[0032]
As described above, the flash memory FROM is used for storing control programs, fixed data, and the like, and rewriting thereof is mainly performed by software by the central processing unit CPU. In this embodiment, in particular, prior to the erase operation of the flash memory FROM, prewrite is performed to align all memory cells to be erased in a write state, and at the time of write, read data read from a specified address and The write operation end determination is performed based on the logical product data of the write data and the bit inverted data, and the rewrite data for the designated address that has not been written is generated based on the same logical product data, or The end of the write operation is determined based on the logical product data of the write history data and the read data obtained by bit inversion of the write data or the rewrite data, and the rewrite data of the rewrite data is determined based on the same logical product data. Generation occurs.
[0033]
As a result, the reliability of the flash memory FROM and thus the microcomputer including the flash memory FROM can be improved, and the speed, cost, and efficiency of processing can be improved. These will be described in detail later.
[0034]
FIG. 2 is a block diagram showing an embodiment of a flash memory FROM included in the microcomputer of FIG. FIG. 3 shows a partial circuit diagram of an embodiment of the memory array MARY and its peripheral part included in the flash memory FROM of FIG. Based on these drawings, the specific configuration and operation of the flash memory FROM included in the microcomputer of this embodiment, and its features will be described. FIG. 3 illustrates representative portions of the write circuit WC, the sense amplifier SA, and the column latch CL, but the circuit elements constituting each portion are not all illustrated. In the following circuit diagrams, MOSFETs with an arrow attached to the channel (back gate) portion are P-channel type, and are distinguished from N-channel MOSFETs without an arrow.
[0035]
In FIG. 2, the flash memory FROM according to this embodiment has a memory array MARY, which occupies most of the required layout area, as its basic component. The flash memory FROM has a control buffer CB coupled to the control bus CBUS of the internal bus IBUS, and further generates a memory controller MC that receives the output signal of the control buffer CB, and an internal voltage that receives the power supply voltage VCC and the ground potential VSS. A circuit VG.
[0036]
Among them, the control buffer CB and the memory controller MC selectively form various internal control signals (not shown) on the basis of various activation control signals supplied via the control bus CBUS of the internal bus IBUS. Supply to each part. The internal voltage generation circuit VG includes a plurality of voltage generation circuits that are selectively operated in accordance with a voltage control signal VCS supplied from a control circuit (not shown) of the microcomputer, and writes, erases, and reads the flash memory FROM. Various internal voltages required for operation are generated.
[0037]
On the other hand, the memory array MARY is not particularly limited, but is a so-called NOR type array, and as shown in FIG. 3, m + 1 arranged in parallel to the horizontal direction in the drawing, that is, substantially 1,024. It includes word lines W0 to Wm and n + 1, that is, substantially 1,024 bit lines B0 to Bn arranged in parallel in the vertical direction. At the intersections of these word lines and bit lines, 1,024 × 1,024, that is, 1,048,576 two-layer gate structure type memory cells MC having floating gates and control gates are arranged in a grid. As a result, the flash memory FROM has a so-called 1 megabit storage capacity.
[0038]
The control gates of n + 1 memory cells MC arranged in the same row of memory array MARY are commonly coupled to corresponding word lines W0 to Wm, respectively, and their sources are n + 1 memory cells MC arranged in adjacent rows. Are commonly coupled to the corresponding source lines S0 to Sp. The drains of m + 1 memory cells MC arranged in the same column of memory array MARY are commonly coupled to corresponding bit lines B0 to Bn. Note that the number p + 1 of the source lines S0 to Sp is smaller than the number m + 1 of the word lines W0 to Wm.
p + 1 = (m + 1) / 2
Needless to say, the relationship
[0039]
In this embodiment, each of the two-layer gate structure type memory cells MC constituting the memory array MARY is not particularly limited. However, when it is in an erased state, it is assumed to hold data of so-called logic “1”. When it is in a write state, so-called logic “0” data is held. In the erase operation of the memory cell MC, a positive potential such as + 9V is applied to the control gate, that is, the corresponding word lines W0 to Wm, and the source, that is, the corresponding source lines S0 to Sp, such as −9V. A negative potential is applied and electrons are injected from the source side into the floating gate, and the write operation of the memory cell MC is performed by applying a positive potential such as +6 V to the drain, that is, the corresponding bit lines B0 to Bn. This is performed by applying a negative potential such as −9 V to the control gate, that is, the corresponding word lines W0 to Wm, and extracting electrons accumulated in the floating gate to the drain side.
[0040]
Thereby, the threshold voltage of the memory cell MC is set to a relatively high value exceeding, for example, +2.5 V when it is in the erased state, and is relatively low lower than +2.5 V when it is in the written state. Value. Therefore, during the read operation of the retained data, the corresponding word lines W0 to Wm are alternatively set to a selection level such as +2.5 V, for example, so that the memory cell MC in the erased state is turned off and compared. A relatively small read current is supplied, and the memory cell MC in the write state is turned on to pass a relatively large read current.
[0041]
As shown in FIG. 2, word lines W0 to Wm constituting memory array MARY are coupled to X address decoder XD on the left side, and source lines S0 to Sp are connected to source voltage control circuit SC on the right side. Combined. Although not particularly limited, the X address decoder XD is supplied with 10-bit internal X address signals X0 to X9 from the address buffer AB, and is necessary for selecting or deselecting the word lines W0 to Wm from the internal voltage generation circuit VG. Various internal voltages are supplied. The internal X address signals X0 to X9 are also supplied to the source voltage control circuit SC, and the source voltage control circuit SC further includes various types necessary for selecting or deselecting the source lines S0 to Sp from the internal voltage generation circuit VG. The internal voltage is supplied.
[0042]
The X address decoder XD decodes the internal X address signals X0 to X9 supplied from the address buffer AB when the flash memory FROM is selected, and outputs the corresponding bits of the word lines W0 to Wm of the memory array MARY. A predetermined selection or non-selection level is selectively set. Further, when the flash memory FROM is selected, the source voltage control circuit SC similarly decodes the internal X address signals X0 to X9 and selectively selects the corresponding bits of the source lines S0 to Sp of the memory array MARY. A predetermined selection or non-selection level is set.
[0043]
Although not particularly limited, when the flash memory FROM is set to the write mode, the selection level of the word lines W0 to Wm is, for example, −9V as described above, and the non-selection level is, for example, the power supply voltage VCC, for example, + 5V. Is done. When the flash memory FROM is set to the erase mode, the selection level of the word lines W0 to Wm is, for example, + 9V as described above, and the non-selection level is, for example, the ground potential VSS. Furthermore, when the flash memory FROM is set to the read mode, the selection level of the word lines W0 to Wm is, for example, +2.5 V as described above, and the non-selection level is the ground potential VSS.
[0044]
Note that the write mode of the flash memory FROM includes a read operation for verifying the write state, that is, a verify operation. The selection level of the word lines W0 to Wm during the verify operation is the selection level during the normal read operation. For example, + 4V, which is slightly higher than + 2.5V.
[0045]
On the other hand, when the flash memory FROM is set to the write mode, the source lines S0 to Sp in the selected state are in a so-called open state, and the non-selected level is set to the ground potential VSS. When the flash memory FROM is set to the erase mode, the selection level of the source lines S0 to Sp is set to -9V, for example, and the non-selection level is set to the ground potential VSS. When the flash memory FROM is set to the read mode, all the source lines S0 to Sp are set to the ground potential VSS.
[0046]
Next, the bit lines B0 to Bn constituting the memory array MARY are coupled to the corresponding unit circuits of the write circuit WC and the sense amplifier SA below. Each unit circuit of the write circuit WC and the sense amplifier SA is coupled to the corresponding unit circuit of the column latch CL on the other side, and 32 unit circuits on the other side are connected via the Y gate circuit YG. Each is selectively connected to a corresponding unit circuit of the data input / output circuit IO. Each unit circuit of data input / output circuit IO is coupled to a corresponding unit circuit of data buffer DB on the other side, and this data buffer DB is coupled to a corresponding bit on data bus DBUS of internal bus IBUS on the other side. The
[0047]
The Y gate circuit YG is supplied with q + 1 bits, that is, substantially 128-bit bit line selection signals YS0 to YSq from the Y address decoder YD, and the Y address decoder YD receives the 7-bit internal Y address signals Y0 to Y0 from the address buffer AB. Y6 is supplied. The address buffer AB is supplied with 17-bit address signals A0 to A16 via the address bus ABUS of the internal bus IBUS.
[0048]
The address buffer AB takes in and holds the address signals A0 to A16 supplied via the address bus ABUS of the internal bus IBUS. Then, 10 bits are supplied to the X address decoder XD and the source voltage control circuit SC as internal X address signals X0 to X9, and the remaining 7 bits are supplied to the Y address decoder YD as internal Y address signals Y0 to Y6. To do.
[0049]
The Y address decoder YD decodes the internal Y address signals Y0 to Y6 supplied from the address buffer AB, and alternatively selects the corresponding bits of the bit line selection signals YS0 to YSq for the Y gate circuit YG to a predetermined selection level. And
[0050]
The Y gate circuit YG includes n + 1, that is, 1,024 switch MOSFETs provided corresponding to each unit circuit of the column latch CL. These switch MOSFETs are selectively turned on 32 by selectively turning the corresponding bits of the bit line selection signals YS0 to YSq supplied from the Y address decoder YD to the high level, and the column latch CL A connection state is established between one input / output node of each unit circuit and a corresponding unit circuit of the data input / output circuit IO.
[0051]
On the other hand, the data buffer DB and the data input / output circuit IO sequentially fetch 32-bit write data supplied via the data bus DBUS of the internal bus IBUS when the flash memory FROM is selected in the write mode, and Y The data is transmitted to 32 designated unit circuits of the column latch CL via the gate circuit YG. The write data taken into each unit circuit of the column latch CL is 1,024 pieces of 1,024 bits coupled to the selected word line of the memory array MARY via the write circuit WC when 128 bytes, that is, 1,024 bits are accumulated. Data are simultaneously written to the memory cells MC. When the flash memory FROM is set to the read mode, the data bus DBUS and the data input / output circuit IO output the read data output from the selected memory cell MC of the memory array MARY and held in each unit circuit of the column latch CL. The data is selectively extracted 32 bits at a time and output to the access device via the data bus DBUS of the internal bus IBUS.
[0052]
As described above, the data input / output operation for the flash memory FROM of this embodiment is performed in units of 32 bits, that is, 4 bytes, but the substantial write and read operations for the memory array MARY are 128 bytes, that is, 1,024. This is done in units of bits. Therefore, word lines W0 to Wm of memory array MARY are alternatively designated according to 10-bit internal X address signals X0 to X9, and bit lines B0 to Bn are 7-bit internal Y address signals Y0 to Y6. As a result, 32 bits are selectively designated.
[0053]
Here, the column latch CL includes n + 1, that is, substantially 1,024 unit circuits provided corresponding to the bit lines B0 to Bn of the memory array MARY, and each of these unit circuits is not particularly limited. As illustrated in FIG. 3, it includes a latch circuit L1 in which a pair of inverters V1 and V2 are cross-coupled, and two N-channel type switch MOSFETs N1 and N2. Among these, the input / output node below the latch circuit L1 of each unit circuit of the column latch CL is coupled to the corresponding data input / output lines D0 to Dn, that is, the data input / output circuit IO via the switch MOSFET N1. The input / output node above it is coupled to the input terminal of the corresponding inverter V3 of the write circuit WC, which will be described later, and coupled to the inverting output node of the corresponding unit sense amplifier UA of the sense amplifier SA via the switch MOSFET N2. Is done. A latch control signal LC1 is commonly supplied from the memory controller MC to the gate of the switch MOSFET N1, and a latch control signal LC2 is commonly supplied to the gate of the switch MOSFET N2.
[0054]
The latch control signal LC1 is normally set to a low level such as the ground potential VSS, and is selectively set to a high level such as the power supply voltage VCC at a predetermined timing when the flash memory FROM is selected in the write mode. The The latch control signal LC2 is normally set to a low level such as the ground potential VSS, and is selectively set to a high level such as the power supply voltage VCC at a predetermined timing when the flash memory FROM is selected in the read mode. The
[0055]
As described above, when the flash memory FROM is selected in the write mode, the column latch CL receives the data bus DBUS, the data buffer DB, the data input / output circuit IO, the Y gate circuit YG of the internal bus IBUS from the access device. Write data is supplied in units of 32 bits via the data input / output lines D0 to Dn. These write data are sequentially fetched and held in the 32 latch circuits L1 corresponding to the column latch CL via the switch MOSFET N2 which is turned on in response to the high level of the latch control signal LC1. Then, at the time when the capture of 128 bytes of write data is completed, the data is transmitted to the memory array MARY via the write circuit WC and is simultaneously transmitted to n + 1, that is, substantially 1,024 memory cells MC coupled to the selected word line. Is written to.
[0056]
On the other hand, when the flash memory FROM is selected in the read mode, the column latch CL receives the inverted output signal of the unit sense amplifier UA, that is, the inverted read data, from 1,024 unit circuits of the sense amplifier SA described later. Supplied. These inverted read data are simultaneously fetched and held in the latch circuit L1 of each unit circuit of the column latch CL via the switch MOSFET N2 that is turned on in response to the high level of the latch control signal LC2. Then, it is inverted by the inverter V2 of the corresponding latch circuit L1 to become non-inverted read data, and from the data input / output lines D0 to Dn, the Y gate circuit YG, the data input / output circuit IO, the data buffer DB and the data bus of the internal bus IBUS. The data is output to the access device in units of 32 bits via DBUS.
[0057]
Next, the write circuit WC includes n + 1, that is, 1,024 unit circuits provided corresponding to the bit lines B0 to Bn of the memory array MARY, and each of these unit circuits is not particularly limited. 3 includes two P-channel MOSFETs P1 and P2, and an inverter V3 that uses a relatively high internal voltage VPP such as + 6V as an operation power supply. The source of MOSFET P1 constituting each unit circuit of write circuit WC is coupled to internal voltage supply point VPP, and its drain is coupled to corresponding bit lines B0 to Bn of memory array MARY via MOSFET P2. Further, the gate of MOSFET P1 is coupled to the output terminal of the corresponding inverter V3, and the input terminal of inverter V3 is coupled to the output terminal of inverter V1 constituting the corresponding latch circuit L1 of column latch CL. A write control signal WP is commonly supplied from the memory controller MC to the gate of the MOSFET P2 of each unit circuit of the write circuit WC.
[0058]
The write control signal WP is normally set to a high level such as the internal voltage VPP, and is selectively set to a low level such as the ground potential VSS at a predetermined timing when the flash memory FROM is selected in the write mode. The
[0059]
Thereby, when the flash memory FROM is selected in the write mode, the MOSFETs P2 constituting each unit circuit of the write circuit WC are selectively turned on in response to the low level of the write control signal WP. At this time, the MOSFET P1 of each unit circuit is held by the corresponding latch circuit L1 of the column latch CL, in other words, on condition that the output signal of the corresponding inverter V3 is at a low level such as the ground potential VSS. When the write data is set to logic “0” and the output signal of the inverter V1 is set to the high level, it is selectively turned on, and the corresponding bit lines B0 to Bn of the memory array MARY are set to the internal voltage VPP, that is, + 6V. A high selection level.
[0060]
Needless to say, when the write data held by the corresponding latch circuit L1 of the column latch CL is logic "1" and the output signal of the corresponding inverter V1 is low level, the output signal of the inverter V3 is the internal voltage VPP. It becomes such a high level. For this reason, the MOSFET P1 of each unit circuit of the write circuit WC is turned off, and the corresponding bit lines B0 to Bn of the memory array MARY are set to a non-selection level such as the ground potential VSS through a path not shown.
[0061]
When the flash memory FROM is selected in the write mode, the word lines W0 to Wm of the memory array MARY are alternatively set to a selection level such as −9V as described above, and the source lines S0 to Sp are Opened. At this time, in n + 1 memory cells MC coupled to the selected word line of the memory array MARY, writing is selectively performed on condition that the corresponding bit lines B0 to Bn are set to a selection level such as + 6V. Electrons accumulated in the floating gate are selectively extracted to the drain side, and the threshold voltage is lowered.
[0062]
Next, the sense amplifier SA includes n + 1, that is, substantially 1,024 unit circuits provided corresponding to the bit lines B0 to Bn of the memory array MARY. Each of these unit circuits is not particularly limited. As shown in FIG. 3, it includes one unit sense amplifier UA and a P-channel type switch MOSFET P3. The input node of the unit sense amplifier UA constituting each unit circuit is coupled to the corresponding bit lines B0 to Bn of the memory array MARY via the switch MOSFET P3, and the inverted output node thereof is connected via the N channel MOSFET N2 of the column latch CL. Are coupled to the input / output node above the corresponding latch circuit L1. A read control signal RC is commonly supplied from the memory controller MC to the gates of the MOSFETs P3 constituting each unit circuit of the sense amplifier SA.
[0063]
The read control signal RC is set to a high level such as the normal power supply voltage VCC, and is selectively set to a low level such as the ground potential VSS at a predetermined timing when the flash memory FROM is selected in the read mode. The
[0064]
When the flash memory FROM is selected in the read mode, the word lines W0 to Wm of the memory array MARY are alternatively set to a selection level such as +2.5 V as described above, and the source lines S0 to Sp. Are all at a low level like the ground potential VSS. In addition, the bit lines B0 to Bn of the memory array MARY are precharged simultaneously to a high level such as the power supply voltage VCC by a precharge circuit (not shown) of the sense amplifier SA at the beginning of the read operation. The precharge levels of these bit lines B0 to Bn are selective on condition that the memory cells MC arranged at the corresponding intersections with the selected word line are in the write state and their threshold voltages are relatively low. It is pulled out and falls.
[0065]
The selective lowering of the bit lines B0 to Bn is sensed and amplified by the unit sense amplifier UA of the corresponding unit circuit of the sense amplifier SA, and in response to this, the inverted read data at the inverted output node of the unit sense amplifier UA is selected. High level. These inverted read data are received by the corresponding latch circuit L1 of the column latch CL in response to the high level of the latch control signal LC2, are inverted to become non-inverted read data, and are selectively output bit by bit.
[0066]
By the way, the two-layer gate structure type memory cells MC constituting the memory array MARY exhibit a relatively large variation in the write / erase characteristics. Therefore, the above-described 128-byte unit write and block-unit erase operations are performed as write operations. Or, while confirming the change in the data held in the memory cell MC after the erase operation, that is, the memory cell MC that has been in the erased state of logic “1” changes to the write state of logic “0”, or the write of logic “0” The process is repeated while confirming whether the memory cell MC in the state has changed to the erased state of logic “1”. In addition, in the flash memory FROM of this embodiment, a prewrite system is adopted in which all memory cells MC to be erased are aligned in a write state prior to the erase operation. In this embodiment, the control necessary for the write / erase operation of the flash memory FROM is mainly performed by software by the central processing unit CPU as described above, and has several features. Will be described in detail.
[0067]
FIG. 4 shows a basic flow diagram of the first embodiment of the microcomputer of FIG. 1 when writing to the flash memory, and FIG. 5 shows an embodiment for explaining the operation when writing the flash memory of FIG. An example operation conceptual diagram is shown. FIG. 6 shows a basic flow diagram of an embodiment of the absurd write determination process at the time of writing to the flash memory in FIG. 4, and FIG. 7 illustrates the operation at the absurd write determination process in FIG. The operation | movement conceptual diagram of one Example is shown. Further, FIG. 8 shows a processing flow chart of an embodiment of the central processing unit of the microcomputer taking the basic flow of FIG. Based on these drawings, the specific operation and characteristics of the microcomputer of this embodiment when writing to the flash memory will be described. In the microcomputer of this embodiment, as described above, data processing is performed in units of 32 bits, that is, 4 bytes. However, in the following operation conceptual diagram, only 8 bits, that is, 1 byte is exemplified.
[0068]
In FIG. 4, the write operation in the flash memory FROM of this embodiment starts from the generation process of the write data WD in step S111. As described above, when the two-layer gate structure type memory cell MC constituting the memory array MARY of the flash memory FROM is in the erased state, as shown in the uppermost part of FIG. It is supposed to hold data. Further, as described above, the substantial write operation in the flash memory FROM is carried out in units of substantially 1,024 bits, that is, in units of 128 bytes, but the write data WD is generated in units of 32 bits, and of these, it becomes a write target. As illustrated in the second row of FIG. 5, data of logic “0” is selectively assigned to the bits. Needless to say, logic “1” data is assigned to bits that are not to be written at the specified address, that is, bits that are to remain in the erased state, and write data WD has logic “1” and “0”. There are many cases where data is mixed.
[0069]
The write data WD generated in step S111 is logically inverted for each bit in step S112 to generate bit inverted data, that is, inverted write data WDI. In the inverted write data WDI, as illustrated in the third row of FIG. 5, the bit to be written to the designated address is set to logic “1”, and the bit not to be written to is set to logic “0”. .
[0070]
When the generation of the write data WD and the inverted write data WDI is completed, first, the retained data RD at the designated address is read out in step S113, and then the absurd writing determination process is performed in step S114. As described above, each bit of the read data RD read from the designated address is set to logic “1” when the corresponding memory cell MC is still in the erased state, and is set to logic “0” when the corresponding memory cell MC is already in the written state. . Therefore, all the bits of the read data RD obtained by the first read after erasure are set to logic “1” as illustrated in the fourth row of FIG. The necessity and effect of the absurd writing determination process in step S114 will be described later in detail.
[0071]
If no abnormality is detected by the absurdity determination process in step S114 and the determination result is yes, in step S115, a logical product is taken for each bit of the inverted write data WDI and the read data RD, and logical product data WDA is generated. . Needless to say, each bit of the logical product data WDA is selectively set to logic “1” on condition that the corresponding bits of the inverted write data WDI and the read data RD are both logic “1”. Logic “0” is set. Therefore, the logical product data WDA generated based on the first read data RD after erasure and the inverted write data WDI has each bit set to the inverted write data WDI as illustrated in the fifth row of FIG. Have the same logical value as the corresponding bit.
[0072]
In the logical product data WDA generated in step S115, whether all the bits have become logic “0” in step S116, that is, whether all the bits to be written have changed to logic “0” after the write operation is completed. Get a judgment of whether. As a result, when all the bits of the logical product data WDA change to logic “0”, the write operation for the designated address is completed, and the process proceeds to another process, and any one of the bits remains logic “1”. If there is, in step S117, the logical product data WDA is bit-inverted, and rewrite data WDR to be rewritten to the specified address is generated. The rewrite data WDR is written to the designated address in step S118, and thereafter, the process returns to step S113 to form a processing loop. Note that the rewrite data WDR generated based on the first read data RD and the logical product data WDA after erasure is the write data WD itself as illustrated in the sixth row of FIG.
[0073]
At the designated address of the memory array MARY for which the write operation in step S118 has been completed, the logical values of the first to second bits and the fourth to eighth bits are rewritten as illustrated in the seventh row of FIG. Although the logic value is changed according to the corresponding bit of the data WDR, the threshold voltage of the corresponding memory cell MC is not sufficiently lowered, and the third bit remains at the logic “1”, that is, the erased state. is there. Therefore, in the read operation in step S113 in the second loop, as illustrated in the eighth stage of FIG. 5, the third bit of the read data RD is also “1”, and the new logical product data obtained in step S115. As illustrated in the ninth row of FIG. 5, only the third bit of the WDA is logic “1”.
[0074]
As a result, the rewrite data WDR generated in step S117 of the second loop is, as exemplified in the 10th stage of FIG. 5, only the third bit is logic “0”, and the other bits are logic “0”. 1 ". The rewrite data WDR is written again to the designated address in step S118. As a result, the third bit of the designated address changes to logic “0” as illustrated in the eleventh stage of FIG. All bits coincide with the write data WD.
[0075]
The retained data at the specified address is read as read data RD in step S113 in the third loop, and then logically ANDed with the inverted write data WDI in step S115 to become logical product data WDA. As is clear from the above description, the logical product data WDA generated by the step S115 in the third loop is that all bits are logical “0” as illustrated in the 13th stage of FIG. The condition of step S116 is satisfied, and the writing is completed.
[0076]
As described above, in the microcomputer of this embodiment, the read data RD read from the designated address of the flash memory FROM in step S113 is used to generate the logical product data WDA with the inverted write data WDI in step S115. The logical product data WDA is used for determining the end of the write operation in step S116 and also used for generating the rewrite data WDR in step S117. In other words, in this embodiment, the end of the write operation is determined based on the read data RD obtained by one read operation in step S113 and the logical product data WDA with the inverted write data WDI, and the rewrite data is determined. In particular, even if the threshold voltage of the memory cell is in the fluctuation region and there is a bit whose logical value changes every time a read operation is performed, the occurrence of rewrite accompanying this is suppressed. In addition, the occurrence of an infinite loop due to the repetition of this can be suppressed.
[0077]
As a result, it is possible to prevent the time required for writing to the flash memory FROM from unintentionally increasing, and to improve the writing characteristics, and to improve the reliability of the flash memory FROM and thus the microcomputer in which the flash memory FROM is mounted. And efficiency of processing can be achieved.
[0078]
By the way, in the absurd writing determination process performed as step S114 in FIG. 4, although not particularly limited, first, as shown in the dotted frame in FIG. 6, the read data RD is bit-inverted and the bit inversion is performed in step S141. After the data, that is, the inverted read data RDI is generated, the logical product of the write data WD and the inverted read data RDI is obtained in step S142 to generate the logical product data RDA. The logical product data RDA is determined in step S143 as to whether or not all bits are logic “0”. If all the bits are logic “0”, it is determined that there is no abnormality and the process proceeds to step S115 and subsequent steps. To do. However, if any bit of the logical product data RDA is logical “1” in step S143, it is regarded that an abnormality has occurred, the write operation is interrupted, and the process proceeds to error processing.
[0079]
That is, each bit of the logical product data RDA obtained as a result of the processing in step S142 has the corresponding bit of the designated address already in the written state and the corresponding bit of the read data RD is logical “0”. When the corresponding bit of the write data WD is logic “1” corresponding to the erased state, that is, when absurd writing is designated, the logic “1” is selectively set. Although no absurd writing has been specified, as shown in FIG. 7, for example, in step S113 in the third loop, the read result of the second bit of the specified address is arranged in the same column, that is, in the same bit line. Even when the bit is changed to logic "0" due to the influence of other bits in the combined depletion error state, it is selectively set to logic "1".
[0080]
From the above, in the microcomputer and the flash memory FROM of this embodiment, prior to the writing of the specified address, the absurdity of the write data WD is identified, the writing operation is interrupted, and the normality of the retained data is ensured. In addition, even after the write operation to the designated address is started, it is possible to detect a depletion error of another memory cell arranged in the same column as the designated memory cell. The reliability of the microcomputer equipped with can be further increased.
[0081]
In the microcomputer of this embodiment, as described above, the flash memory FROM is actually written in units of 128-byte sectors, and the above-described series of processing relating to the designated sector write operation is performed mainly. The central processing unit CPU performs the processing in software. For this reason, the central processing unit CPU proceeds with specific processing according to the procedure illustrated in FIG. 8, and performs a writing operation along the basic flow of FIG.
[0082]
That is, the central processing unit CPU first edits the 128-byte sector write data WDS to be written to the designated address, that is, the designated sector in step S211, and inverts and reverses the sector write data WDS in the next step S212. Sector write data WDIS is generated. In step S213, the holding data RDS of the designated sector is read out in units of sectors, and in step S214, absurd writing is determined based on the sector read data RDS and the sector write data WDS. The generation of the sector write data WDS and the inverted sector write data WDIS, the reading of the sector read data RDS, and the absurd write determination processing in steps S211 to S214 are actually 32 bits, which is the arithmetic processing unit of the central processing unit CPU. Although it is repeated 32 times in units of 4 bytes, it is shown in a simplified manner.
[0083]
The central processing unit CPU, which has successfully completed the absurd write determination process in step S214, next inputs 4B, that is, 4 bytes of the inverted sector write data WDIS to the register REG1 in step S215, and then reads the sector read data in step S216. The corresponding 4 bytes of RDS are input to the register REG2. In step S217, the contents of the registers REG1 and REG2, that is, the corresponding 4-byte logical product of the inverted sector write data WDIS and the sector read data RDS are obtained, and the processing result, that is, the logical product data is input to the register REG3. In step S218, it is determined whether or not the contents of the register REG3, that is, the logical product data, is all-bit logic “0”.
[0084]
As a result, when the contents of the register REG3, that is, any bit of the logical product data is logical “1”, the central processing unit CPU performs the sector rewrite by inverting the content of the register REG3, that is, the logical product data in step S222. After generating 4 bytes of data WDRS, it is determined in step S223 whether processing for 1 sector, that is, 128 bytes has been completed. If the processing for one sector has not been completed yet, the central processing unit CPU returns to step S214 to repeat the processing for the next four bytes, and if the processing for one sector has been completed, step S224 is performed. Thus, after confirming whether the number of times of writing related to the sector has exceeded the predetermined value, the edited rewrite data WDRS for one sector is written to the designated sector of the flash memory FROM in step S225. In step S224, when the write count exceeds a predetermined value, the central processing unit CPU performs a predetermined error process.
[0085]
On the other hand, when the content of the register REG3, that is, the logical product data becomes all-bit logic “0” in step S218, the central processing unit CPU writes logic “0” to the corresponding bit of the register REG4 in step S219. Thereafter, in step S220, it is determined whether the processing for one sector, that is, 128 bytes has been completed. If the processing for one sector has not been completed yet, the process returns to step S214 to repeat the processing for the next four bytes. If the processing for one sector has been completed, all bits of the register REG4 are obtained in step S221. Is determined to be logic “0”.
[0086]
The register REG4 has 32 bits each corresponding to 4 bytes of the sector write data WDS and the sector read data RDS, and the central processing unit CPU registers the register in advance when the write operation for one sector is started. Write logic “1” to all bits of REG4. Further, as described above, each bit of the register REG4 includes the contents of the register REG3, that is, all the bits of 4-byte AND data corresponding to the inverted sector write data WDIS and the sector read data RDS are logical “0”, that is, the sector When the end of the write operation for the corresponding 4 bytes of the write data WDS is confirmed, each is rewritten to logic “0”. Therefore, in step S221, all the bits of the register REG4 becoming logic “0” indicates that all writing relating to the 128-byte sector write data WDS has been completed.
[0087]
Accordingly, in step S221, the central processing unit CPU that determines that any bit of the register REG4 is logic “1” moves to step S224 and writes the sector rewrite data WDRS. When it is determined that the bit is logic “0”, the process related to writing the sector write data WDS to the designated sector is terminated.
[0088]
As described above, in the microcomputer according to the present embodiment, a series of processes related to the writing operation of the flash memory FROM is performed mainly by software by the central processing unit CPU. At first glance, an increase in processing load on the central processing unit CPU is noticed. It becomes. However, as described above, the flash memory FROM is for storing a program related to the operation control of the central processing unit CPU, and the fact that the flash memory FROM is rewritten means that the central processing unit CPU and this are rewritten. This indicates that the normal processing inherent to the system including the system is in an inexecutable or unnecessary state. Therefore, the central processing unit CPU can be involved in a series of processes relating to the rewriting operation of the flash memory FROM, on the condition that the control program relating to the rewriting of the flash memory FROM remains in, for example, the static RAM.
[0089]
A series of processing relating to the writing operation of the flash memory FROM is mainly performed by software by the central processing unit CPU, so that the hardware relating to the writing operation of the flash memory FROM is reduced, and the required layout area and the chip size of the microcomputer are reduced. To reduce the cost of the microcomputer. In particular, during the development period of the microcomputer, the writing procedure can be arbitrarily modified and changed by rewriting the flash memory FROM, and thus the development period of the flash memory FROM and thus the microcomputer can be shortened. .
[0090]
FIG. 9 shows a basic flowchart of the second embodiment at the time of writing to the flash memory of the microcomputer of FIG. FIG. 10 shows an operation conceptual diagram of an embodiment for explaining the operation at the time of flash memory writing in FIG. 9, and FIG. 11 shows an embodiment of the central processing unit taking the basic flow of FIG. An example process flow diagram is shown. Since this embodiment basically follows the embodiment shown in FIGS. 4 to 8, only the portions different from this will be described.
[0091]
In FIG. 9, the write data WD generated at step S311 is bit-inverted to become inverted write data WDI at step S312, and this inverted write data WDI is further written with the same logical value at step S313 as write history data WDH. It becomes. Needless to say, the initial write history data WDH generated in step S313 is the inverted write data WDI itself as illustrated in the third row of FIG.
[0092]
Next, the read data RD read from the designated address of the flash memory FROM in step S314 is subjected to the logical product with the write history data WDH in step S316 after receiving the absurd write determination in step S315. The logical product data WDA. The logical product data WDA becomes new write history data WDH in step S317. As described above, the initial write history data WDH is the inverted write data WDI itself, and the first logical product data WDA is As illustrated in the fifth row in FIG. 10, the inverted write data WDI itself is used, and therefore each bit of the new write history data WDH generated in step S317 is also illustrated in the sixth row in FIG. Thus, the logical value up to that point is retained as it is.
[0093]
The logical product data WDA generated in step S316 is determined in step S318 whether all the bits have become logic “0”, that is, all the bits to be written are changed to logic “0” after the write operation is completed. Received a determination of whether or not As a result, when all the bits of the logical product data WDA have changed to logic “0”, it is determined that the write operation for the designated address has been completed, and the process proceeds to another process. However, if any of the bits is still logic “1”, the rewrite data WDR is generated by inverting the logical product data WDA in step S319, and then the rewrite data for the designated address is generated in step S320. WDR writing is performed, and the process returns to step S314.
[0094]
At the specified address of the memory array MARY for which the write operation in step S320 has been completed, as illustrated in the eighth row of FIG. 10, only the third bit has not been written, and the logical “1”, that is, the erase state In the second read operation in step S314 in the loop, the third bit of the read data RD becomes logic “1” as illustrated in the ninth row of FIG. For this reason, the new logical product data WDA obtained in step S316 is, as exemplified in the 10th stage of FIG. 10, only the third bit becomes logic “1”, and the new write history data obtained in step S317. As illustrated in the eleventh stage of FIG. 10, only the third bit of the WDH is also a logic “1”.
[0095]
As a result, the rewrite data WDR generated in step S319 in the second loop is, as illustrated in the twelfth stage of FIG. 10, only the third bit is logic “0”, and the other bits are logic “0”. 1 ". The rewrite data WDR is written to the designated address again in step S320, and as a result, the third bit of the designated address changes to logic “0” as illustrated in the 13th stage of FIG. The bit matches the write data WD.
[0096]
By the way, when the threshold voltage of the two-layer gate structure type memory cell MC constituting the memory array MARY is in the fluctuation region, the corresponding bit of the read data RD is changed from logic “0” to “1” every time a read operation is performed. There is a case where the logic changes from “1” to “0”. This causes an abnormality in the determination process in step S318, which causes an undesired increase in write time and occurrence of an infinite loop.
[0097]
In the case of this embodiment, for example, the memory cell MC corresponding to the fourth bit of the read data RD is in the fluctuation region, and as shown in the 14th stage of FIG. The fourth bit of the data RD is changed to logic “1” in the third step S314 of the loop, and is in an erased state.
[0098]
However, in the embodiment of FIG. 4, the logical product data WDA is generated based on the read data RD and the inverted write data WDI. However, in this embodiment, as described above, the read data RD and Since it is generated on the basis of the write history data WDH, the fourth bit of the logical product data WDA remains logical “0” in step S316 of the third loop, and the writing is completed.
[0099]
That is, in the case of this embodiment, the write history data WDH is initially generated as the inverted write data WDI itself, but after the second loop, the write history data WDH is rewritten based on the result of the logical product processing in step S316, and once written. The bit corresponding to the memory cell MC in the state changes to logic “0”. In other words, each bit of the write history data WDH indicates that the corresponding memory cell MC is a write target bit, and also indicates a history that the corresponding memory cell MC has been once rewritten to logic “0”. As long as the rewrite data WDR is generated based on the write history data WDH and the read data RD, rewriting to the memory cell MC once rewritten does not occur.
[0100]
As a result, due to overwriting in which rewriting is repeated with respect to the memory cell MC in the written state, the threshold voltage of the memory cell becomes too low, causing a depletion failure, or the variation in the threshold voltage of the memory cell MC is large. Thus, the reliability of the flash memory FROM and thus the microcomputer can be improved.
[0101]
In the microcomputer of this embodiment, as in the embodiment of FIG. 4, the flash memory FROM write operation is actually executed in units of 128-byte sectors, and the above-described series of processing relating to the write operation of the designated sector. Is mainly performed by software by the central processing unit CPU. For this reason, the central processing unit CPU proceeds with specific processing according to the procedure shown in FIG. 11, and performs the write operation along the basic flow of FIG.
[0102]
That is, the central processing unit CPU first edits the 128-byte sector write data WDS to be written in the designated sector in step S411, and in the next steps S412 and 413, the sector write data WDS is bit-inverted to invert the sector. Write data WDIS and write history data WDHS are generated. In step S414, after holding data RDS of the designated sector is read out in units of sectors, in step S415, absurd writing is determined based on sector read data RDS and sector write data WDS.
[0103]
The central processing unit CPU that has successfully completed the absurd write determination process in step S415 inputs 4 bytes of the write history data WDHS to the register REG1 in the next step S416, and corresponds to the sector read data RDS in step S417. 4 bytes are input to the register REG2. In step S418, the contents of the registers REG1 and REG2, that is, the corresponding 4-byte logical product of the write history data WDHS and the sector read data RDS are obtained, and the processing result, that is, the logical product data is input to the register REG3. By S419, new write history data WDHS is set. Further, in step S420, it is determined whether or not the register REG3 becomes all bit logic “0”, and the generation processing and the writing processing of the rewrite data WDRS in steps S424 to S427 are selectively executed according to the result. . In step S423, the logic “0” of all bits of the register REG4 is determined, and the write operation relating to the sector write data WDS is terminated.
[0104]
In this way, a series of processing relating to the writing operation of the flash memory FROM is performed mainly by software by the central processing unit CPU, thereby reducing the hardware relating to the writing operation of the flash memory FROM and reducing the cost of the microcomputer. In addition, the development period of the flash memory FROM and thus the microcomputer can be shortened.
[0105]
FIG. 12 shows a basic flow chart of an embodiment at the time of erasing the flash memory of the microcomputer of FIG. The outline of flash memory erasing operation of the microcomputer of this embodiment and its features will be described with reference to FIG. This embodiment basically follows the embodiment shown in FIG. 1 to FIG. 8 or FIG. 9 to FIG. 11, and each processing step described below is not particularly limited. Performed by the CPU in software. The erase operation of the flash memory FROM is selectively performed by designating a block composed of a predetermined number of sectors, or is performed collectively for all addresses.
[0106]
In FIG. 12, the erase operation of the flash memory FROM in the microcomputer of this embodiment is started by the generation of the write data WD in step S511. In step S511, write data WD is generated to write logic “0” to all the memory cells MC at the address to be erased. The write data WD generated in step S511 is prewritten to the designated address of the flash memory FROM in a sector unit in step S512, and it is determined in step S513 whether prewrite to all the sectors to be erased has been completed. Done. As a result, when it is confirmed that pre-writing to all sectors is completed, the erasing operation is repeated in units of blocks, for example, in steps S514 and S515, and when erasing of all the blocks is confirmed, the erasing process is completed.
[0107]
In this embodiment, the pre-lighting in steps S512 and S513 is performed according to the basic flow of FIG. 4 or FIG. Therefore, the write operation to the two-layer gate structure type memory cell MC constituting the memory array MARY of the flash memory FROM is stopped when each memory cell MC is in a write state even once, and the memory cell MC after the prewrite is performed. The write state of is substantially equal to the average state. For this reason, even though the erase operation in steps S514 and S515 is performed in units of a block composed of a relatively large number of memory cells MC, these memory cells MC can be averaged. As a result, it is possible to prevent a specific memory cell MC from entering an over-erased state, thereby preventing the deterioration of the memory cell MC, thereby improving the reliability of the flash memory FROM and thus the microcomputer.
[0108]
FIG. 13 shows a partial circuit diagram of another embodiment of the memory array MARY and its peripheral part included in the flash memory of the microcomputer to which the present invention is applied. In this embodiment, the basic flow of FIG. 9 is realized by hardware mainly by related circuits of the flash memory, and the load on the central processing unit of the microcomputer is reduced accordingly. The circuit elements in FIG. 13 denoted by the same reference numerals as those in FIG. Further, in this embodiment, hardware corresponding to the absurd write determination process in step S315 of FIG. 9 is not included, but it is possible to include this as necessary. In the following, description will be added regarding parts different from FIG.
[0109]
In FIG. 13, the column latch CL is not particularly limited, but includes n + 1, that is, substantially 1,024 unit circuits provided corresponding to the bit lines B0 to Bn of the memory array MARY. A latch circuit L1 in which inverters V1 and V2 are cross-coupled, another latch circuit L2 in which inverters V4 and V5 are cross-coupled, and a two-input AND circuit that receives the output signals of these latch circuits L1 and L2. (AND) gate G1. The column latch CL includes an AND gate G2 having a substantially 1,024 input provided in common to the unit circuits, and each input terminal of the AND gate G2 has an input / output below the latch circuit L1 of each unit circuit. Each node is joined. Needless to say, the AND gate G2 is not composed of a single logic gate, but becomes a AND gate G2 having substantially 1,024 inputs by combining a large number of logic gates.
[0110]
The input / output node below the latch circuit L1 of each unit circuit of the column latch CL is coupled to the corresponding data input / output lines D0 to Dn, that is, the data input / output circuit IO via the switch MOSFET N1, and the AND gate G2 Each is coupled to a corresponding input terminal. The upper input / output node is coupled to the input terminal on the right side of the AND gate G1 and is coupled to the input terminal of the inverter V3 of the corresponding unit circuit of the write circuit WC, and further includes an N-channel switch MOSFET N4. To the corresponding output terminal of the AND gate G1. The latch control signal LC1 is commonly supplied from the memory controller MC (not shown) to the gate of the switch MOSFET N1, and the latch control signal LC4 is commonly supplied to the gate of the switch MOSFET N4.
[0111]
The latch control signal LC1 is normally at a low level such as the ground potential VSS, and when the flash memory is selected in the write mode, write data is input from the data input / output circuit IO via the Y gate circuit YG. At a predetermined timing, the power supply voltage VCC is selectively set to a high level. The latch control signal LC4 is also normally at a low level, and when the flash memory is selected in the write mode, AND data of the read data and the inverted write data or the write history data is generated by the AND gate G1. At a predetermined timing, in other words, at a timing corresponding to the end of step S316 in the basic flow of FIG.
[0112]
On the other hand, the input / output node below the latch circuit L2 of each unit circuit of the column latch CL is coupled to the corresponding data input / output lines D0 to Dn, that is, the data input / output circuit IO via the N-channel type switch MOSFET N3. The input terminal on the left side of the AND gate G1 is coupled to the inverted output node of the corresponding unit sense amplifier UA of the sense amplifier SA via the switch MOSFET N2. The latch control signal LC2 is commonly supplied from the memory controller MC to the gate of the switch MOSFET N2, and the latch control signal LC3 is commonly supplied to the gate of the switch MOSFET N3.
[0113]
Note that the latch control signal LC2 is normally at a low level such as the ground potential VSS, and when the flash memory is selected in the read mode, the output level of the corresponding unit sense amplifier UA is determined at a predetermined timing. It is selectively set to a high level like the power supply voltage VCC. The latch control signal LC3 is also normally at a low level, and when the flash memory is selected in the read mode, the latch control signal LC3 is selectively high at a predetermined timing at which the read data at the specified address should be transmitted to the data input / output circuit IO. Level.
[0114]
The write operation of the flash memory of this embodiment will be specifically described below in association with each processing step in the basic flow of FIG.
[0115]
First, the write data WD generated in step S311 of FIG. 9 is transferred from the data input / output circuit IO to the column latch CL in units of 32 bits via the corresponding 32 bits of the Y gate circuit YG and the data input / output lines D0 to Dn. Supplied. These write data WD are sequentially fetched and held in the latch circuit L1 of the corresponding unit circuit of the column latch CL via the switch MOSFET N1 that is turned on in response to the high level of the latch control signal LC1.
[0116]
Needless to say, each bit of the write data WD at the input / output node below the data input / output lines D0 to Dn, that is, the latch circuit L1 of each unit circuit of the column latch CL, is a bit corresponding to the memory cell MC to be written. “0”, that is, a low level such as the ground potential VSS, and all other bits are set to a logic “1”, that is, a high level such as the power supply voltage VCC. Each bit of the write data WD held in the latch circuit L1 is bit-inverted at the output terminal of the inverter V1, and becomes the inverted write data WDI after step S312 in FIG. 9, and also the write history data WDH after step S313. Become.
[0117]
Next, in step S314 in FIG. 9, 1,024 bits, that is, 128 bytes are read from the designated address of the memory array MARY, and logically inverted and established at the inverted output node of the corresponding unit sense amplifier UA of the sense amplifier SA. The read data RD to be received is simultaneously taken into the corresponding latch circuit L2 via the switch MOSFET N2 of the column latch CL which is turned on in response to the high level of the latch control signal LC2, and non-inverted at the output terminal of the inverter V5 Read data RD. These read data RD are logically ANDed with the corresponding bits of the write history data WDH held in the latch circuit L1 by the corresponding AND gate G1, and the logical product data WDA after step S316 in FIG. Become. Then, it is taken into the corresponding latch circuit L1 via the switch MOSFET N4 that is turned on in response to the high level of the latch control signal LC4, and becomes new write history data WDH after step S317.
[0118]
The write history data WDH, that is, the logical product data WDA taken into the latch circuit L1, is inverted at the input / output node below each latch circuit L1 and supplied to the corresponding input terminal of the AND gate G2, respectively, and the logical product is taken. . The AND gate G2 corresponds to the determination processing in step S318 in FIG. 9, and the output signal WDA0 is that all bits of the logical product data WDA held in the latch circuit L1 are logical "0". When it is done, it is selectively made high. The output signal WDA0 of the AND gate G2 is supplied to the memory controller MC of the flash memory, and the end of writing is determined by receiving the high level.
[0119]
On the other hand, the write history data WDH fetched by the latch circuit L1, that is, the logical product data WDA, becomes the rewrite data WDR at the input / output node below each latch circuit L1. Then, on condition that the corresponding bit of the rewrite data WDR is set to logic “0”, that is, on the condition that the corresponding bit of the logical product data WDA is logic “1”, that is, high level, the write circuit The MOSFET P1 of the corresponding unit circuit of WC is selectively turned on, and writing to the corresponding memory cell MC of the memory array MARY is selectively performed.
[0120]
As described above, in the microcomputer according to the present embodiment, a series of processes related to the write operation of the flash memory is mainly performed by hardware by the related circuit of the flash memory, that is, the column latch CL, the write circuit WC, and the sense amplifier SA. The central processing unit is hardly involved other than generation of write data WD and data transfer in units of 32 bits. For this reason, for example, when writing to the flash memory is performed partially in the interval of normal processing of the central processing unit, a relatively small amount of hardware is added and the flash memory or the like is relatively fast. Rewriting can be performed.
[0121]
The effects obtained from the above embodiments are as follows. That is,
(1) In a nonvolatile memory such as a flash memory mounted on a single chip microcomputer or the like, based on logical product data of read data read from a specified address and bit inverted data of write data to be written there, One read operation by determining the end of the write operation for the specified address and generating rewrite data to be rewritten to the specified address that has not been written based on the same logical product data The end of the write operation can be determined and the rewrite data can be generated based on the read data obtained by the above, so that an infinite loop is suppressed especially when the threshold voltage of the memory cell is in the fluctuation region, and the flash memory, etc. Can suppress unintentional increase in the time required for writing Effect that can improve characteristics.
[0122]
(2) Write history data obtained by bit-inverting write data to be written to a specified address or rewrite data for a specified address that has not been written in a non-volatile memory such as a flash memory mounted on a single chip microcomputer or the like. By determining the end of the write operation for the specified address based on the logical product data with the read data read from the specified address, and generating rewrite data based on the same logical product data, Even when a memory cell that has been written into is in an erased state, rewriting to such a memory cell can be prevented, so that an infinite loop especially when the threshold voltage of the memory cell is in the fluctuation region is further increased. Reliable cancellation and writing to flash memory etc. With an involuntary increase in main time can be reliably prevented, there is an advantage that it is possible to improve the writing characteristic.
[0123]
(3) In the above item (1) or (2), by applying a series of processes relating to a write operation of a flash memory or the like to a flash memory or the like having a prewrite function, prewriting of a memory cell to be erased There is an effect that the variation in the threshold voltage later can be reduced and the erasing characteristics can be improved.
[0124]
(4) In the above items (1) to (3), the absurd write determination processing is performed based on the logical product data of the write data to be written to the designated address and the bit inverted data of the read data read from the designated address. By doing so, it is possible to prevent the absurd writing to the already written bits of the specified address, and to identify the depletion error, thereby improving the reliability of the retained data such as the flash memory. An effect is obtained.
[0125]
(5) In the above items (1) to (4), a series of processing relating to the writing operation of the flash memory or the like is realized by software by a central processing unit mounted on the microcomputer or the like, so that the flash memory or the like Utilizing a central processing unit that is not used for normal processing while writing is in progress, reduce the amount of flash memory hardware, reduce the size of microcomputers and other chips, and reduce their costs The effect of being able to be obtained.
[0126]
(6) In the above items (1) to (4), a series of processing related to the write operation of the flash memory or the like is realized in hardware by a related circuit such as the flash memory, thereby adding a relatively small amount of hardware. In addition, there is an effect that the flash memory or the like can be partially rewritten at a relatively high speed and while the central processing unit is performing other processing.
[0127]
(7) According to the above items (1) to (6), the reliability of the flash memory and the single-chip microcomputer including the same can be improved, and the speed, cost, and efficiency of processing can be improved. The effect is obtained.
[0128]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the single-chip microcomputer does not necessarily include all the functional blocks shown in the figure, and can include other various functional blocks. The block configuration and bus configuration of the single-chip microcomputer can take various embodiments without being restricted by this embodiment.
[0129]
In FIG. 2, the flash memory FROM can take an arbitrary bit configuration such as x8 bits or x16 bits, and the memory array MARY is divided into a plurality of memory mats including its direct peripheral circuits. Can do. The storage capacity of the flash memory FROM can be arbitrarily set, and the same applies to the block configuration. 3 and 13, the memory array MARY can include an arbitrary number of redundant elements, and the absolute numbers of the word lines and bit lines can be arbitrarily set. The specific circuit configuration of the write circuit WC, the sense amplifier SA, and the column latch CL, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, the effective level of each control signal, and the like can take various embodiments.
[0130]
4, 6, 8, 9, 11, and 12, the specific processing flow at the time of writing / erasing the flash memory FROM can be changed in various ways such as changing the order or changing the logical value. A form may be considered.
[0131]
In the above description, the case where the invention made mainly by the present inventor is applied to the flash memory, which is a field of use as a background, and the single-chip microcomputer on which the flash memory is mounted has been described. However, the present invention is not limited thereto. For example, a flash memory and a central processing unit formed on separate semiconductor substrate surfaces, a single flash memory, or various memory integrated circuit devices having similar write / erase functions, Furthermore, it can be applied to various digital systems equipped with this. The present invention can be widely applied to a nonvolatile memory having a memory array in which at least two-layer gate structure type memory cells are arranged in a grid and a system including the nonvolatile memory.
[0132]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. In other words, in a non-volatile memory such as a flash memory mounted on a single-chip microcomputer, etc., specified based on the logical product data of the read data read from the specified address and the bit inverted data of the write data to be written there By determining the end of the write operation for the address and generating rewrite data to be rewritten to the designated address where the write has not been completed based on the same logical product data, Based on the obtained read data, the end of the write operation can be determined and rewrite data can be generated, so that infinite loops are suppressed especially when the threshold voltage of the memory cell is in the fluctuation region, and flash Suppressing unintentional increases in the time required for writing to memory, etc. Rutotomoni, it is possible to improve the writing characteristic such as a flash memory.
[0133]
In non-volatile memory such as flash memory mounted on a single-chip microcomputer, etc., write data to be written to a specified address, or write history data obtained by bit-reversing rewrite data for a specified address that has not been written, and specified Memory that has been written once by determining the end of the write operation based on logical product data with read data read from the address and generating rewrite data based on the same logical product data Even when the cell is in the erased state again, such rewriting to the memory cell can be prevented, so that the infinite loop can be more reliably eliminated especially when the threshold voltage of the memory cell is in the fluctuation region. Unnecessarily increase the time required for writing to flash memory, etc. It is possible to reliably prevent, it is possible to improve the writing characteristic such as a flash memory.
[0134]
By applying a series of processing related to the write operation of the flash memory to a flash memory having a prewrite function and a microcomputer including the same, the threshold voltage after prewrite of the memory cell to be erased is reduced. The variation can be suppressed and the erasing characteristics can be enhanced.
[0135]
In the above flash memory or the like, the specified address is already written by performing an absurd write determination process based on the logical product data of the write data to be written to the specified address and the bit inverted data of the read data read from the specified address. It is possible to prevent an absurd writing to a completed bit and to identify a depletion error, thereby improving the reliability of data held in a flash memory or the like.
[0136]
A series of processing related to the writing operation of the flash memory or the like is realized by software by a central processing unit mounted on a microcomputer or the like so that it can be used for normal processing while writing to the flash memory or the like is performed. It is possible to reduce the cost by reducing the amount of hardware such as a flash memory and reducing the chip size of a microcomputer or the like by utilizing a non-central processing unit for rewriting a flash memory or the like.
[0137]
A series of processing related to the write operation of the flash memory and the like is realized by hardware using a related circuit such as a flash memory, so that a relatively small amount of hardware is added and the central processing unit can be operated at a relatively high speed. During the processing, partial rewriting of the flash memory or the like can be performed.
[0138]
As described above, the reliability of a flash memory and the like and a single chip microcomputer including the same can be improved, and the speed, cost, and efficiency of processing can be improved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a microcomputer to which the present invention is applied.
2 is a block diagram showing an embodiment of a flash memory included in the microcomputer of FIG. 1. FIG.
3 is a partial circuit diagram showing one embodiment of a memory array and a peripheral portion included in the flash memory FROM of FIG. 2; FIG.
4 is a basic flow diagram showing a first embodiment of the microcomputer of FIG. 1 when writing to a flash memory. FIG.
5 is an operation concept diagram showing one embodiment for explaining the operation at the time of writing to the flash memory of FIG. 4; FIG.
6 is a basic flowchart showing an embodiment of absurd write determination processing at the time of writing to the flash memory of FIG. 4; FIG.
7 is an operation conceptual diagram showing an embodiment for explaining the operation during the absurd write determination processing of FIG. 6; FIG.
8 is a process flow diagram showing an embodiment of a central processing unit of a microcomputer taking the basic flow of FIG.
FIG. 9 is a basic flowchart showing a second embodiment of the microcomputer of FIG. 1 when writing to the flash memory.
10 is an operation concept diagram showing one embodiment for explaining the flash memory writing operation of FIG. 9; FIG.
11 is a process flow diagram showing an embodiment of a central processing unit of a microcomputer taking the basic flow of FIG. 9;
12 is a basic flow diagram showing an embodiment of the microcomputer of FIG. 1 when erasing flash memory. FIG.
FIG. 13 is a partial circuit diagram showing another embodiment of a memory array and its peripheral part included in a flash memory of a microcomputer to which the present invention is applied;
FIG. 14 is a basic flowchart showing an example of writing to flash memory by a microcomputer developed by the inventors of the present application prior to the present invention.
FIG. 15 is a flash of a microcomputer developed by the present inventors prior to the present invention.
It is a basic flowchart which shows another example at the time of write-in memory.
[Explanation of symbols]
CPU ... Central processing unit, CPG ... Clock generation circuit, IBUS ... Internal bus, PBUS ... Peripheral bus, FROM ... Flash memory, SRAM ... Static RAM (Random access memory), DMAC ... Direct memory access Controller, BUSC ... Bus controller, SCI ... Serial communication interface, TIM ... Timer circuit, D / A ... Digital / analog conversion circuit, A / D ... Analog / digital conversion circuit, IOPA-IOPK ... Input / output Port, XTAL: Crystal oscillator.
MARY ... Memory array, XD ... X address decoder, SC ... Source voltage control circuit, WC ... Write circuit, SA ... Sense amplifier, CL ... Column latch, YG ... Y gate circuit, YD ... Y Address decoder, CB ... Control buffer, MC ... Memory controller, AB ... Address buffer, DB ... Data buffer, IO ... Data input / output circuit, VG ... Internal voltage generation circuit, VCS ... Voltage control signal, VCC: power supply voltage, VSS: ground potential.
W0 to Wm... Word line, B0 to Bn... Bit line, MC... Two-layer gate structure type memory cell, S0 to Sp... Source line, VPP ... internal voltage, UA. Dn: Data input / output line, WP: Write control signal, RC: Read control signal, LC1 to LC4: Latch control signal.
S111 to S118, S141 to S143, S211 to S225, S311 to S320, S411 to S427, S511 to S515, S611 to S619, S711 to S716 ... processing steps.
WD: Write data, WDI: Inverted write data, WDR: Rewrite (rewrite) data, WDH, WDSH ... Write history data, RD: Read data, RDI: Inverted read data, WDA, RDA ... Logical product data, WDS: Sector write data, WDIS: Inverted sector write data, WDRS: Sector rewrite data, RDS: Sector read data, REG1 to REG4: Registers.
L1 to L2... Latch circuit.
P1 to P3... P channel MOSFET, N1 to N4... N channel MOSFET, V1 to V5... Inverter, G1 to G2.

Claims (4)

A microcomputer having a central processing unit and a non-volatile memory having a memory array in which two-layer gate structure type memory cells are arranged in a lattice on the same semiconductor substrate,
The non-volatile memory is a predetermined data write operation executed by the central processing unit.
An inverted signal of write data to be written to the designated address of the memory array indicated by the central processing unit is formed as first data, and the read data read from the designated address and the first data are subjected to a logical product process. Generating a second data, forming an inverted signal of the second data as third data, and storing the first data in a latch circuit provided in a bit line corresponding to the designated address of the memory array. A second operation performed a plurality of times for a plurality of designated addresses corresponding to the write unit of the array;
A third operation of simultaneously writing the third data stored in the latch circuit to the memory cells of the memory array in the memory array;
The microcomputer in which the first to third operations are repeatedly performed until the second data corresponding to the write unit corresponding to each designated address matches the same bit state . In claim 1 ,
Prior to erasing data, the non-volatile memory pre-writes the information held in all memory cells to be erased so as to be in a written state,
A series of processing related to the write operation including the first to third operations of the nonvolatile memory uses all the bits of the write data as data that should make the erase state of the memory cell the write state , even during the pre-write. A microcomputer characterized by being performed . In claim 1 or claim 2 ,
And the write data to be written to the specified address in the memory array after said first operation or second operation, logical and fourth data formed by inverting the read data read from the specified address of the memory array Riseki processing all the bits that are shifted to the third operation when there is a match, the microcomputer characterized that you further performs a fourth operation error is also determined with the presence of stated mismatch in 1 bit. In claim 3 ,
The predetermined data write operation executed by the central processing unit is performed by software in accordance with a write control program including the first to fourth operations stored in the nonvolatile memory. A microcomputer.

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