JP2000090678A - Nonvolatile memory and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data writing method effective for prewrite system flash memory, or the like, and to enhance reliability of a flash memory being mounted on a single chip microcomputer, or the like, by improving the writing/erasing characteristics thereof. SOLUTION: In a flash memory being mounted on a single chip microcomputer, or the like, a read data RD to be read out from a designated address is generated at step S113 and the logical product data WDA of the read data RD and the bit inverted data WD1 of a write data WD to be written at a designated address is generated at step S115. Based on the logical product data WDA, a decision is made step S116 that the write operation has ended and creat a rewrite date WDR to be rewritten at a designated address where write operation has not yet ended is generated at step S117 based on an identical logical product data WDA.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory and a system, for example, a flash memory having a prewrite function, a single-chip microcomputer including the same, and a technique particularly effective for improving the reliability thereof.

[0002]

2. Description of the Related Art A so-called two-layer gate type memory cell having a floating (floating) gate and a control (control) gate whose threshold voltage is selectively raised or lowered in accordance with the logical value of retained data is known. is there. There is also a flash memory whose basic component is a memory array in which such two-layer gate structure type memory cells are arranged in a lattice, and such a flash memory and a central processing unit are mounted on the same semiconductor substrate surface. There is a single-chip microcomputer.

[0003] On the other hand, the data erasing operation in a flash memory is performed, for example, in units of predetermined blocks. One means for improving the erasing characteristics of the flash memory is to erase all memory cells to be erased prior to the erasing operation. It is becoming common to perform so-called pre-write in which the data is written in a writing state.

[0004]

Prior to the present invention, the inventors of the present invention developed a single-chip microcomputer equipped with a flash memory, and noticed the following problems in the process. That is, in this microcomputer, data processing is performed by the central processing unit in units of 32 bits, for example, and data is written to the flash memory in units of so-called sectors of, for example, 128 bytes.

In the microcomputer, the generation and verification of write (write) data with respect to the flash memory, that is, the write confirmation processing, are performed by software by a central processing unit of the microcomputer, and the processing steps are exemplified in FIG. As described above, first, after the write data WD is generated in step S611, the inverted write data WDI obtained by bit-inverting the write data WD is generated in step S612.
In the write data WD, the bit to be written is so-called logic "0", and in the inverted write data, the bit to be written is so-called logic "1". In the flash memory, of the two-layer gate structure type memory cells constituting the memory array, a memory cell in an erased state has a relatively high threshold voltage, for example, and holds data of logic "1". It is assumed that the memory cell in the written state has a relatively low threshold voltage and holds data of logic "0".

In the microcomputer, after the held data RD is read from the address to be written into the flash memory in the next step S613,
By the step S614, the inverted write data WDI
AND data WDA of data and read data RD is calculated. Also, in step S615, the logical product data WD
A rewrite data WDR for inverting the bits of A and rewriting the data at the specified address is generated.
By 16, the rewrite data WDR is written to the designated address of the flash memory of the memory array.

When a series of write operations is completed, in step S617, the stored data R from the designated address is read.
D is read again, and the logical product data WDA of the inverted write data WDI and the read data RD is calculated in step S618. A determination is made. If all bits are “0”, it is determined that the write operation has been completed. If any of the bits is “1”, the process returns to step S613, and a series of write operations is repeated. This allows
Write control is performed in bit units, and writing is repeated only for the memory cells in the erased state. As a result, the meaningless writing is repeatedly performed on the memory cell in the written state, and the threshold voltage of the memory cell can be prevented from lowering unnecessarily, so that the writing / erasing characteristics of the flash memory can be improved.

However, in the flash memory, after the write operation of, for example, 128 bytes in steps S613 to S616 is repeated, steps S617 to S616 are repeated.
The determination operation of S619 is repeated, and the reading operation of the designated address in Steps S613 and S617 is performed twice after a relatively long time. Therefore, if a difference occurs in the logical value of the read data RD obtained by these read operations, an undesired write operation is performed, and the time required for the write becomes longer. In a so-called fluctuation area fluctuating to logic “1” or “0”, for example, in step S61
3, the read result becomes logic "0" and step S6
In the case where the result of reading by the logic circuit 17 becomes logic "1", an infinite loop state occurs and the writing process does not end forever, thereby lowering the reliability of the flash memory and thus the microcomputer including the flash memory.

In order to cope with this, the present inventors et cetera, as exemplified in FIG.
Instead of the write process of No. 16, a method of fixedly writing the given write data WD in step S713 regardless of the read result of the designated address was considered.
However, by adopting this method, the read operation of the designated address is performed once and the above-mentioned problem is solved. For example, in a 32-bit memory cell serving as a write unit, there are those in an erased state and those in a written state. If mixed,
Unnecessary writing is repeatedly performed on the memory cells already in the written state, so that writing stress on these memory cells increases. In particular, in the case of a flash memory employing a pre-write method, the threshold voltage of the memory cell to be erased becomes unnecessarily low due to an erasing process, and the threshold voltage of the memory cell to be erased becomes uneven. Deterioration to erasure characteristics.

An object of the present invention is to provide a data writing method effective for a flash memory or the like employing a prewrite method. Another object of the present invention is to improve the write / erase characteristics of a flash memory or the like mounted on a single-chip microcomputer or the like, and to enhance its reliability.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of typical inventions disclosed in the present application. That is, in a nonvolatile memory such as a flash memory mounted on a single-chip microcomputer or the like, based on logical product data of read data read from a specified address and bit-inverted data of write data to be written to the specified address, Determines the end of the write operation to the specified address and
Based on the same logical product data, rewrite data to be rewritten to a specified address where writing has not been completed is generated.

[0013] Alternatively, logical product data of write data to be written to a specified address or write history data obtained by bit inversion of rewrite data for a specified address for which writing has not been completed, and read data read from the specified address is also stored. At the same time, the end of the write operation to the specified address is determined, and the rewrite data is generated based on the same logical product data.

A series of processes relating to a write operation of the above flash memory or the like is applied to a flash memory or the like having a prewrite function for aligning information held in all memory cells to be erased to a write state prior to erasure of data. I do.

In the above-mentioned flash memory, etc., based on the logical product data of the write data to be written to the specified address and the bit-inverted data of the read data read from the specified address, the absurd writing of the already written bits of the specified address Or a depletion error.

A series of processes relating to the writing operation of the flash memory or the like is realized by software by a central processing unit mounted on a microcomputer or the like.

A series of processes related to the write operation of the flash memory or the like is realized by hardware using a related circuit such as a flash memory.

According to the above-described means, the end of the write operation can be determined based on the read data obtained by one read operation, and the rewrite data can be generated. It is possible to suppress an infinite loop when the threshold voltage is in the fluctuation region, suppress an undesired increase in the time required for writing in a flash memory or the like, and improve the writing characteristics of the flash memory or the like.

Further, the end of the write operation is determined based on the logical product data of the write history data and the read data, and the rewrite data is generated. In such a case, rewriting to the memory cell can be prevented, so that an infinite loop, particularly when the threshold voltage of the memory cell is in the fluctuation region, is more reliably eliminated, and writing to a flash memory or the like can be prevented. It is possible to reliably prevent an undesired increase in the required time, and to further improve the write characteristics of a flash memory or the like.

By applying a series of processes relating to a write operation to a flash memory or the like having a prewrite function, variations in the threshold voltage of a memory cell to be erased after prewrite are suppressed, and the erase characteristics of the flash memory or the like are reduced. Can be increased.

By determining the absurd write based on the logical product data of the write data and the bit-inverted data of the read data, it is possible to identify the absurdity of the write data for the memory cell already in the written state,
It is possible to identify a depletion error of a memory cell coupled to the same bit line as a memory cell to be written, thereby improving the reliability of data held in a flash memory or the like.

A series of processes relating to the writing operation of the flash memory or the like is realized by software by the central processing unit, so that the central processing unit which is not used for normal processing while the rewriting of the flash memory or the like is performed. By utilizing the above, the amount of hardware of the flash memory can be reduced, the chip size of the microcomputer or the like can be reduced, and the cost can be reduced.

A series of processes relating to the write operation of the flash memory and the like are realized by hardware using related circuits such as a flash memory, so that a relatively small amount of hardware is added, the speed is relatively high, and the central processing is performed. While the unit is performing other processing, partial rewriting of the flash memory or the like can be performed.

As described above, the reliability of the flash memory and the like and the single-chip microcomputer including the same can be enhanced, and the speed, the cost, and the processing efficiency can be improved.

[0025]

FIG. 1 is a block diagram showing one embodiment of a single-chip microcomputer (system) to which the present invention is applied. First, an outline of the configuration and operation of a single-chip microcomputer (hereinafter simply referred to as a microcomputer) of this embodiment and its features will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, a well-known MOSFET (metal oxide semiconductor type field effect transistor; in this specification, MOSFET
(Referred to as an insulated gate type field effect transistor) on a single semiconductor substrate surface such as single crystal silicon by an integrated circuit manufacturing technique.

Referring to FIG. 1, the microcomputer of this embodiment includes a so-called stored program central processing unit CPU and a clock generation circuit CPG. The central processing unit CPU is connected to a flash memory FROM (non-volatile memory), a static RAM (SRAM), a direct memory access controller DMAC, and a bus controller BUSC via an internal bus IBUS, and a clock generation circuit C
The crystal oscillator XTAL having a predetermined natural vibration number is coupled to the PG via the external terminals XTAL and EXTAL. The microcomputer is further supplied with a power supply voltage VCC and a ground potential VSS as main operating power supplies from external power supply devices via external terminals VCC and VSS, respectively. The central processing unit CPU has an external terminal STB.
Standby signal STBYB via YB and RESB
(Here, a so-called inverted signal or the like which is selectively set to a low level when it is made valid is represented by suffixed with B at the end of its name. The same applies hereinafter) and a reset signal RE.
SB are supplied respectively. The power supply voltage VCC serving as a main operation power supply is, for example, +5 V (volt).

The central processing unit CPU of the microcomputer performs step operations in accordance with a control program stored in the flash memory FROM, performs various arithmetic processes, and controls and controls each section of the microcomputer. In this embodiment, the central processing unit C
The PU performs a series of processes relating to rewriting of the flash memory FROM, which will be described later in detail.

The clock generation circuit CPG, together with the external crystal oscillator XTAL, forms a clock signal having a predetermined frequency and phase corresponding to its natural frequency, and supplies it to each section of the microcomputer. The flash memory FROM uses a memory array in which memory cells each having a two-layer gate structure having a control gate and a floating gate are arranged in a lattice as its basic constituent elements. Stores data etc. Needless to say, since the data held in the flash memory FROM can be rewritten, a system having various functions can be realized with the same microcomputer, and the development period for debugging or the like can be shortened. . The specific configuration and operation of the flash memory FROM, its writing and erasing processing procedures and characteristics will be described later in detail.

The static RAM (SRAM) enables relatively high-speed access, and the central processing unit CP
The calculation result of U and control data are temporarily stored. Also, a direct memory access controller DMAC
Supports data transfer between, for example, a static RAM (SRAM) and an external device without the intervention of a central processing unit CPU. Further, the bus controller BUSC manages bus access to the internal bus IBUS, and controls the internal bus IBUS and the peripheral bus PBU.
S, that is, a connection process with a device coupled thereto is performed.

Microcomputer peripheral bus PBUS
Is further connected to a serial communication interface SCI, a timer circuit TIM, a digital / analog conversion circuit D / A, an analog / digital conversion circuit A / D, and eleven input / output ports IOPA to IOPK. Among them, the serial communication interface SCI has corresponding input / output ports IOPA to IOPA.
Supports serial data transfer according to a predetermined algorithm with an external serial input / output device coupled to a predetermined port of the PK, and the timer circuit TIM operates according to a clock signal supplied from a clock generation circuit CPG. Perform time management.

On the other hand, a digital / analog conversion circuit D / A
Converts digital data generated by the central processing unit CPU or the like into a predetermined analog signal and transmits the analog signal to an external input / output device. The analog / digital conversion circuit A / D converts an analog input signal input from, for example, various external sensors into a digital signal of a predetermined bit and transmits the digital signal to a central processing unit CPU and the like. further,
The input / output ports IOPIOPA to IOPK function as interface circuits for transmitting and receiving signals between the various components of the microcomputer and various external devices.

As described above, the flash memory FROM
Are provided for storing control programs, fixed data, and the like, and rewriting is performed mainly by software by the central processing unit CPU. In this embodiment, in particular, prior to the erasing operation of the flash memory FROM, pre-writing for aligning all memory cells to be erased to a writing state is performed, and at the time of writing, read data read from a designated address is read. The end of the write operation is determined based on the logical product data of the write data and the bit-inverted data, and the rewrite data for the specified address where the writing has not been completed is generated based on the same logical product data, or The end of the write operation is determined based on the logical product data of the write history data obtained by bit inverting the write data or the rewrite data and the read data, and the rewrite data is determined based on the same logical product data. Generation occurs.

As a result, the reliability of the flash memory FROM and the microcomputer including the same can be improved, and the speed, cost, and processing efficiency can be increased. These will be described later in detail.

FIG. 2 is a block diagram showing one embodiment of the flash memory FROM included in the microcomputer of FIG. FIG. 3 is a partial circuit diagram of one embodiment of the memory array MARY and peripheral portions included in the flash memory FROM of FIG. With reference to these drawings, the specific configuration and operation of the flash memory FROM included in the microcomputer of this embodiment, its features, and the like will be described. Note that FIG.
In FIG. 1, typical parts of the write circuit WC, the sense amplifier SA, and the column latch CL are exemplified, but the circuit elements constituting each part are not all illustrated. In the following circuit diagram, the MOSFET with an arrow on its channel (back gate) portion is a P-channel type and an N-channel MOSFET without an arrow
It is shown separately from.

In FIG. 2, the flash memory FROM of this embodiment has a memory array MARY arranged as occupying most of the required layout area as its basic component. Also, the flash memory FROM has an internal bus IB
It includes a control buffer CB coupled to a US control bus CBUS, and further includes a memory controller MC receiving an output signal of the control buffer CB, and an internal voltage generating circuit VG receiving a power supply voltage VCC and a ground potential VSS.

The control buffer CB and the memory controller MC selectively form various internal control signals (not shown) based on various activation control signals supplied through the control bus CBUS of the internal bus IBUS. It is supplied to each part of the flash memory FROM.
The internal voltage generation circuit VG is provided with a voltage control signal V supplied from a control circuit (not shown) of the microcomputer.
It includes a plurality of voltage generating circuits selectively activated according to CS, and generates various internal voltages necessary for writing, erasing and reading operations of the flash memory FROM.

On the other hand, the memory array MARY is, although not particularly limited, a so-called NOR type array.
As shown in FIG. 3, m + 1 or substantially 1,024 word lines W0 to W0 arranged in parallel in the horizontal direction of the drawing are substantially provided.
Wm and n + 1 bit lines B0 to Bn arranged in parallel in the vertical direction, that is, substantially 1,024 bit lines B0 to Bn. At the intersection of these word lines and bit lines, a 1,024 ×
1,024, that is, 1,048,576 two-layer gate structure type memory cells MC are arranged in a lattice. This allows
The flash memory FROM has a so-called 1 megabit storage capacity.

The control gates of the (n + 1) memory cells MC arranged on the same row of the memory array MARY are:
Commonly coupled to corresponding word lines W0 to Wm, respectively.
The sources include the sources of the (n + 1) memory cells MC arranged in the adjacent row and the corresponding source lines S0 to Sp.
Are commonly connected to each other. Also, the memory array MAR
The drains of the (m + 1) memory cells MC arranged in the same column of Y are commonly coupled to corresponding bit lines B0 to Bn. The number p + 1 of the source lines S0 to Sp
However, it goes without saying that there is a relationship of p + 1 = (m + 1) / 2 with respect to the number m + 1 of the word lines W0 to Wm.

In this embodiment, the memory array MAR
Each of the two-layer gate structure type memory cells MC constituting Y is not particularly limited, but is assumed to hold so-called logical "1" data when it is in an erased state and when it is in a write state. , So-called logical "0" data. In the erasing operation of the memory cell MC, a positive potential such as +9 V is applied to its control gate, that is, the corresponding word line W0 to Wm, and its source, that is, the corresponding source line S0
To Sp, for example, by applying a negative potential such as -9 V, and injecting electrons from the source side into the floating gate. The write operation of the memory cell MC is performed on the drain, that is, the corresponding bit line B0 to Bn. And a negative potential such as -9 V is applied to the control gate, that is, the corresponding word line W0-Wm, to extract the electrons accumulated in the floating gate to the drain side. It is done by doing.

Thus, the threshold voltage of memory cell MC is set to a relatively high value exceeding, for example, +2.5 V when it is in the erased state, and is lower than +2.5 V when it is in the written state. A relatively low value.
Therefore, during the read operation of the held data, the corresponding word lines W0 to Wm are selectively set to a selection level such as +2.5 V, for example, so that the memory cells MC in the erased state are turned off and compared. An extremely small read current is passed, and the memory cell MC in the write state is turned on to pass a relatively large read current.

As shown in FIG. 2, the word lines W0 to Wm forming the memory array MARY are coupled to the X address decoder XD on the left side thereof, and are connected to the source lines S0 to Wm.
Sp is coupled to the source voltage control circuit SC to the right. Although not particularly limited, the X address decoder XD receives a 10-bit internal X from the address buffer AB.
Address signals X0 to X9 are supplied, and various internal voltages necessary as selection or non-selection levels of word lines W0 to Wm are supplied from internal voltage generation circuit VG. The internal X address signals X0 to X9 are also supplied to a source voltage control circuit SC. The source voltage control circuit SC further includes various types of signals required as selection or non-selection levels of the source lines S0 to Sp from the internal voltage generation circuit VG. Is supplied.

When flash memory FROM is selected, X address decoder XD decodes internal X address signals X0 to X9 supplied from address buffer AB, and outputs word lines W0 to W0 of memory array MARY.
The corresponding bit of Wm is selectively set to a predetermined selection or non-selection level. When flash memory FROM is selected, source voltage control circuit SC similarly decodes internal X address signals X0-X9 and selectively corresponding bits of source lines S0-Sp of memory array MARY. It has a predetermined selection or non-selection level.

Although not particularly limited, the flash memory F
When the ROM is in the write mode, the word lines W0 to W0
As described above, the selection level of Wm is, for example, -9 V, and the non-selection level is, for example, power supply voltage VCC, that is, +5 V, for example. Also, a flash memory FROM
Is set to the erase mode, the selection level of the word lines W0 to Wm is set to, for example, +9 V as described above, and the non-selection level is set to, for example, the ground potential VSS. further,
When the flash memory FROM is set to the read mode, the selection level of the word lines W0 to Wm is, for example, +2.5 V as described above, and the non-selection level is the ground potential VSS.

Note that the write mode of the flash memory FROM includes a read operation for confirming a write state, that is, a verify operation. In this verify operation, the selection level of the word lines W0 to Wm is:
It is set to, for example, +4 V, which is slightly higher than the selection level in the normal read operation, that is, +2.5 V.

On the other hand, when the flash memory FROM is in the write mode, the selected source lines S0 to S0
Sp is in a so-called open state, and its non-selection level is set to the ground potential VSS. Also, the flash memory FR
When the OM is set to the erase mode, the selection level of the source lines S0 to Sp is set to, for example, -9 V, and the non-selection level is set to the ground potential VSS. When the flash memory FROM is set to the read mode, all the source lines S0 to Sp are set to the ground potential VSS.

Next, the bit lines B0 to Bn forming the memory array MARY are connected to the write circuit W
C and the corresponding unit circuit of the sense amplifier SA. Each unit circuit of the write circuit WC and the sense amplifier SA is coupled to the corresponding unit circuit of the column latch CL on the other side, and each unit circuit of the column latch CL has 32 unit circuits on the other side via the Y gate circuit YG Each is selectively connected to a corresponding unit circuit of the data input / output circuit IO. Each unit circuit of the data input / output circuit IO is:
The other side is coupled to a corresponding unit circuit of data buffer DB, and the other side of data buffer DB is coupled to a corresponding bit of data bus DBUS of internal bus IBUS.

The Y gate circuit YG is supplied with q + 1 bits, ie, substantially 128 bits, bit line selection signals YS0 to YSq from the Y address decoder YD. The Y address decoder YD receives a 7-bit internal Y address from the address buffer AB. Signals Y0 to Y6 are supplied. The address buffer AB has an address bus A of the internal bus IBUS.
17-bit address signals A0 to A16 via BUS
Is supplied.

Address buffer AB is connected to internal bus IBU
The address signals A0 to A16 supplied via the S address bus ABUS are captured and held. Then, the 10 bits are used as the internal X address signals X0 to X9, and the X address decoder XD and the source voltage control circuit S are used.
C, and the remaining 7 bits are converted to the internal Y address signal Y.
It is supplied to the Y address decoder YD as 0 to Y6.

The Y address decoder YD includes internal Y address signals Y0 to Y6 supplied from the address buffer AB.
And selectively set the corresponding bits of the bit line selection signals YS0 to YSq for the Y gate circuit YG to a predetermined selection level.

The Y gate circuit YG includes n + 1, ie, 1,0, provided corresponding to each unit circuit of the column latch CL.
Includes 24 switch MOSFETs. These switch MOSFETs are selectively turned on 32 by 32 when the corresponding bits of the bit line selection signals YS0 to YSq supplied from the Y address decoder YD are alternatively set to a high level, and the column latches CL Is connected between one input / output node of each unit circuit and the corresponding unit circuit of the data input / output circuit IO.

On the other hand, when the flash memory FROM is selected in the write mode, the data buffer DB and the data input / output circuit IO sequentially transmit 32-bit write data supplied via the data bus DBUS of the internal bus IBUS. The data is fetched and transmitted to the designated 32 unit circuits of the column latch CL via the Y gate circuit YG. When 128 bytes, that is, 1,024 bits, of the write data captured by each unit circuit of the column latch CL are accumulated, 1,024 pieces of 1,024 bits that are coupled to the selected word line of the memory array MARY via the write circuit WC. The data is simultaneously written to the memory cells MC. When the flash memory FROM is set to the read mode, the data bus DBUS and the data input / output circuit IO connect to the memory array M
The read data output from the selected memory cell MC of the ARY and held in each unit circuit of the column latch CL is selectively taken out by 32 bits, and the internal bus IBUS
To the access device via the data bus DBUS.

As described above, the data input / output operation with respect to the flash memory FROM of this embodiment is performed in units of 32 bits, that is, 4 bytes.
The substantial write and read operations for ARY are:
This is performed in units of 128 bytes, that is, 1,024-bit sectors. Therefore, the word lines W0 to Wm of the memory array MARY are connected to the 10-bit internal X address signal X.
0 to X9, and the bit line B0
.About.Bn are selectively designated in units of 32 bits in accordance with the 7-bit internal Y address signals Y0 to Y6.

Here, the column latch CL includes n + 1, ie, substantially 1,024 unit circuits provided corresponding to the bit lines B0 to Bn of the memory array MARY, and each of these unit circuits is particularly limited. However, as illustrated in FIG. 3, a pair of inverters V1 and V2
Are cross-coupled, and two N-channel switch MOSFETs N1 and N2. Of these, the input / output node below the latch circuit L1 of each unit circuit of the column latch CL is connected to a switch MOSFET.
Via TN1, it is coupled to corresponding data input / output lines D0-Dn, that is, data input / output circuit IO. The upper input / output node is coupled to an input terminal of a corresponding inverter V3 of a write circuit WC to be described later, and is coupled to an inverted output node of a corresponding unit sense amplifier UA of the sense amplifier SA via a switch MOSFET N2. Is done. The latch control signal LC1 is commonly supplied from the memory controller MC to the gate of the switch MOSFET N1, and the latch control signal LC2 is commonly supplied to the gate of the switch MOSFET N2.

The latch control signal LC1 is normally set to a low level such as the ground potential VSS, and when the flash memory FROM is selected in the write mode,
At a predetermined timing, it is selectively set to a high level like the power supply voltage VCC. The latch control signal LC2 is normally set to a low level such as the ground potential VSS, and is selectively set to a high level such as the power supply voltage VCC at a predetermined timing when the flash memory FROM is selected in the read mode. You.

As described above, the flash memory FROM
Is set to the selected state in the writing mode, the data latch DBUS, the data buffer DB, the data input / output circuit IO, the Y gate circuit YG, and the data input / output line D0 of the internal bus IBUS are supplied from the access device to the column latch CL.
Write data is supplied in 32-bit units via .about.Dn. These write data are latch control signals L
Switch MO that is turned on in response to the high level of C1
Through the SFET N2, the corresponding 3 of the column latch CL
The two latch circuits L1 sequentially take in and hold the data.
Then, at the point in time when the capture of the 128-byte write data is completed, the data is transmitted to the memory array MARY via the write circuit WC, and n + coupled to the selected word line.
Data is simultaneously written to one, that is, substantially 1,024 memory cells MC.

On the other hand, when the flash memory FROM is selected in the read mode, the inverted output signal of the unit sense amplifier UA, that is, the inverted output signal of the unit sense amplifier UA from the 1,024 unit circuits of the sense amplifier SA described later is stored in the column latch CL. Read data is supplied. These inverted read data are simultaneously captured and held by the latch circuit L1 of each unit circuit of the column latch CL via the switch MOSFET N2 which is turned on in response to the high level of the latch control signal LC2. Then, the data is inverted by the inverter V2 of the corresponding latch circuit L1 to become non-inverted read data. DBU
The data is output to the access device in 32-bit units via S.

Next, the write circuit WC is provided corresponding to the bit lines B0 to Bn of the memory array MARY.
+1 or 1,024 unit circuits, each of which is not particularly limited, as shown in FIG. 3, has two P-channel MOSFETs P1 and P2 and a relatively High potential internal voltage VP
And an inverter V3 using P as an operation power supply. The source of the MOSFET P1 constituting each unit circuit of the write circuit WC is coupled to the internal voltage supply point VPP, and the drain thereof is connected to the memory array MARY via the MOSFET P2.
Are coupled to corresponding bit lines B0 to Bn. Also, M
The gate of the OSFET P1 is coupled to the output terminal of the corresponding inverter V3, and the input terminal of the inverter V3 is coupled to the output terminal of the inverter V1 forming the corresponding latch circuit L1 of the column latch CL. Write circuit W
The write control signal WP is commonly supplied from the memory controller MC to the gate of the MOSFET P2 of each unit circuit of C.

The write control signal WP is normally set to a high level like the internal voltage VPP, and when the flash memory FROM is selected in the write mode,
At a predetermined timing, it is selectively set to a low level such as the ground potential VSS.

As a result, the MOSFET P2 constituting each unit circuit of the write circuit WC is
When the ROM is selected in the write mode, the ROM is selectively and simultaneously turned on in response to the low level of the write control signal WP. At this time, the MOSF of each unit circuit
ETP1 is provided on condition that the output signal of the corresponding inverter V3 is at a low level such as the ground potential VSS.
In other words, the write data held by the corresponding latch circuit L1 of the column latch CL is logic “0”.
And the output signal of the inverter V1 is set to a high level to selectively turn on the memory array MA.
The bit lines B0 to Bn corresponding to RY are set to a high selection level such as the internal voltage VPP, that is, + 6V.

Needless to say, when the write data held by the corresponding latch circuit L1 of the column latch CL is set to logic "1" and the output signal of the corresponding inverter V1 is set to the low level, the output signal of the inverter V3 becomes internal. It becomes a high level like the voltage VPP. Therefore, the MOSFET P1 of each unit circuit of the write circuit WC
Are turned off, and the corresponding bit lines B0 to Bn of the memory array MARY are set to a non-selection level such as the ground potential VSS via a path (not shown).

When the flash memory FROM is set to the selected state in the write mode, the word lines W0 to Wm of the memory array MARY are alternatively set to a selection level such as -9 V as described above, and the source line S0 is set. Sp is in an open state. At this time, in the (n + 1) memory cells MC coupled to the selected word line of the memory array MARY, writing is selectively performed on the condition that the corresponding bit lines B0 to Bn are at a selection level such as + 6V. The electrons accumulated in the floating gate are selectively extracted to the drain side, and the threshold voltage is lowered.

Next, the sense amplifiers SA are provided corresponding to the bit lines B0 to Bn of the memory array MARY.
+1 or 1,024 unit circuits are provided, and each of these unit circuits is not particularly limited.
As shown in FIG. 3, one unit sense amplifier UA and P
And a channel-type switch MOSFET P3. The input node of the unit sense amplifier UA constituting each unit circuit is connected to the memory array M via the switch MOSFET P3.
ARY are coupled to corresponding bit lines B0 to Bn, and their inverted output nodes are connected to N channel M of column latch CL.
Coupled via OSFET N2 to an input / output node above corresponding latch circuit L1. A read control signal RC is commonly supplied from the memory controller MC to the gate of the MOSFET P3 that constitutes each unit circuit of the sense amplifier SA.

The read control signal RC is set to a high level like the normal power supply voltage VCC, and when the flash memory FROM is selected in the read mode,
At a predetermined timing, it is selectively set to a low level such as the ground potential VSS.

When the flash memory FROM is selected in the read mode, the word lines W0 to Wm of the memory array MARY are alternatively set to +2.5
V, and all the source lines S0 to Sp are at a low level such as the ground potential VSS. At the beginning of the read operation, the bit lines B0 to Bn of the memory array MARY are simultaneously precharged to a high level such as the power supply voltage VCC by a precharge circuit (not shown) of the sense amplifier SA. The precharge levels of these bit lines B0 to Bn are selectively set on condition that memory cell MC arranged at the corresponding intersection with the selected word line is in a write state and its threshold voltage is relatively low. It is pulled out and falls.

The selective lowering of the levels of the bit lines B0 to Bn is sensed and amplified by the unit sense amplifier UA of the corresponding unit circuit of the sense amplifier SA, and in response to this, the inverted reading at the inverted output node of the unit sense amplifier UA is performed. Data is selectively set to high level. These inverted read data are received by the corresponding latch circuit L1 of the column latch CL in response to the high level of the latch control signal LC2, and are inverted to become non-inverted read data.
It is selectively output in units of 32 bits.

Incidentally, the memory cell MC of the two-layer gate structure forming the memory array MARY has its write / read
Since the erase characteristics exhibit relatively large variations, the above-described 128-byte write and block erase operations are performed while confirming changes in data held in the memory cells MC after the write or erase operation, that is, logic “ Check whether the memory cell MC in the erase state of "1" has changed to the write state of logic "0", or the memory cell MC in the write state of logic "0" has changed to the erase state of logic "1". It is repeated while doing. Further, in the flash memory FROM of this embodiment, prior to the erasing operation, a pre-write method is adopted in which all the memory cells MC to be erased are brought into a writing state. In this embodiment, the flash memory FRO
As described above, the control necessary for the write / erase operation of M is mainly performed by software by the central processing unit CPU, and has several features, which will be described in detail below.

FIG. 4 shows a basic flow chart of the first embodiment at the time of writing to the flash memory of the microcomputer of FIG. 1, and FIG. 5 illustrates the operation at the time of writing to the flash memory of FIG. FIG. 3 is a conceptual diagram of the operation of one embodiment. FIG. 6 is a basic flowchart of one embodiment of the absurd write determination processing at the time of writing to the flash memory in FIG. 4, and FIG. FIG. 3 is a conceptual diagram of the operation of one embodiment. Further, FIG. 8 shows a processing flow diagram of an embodiment of the central processing unit of the microcomputer which adopts the basic flow of FIG. With reference to these drawings, a specific operation and characteristics of the microcomputer of this embodiment when writing to a flash memory will be described. In the microcomputer of this embodiment, data processing is performed in units of 32 bits, that is, in units of 4 bytes, as described above.
Only eight bits, that is, one byte are illustrated.

In FIG. 4, the write operation in the flash memory FROM of this embodiment is performed in step S11.
1 starts with the write data WD generation process. As described above, the memory array M of the flash memory FROM
The two-layer gate structure type memory cell MC configuring ARY is
When it is in the erased state, as shown at the top of FIG. 5, all data of logic "1" are held. As described above, the substantial write operation in the flash memory FROM is performed in units of substantially 1,024 bits, that is, in units of 128 bytes.
D is generated in units of 32 bits, and data of logic "0" is selectively allocated to bits to be written, as illustrated in the second row of FIG. Needless to say, data of logic “1” is assigned to a bit that is not to be written at the designated address, that is, a bit that is to be kept in the erased state, and write data WD is assigned data of logic “1” and “0”. Data is often mixed.

The write data WD generated in step S111 is logically inverted for each bit in step S112 to generate bit-inverted data, that is, inverted write data WDI. This inverted write data WDI
In FIG. 5, as illustrated in the third row of FIG. 5, the bit to be written at the designated address is set to logic “1”, and the bit not to be written is set to logic “0”.

Write data WD and inverted write data W
When the generation of the DI is completed, first, in step S113, after the held data RD of the specified address is read,
In step S114, an absurd writing determination process is performed. As described above, each bit of the read data RD read from the specified address is set to the logic "1" when the corresponding memory cell MC is still in the erased state, and is set to the logic "0" when the corresponding memory cell MC is already in the written state. .
Therefore, the read data RD obtained by the first read after erasing is, as illustrated in the fourth row of FIG.
All the bits are set to logic "1". Step S
The necessity of the absurd write determination processing by 114 and its effect will be described later in detail.

If no abnormality is detected by the absurdity determination process in step S114 and the determination result is yes, in step S115, the logical product of the inverted write data WDI and the read data RD is calculated for each bit, and the logical product data WDA is calculated. Generated. Needless to say, the logical product data W
Each bit of DA is selectively set to logic "1" on condition that both corresponding bits of inverted write data WDI and read data RD are logic "1", and is set to logic "0" under other conditions. You. Therefore, the logical product data WDA generated based on the first read data RD after erasing and the inverted write data WDI has each bit of the inverted write data WDI as illustrated in the fifth row of FIG.
Has the same logical value as the corresponding bit of.

In the logical product data WDA generated in step S115, it is determined whether or not all the bits of the logical product data have become logical "0" in step S116, that is, all the bits to be written after the write operation is completed are logical "0". Is determined whether or not it has changed. As a result,
If all the bits of the logical product data WDA change to logical "0", the write operation to the designated address is completed and the process proceeds to another process. If any of the bits is still logical "1", In step S117, the rewrite data WDR to be rewritten to the specified address is generated by inverting the bit of the logical product data WDA in step S117. This rewrite data WDR is written to the designated address in step S118, and thereafter, in step S1
Returning to 13, a processing loop is formed. The rewrite data WDR generated based on the first read data RD and the logical product data WDA after the erasure is the write data WD itself, as exemplified in the sixth row of FIG.

At the designated address of the memory array MARY having completed the write operation in step S118, as exemplified in the seventh row of FIG. 5, the logical values of the first and second bits and the fourth to eighth bits thereof Is the rewrite data W
Although the logical value is changed to the logical value corresponding to the corresponding bit of DR, the third bit remains at the logical "1", that is, the erased state, because the threshold voltage of the corresponding memory cell MC does not become sufficiently low. . Therefore, in the read operation in step S113 of the second loop, the third bit of the read data RD also becomes logical “1” as illustrated in the eighth row of FIG. 5, and the new logical product data obtained in step S115 is obtained. As illustrated in the ninth row of FIG. 5, only the third bit of the WDA becomes logic “1”.

Thus, step S1 of the second loop is executed.
In the rewrite data WDR generated by No. 17, only the third bit becomes logic "0" and the other bits become logic "1", as exemplified in the tenth row of FIG. This rewrite data WDR is stored in step S1.
18, the third bit of the specified address is changed to logic “0” as illustrated in the eleventh stage of FIG. 5, and all the bits match the write data WD. It will be in the state of having done.

The data held at the designated address is read out as read data RD in step S113 of the third loop, and then, in step S115, logical product with inverted write data WDI is obtained to form logical product data WDA. As is apparent from the above description, the logical product data WDA generated in step S115 in the third loop
As illustrated in the thirteenth stage of FIG. 5, all the bits become logic "0", so that the condition of step S116 is satisfied and the writing is completed.

As described above, in the microcomputer of this embodiment, the read data RD read from the specified address of the flash memory FROM in step S113 is replaced with the inverted write data W in step S115.
The logical product data WDA is supplied to the DI and the logical product data WDA is used to determine the end of the write operation in step S116 and to generate the rewrite data WDR in step S117. That is, in this embodiment, the end of the write operation is determined based on the logical product data WDA of the read data RD obtained by one read operation in step S113 and the inverted write data WDI, and the rewrite data is determined. In particular, even when the threshold voltage of a memory cell is in a fluctuation region and there is a bit whose logical value changes every time a read operation is performed, the occurrence of rewriting is suppressed. However, the occurrence of an infinite loop due to the repetition can be suppressed.

As a result, it is possible to prevent the time required for writing in the flash memory FROM from being unintentionally increased, and to improve the writing characteristics of the flash memory FROM. , Speeding up the processing and increasing the efficiency of the processing.

By the way, in the determination process of the absurd writing performed in step S114 of FIG. 4, there is no particular limitation. First, as shown in the dotted frame of FIG. After the bit inversion data, that is, the inverted read data RDI, is generated, in step S142, the logical product of the write data WD and the inverted read data RDI is calculated to generate the logical product data RDA. Logical product data RDA
In step S143, it is determined whether all bits are logical "0". If all bits are logical "0", it is determined that there is no abnormality, and the process proceeds to step S115 and subsequent steps. However, if any of the bits of the logical product data RDA is logic “1” in step S143, it is determined that an abnormality has occurred, and the write operation is interrupted.
Move on to error handling.

That is, each bit of the logical product data RDA obtained as a result of the processing in step S142 is such that the corresponding bit of the designated address is already in the write state and the corresponding bit of the read data RD is logical "0". Regardless, when the corresponding bit of the write data WD is the logic “1” corresponding to the erased state, that is, when the absurd writing is designated, the logic is selectively set to the logic “1”. In addition, although there was no designation of absurd writing, for example, as shown in FIG.
3, when the read result of the second bit of the specified address is arranged in the same column, that is, changes to logic "0" under the influence of another bit in the depletion error state coupled to the same bit line Also selectively becomes logic "1".

As described above, in the microcomputer and the flash memory FROM of this embodiment, prior to writing the designated address, the absurdity of the write data WD is identified, the write operation is interrupted, and the normality of the held data is , And even after a write operation to a specified address is started, a depletion error of another memory cell arranged in the same column as the specified memory cell can be detected. It is possible to further enhance the reliability of the FROM and, further, the microcomputer in which the FROM is mounted.

In the microcomputer of this embodiment, as described above, the write operation of the flash memory FROM is actually executed in units of 128-byte sectors, and the above-described series of processing relating to the write operation of the designated sector is performed. Is performed by software mainly by the central processing unit CPU. For this reason, in the central processing unit CPU, specific processing proceeds according to the procedure illustrated in FIG. 8, and the writing operation is performed according to the basic flow in FIG.

That is, the central processing unit CPU first edits the specified address, that is, the sector write data WDS in the unit of 128 bytes to be written in the specified sector in step S211. In the next step S212, the sector write data WDS is bit-inverted. To generate inverted sector write data WDIS. Step S
After reading the holding data RDS of the specified sector in sector units according to 213, an absurd write determination is performed based on the sector read data RDS and the sector write data WDS in step S214. Step S2
Actually, the generation of the sector write data WDS and the inverted sector write data WDIS, the reading of the sector read data RDS, and the absurd write determination process in steps S11 to S214 are performed using 32 bits, that is, 4 bytes, which are the operation processing unit of the central processing unit CPU. Although the unit is repeated 32 times, it is simplified.

The central processing unit CPU, which has normally completed the absurd write determination processing of step S214, proceeds to step S215 to execute the inverted sector write data WDI.
After inputting 4B of S, that is, 4 bytes, to the register REG1, in step S216, the sector read data R
The corresponding 4 bytes of DS are input to the register REG2. Also, in step S217, the register REG1
And REG2, that is, the inverted sector write data W
The logical product of the corresponding 4 bytes of the DIS and the sector read data RDS is taken, and the processing result, that is, the logical product data, is input to the register REG3. Is determined.

As a result, if any bit of the contents of the register REG3, that is, the logical product data is logical "1", the central processing unit CPU inverts the contents of the register REG3, that is, the logical product data, in step S222. After the sector rewrite data WDRS is generated for 4 bytes, it is determined in step S223 whether the processing for one sector, that is, 128 bytes has been completed. If the processing for one sector has not been completed yet, the central processing unit CPU returns to step S214 to repeat the processing for the next 4 bytes, and if the processing for one sector has been completed, the processing proceeds to step S224.
Then, after confirming whether the number of times of writing for the sector exceeds a predetermined value, in step S225, the edited rewrite data WDRS for one sector is written to the designated sector of the flash memory FROM. When the number of times of writing exceeds a predetermined value in step S224, the central processing unit CPU performs predetermined error processing.

On the other hand, in step S218, the register RE
When the content of G3, that is, the logical product data becomes logical "0" for all bits, the central processing unit CPU proceeds to step S2.
After writing the logical "0" into the corresponding bit of the register REG4 by 19, it is determined in step S220 whether the processing for one sector, that is, 128 bytes has been completed. If the processing for one sector has not been completed yet, the process returns to step S214 to repeat the processing for the next 4 bytes, and if the processing for one sector has been completed, the process returns to step S221.
It is determined whether all bits of EG4 have become logic "0".

The register REG4 has 32 bits each corresponding to 4 bytes of the sector write data WDS and 4 bytes of the sector read data RDS, and the central processing unit CPU determines when the write operation for one sector is started. , Write logic "1" to all bits of the register REG4 in advance. As described above, each bit of the register REG4 is the content of the register REG3, that is, all the bits of the corresponding 4-byte logical product data of the inverted sector write data WDIS and the sector read data RDS are logical "0", that is, the sector. When the end of the write operation for the corresponding 4 bytes of the write data WDS is confirmed, each is rewritten to logic "0". Therefore, in step S221, the fact that all the bits of the register REG4 have become logical "0" indicates that all the writing relating to the 128-byte sector write data WDS has been completed.

Therefore, in step S221,
When the central processing unit CPU determines that any bit of the register REG4 is logic “1”, the process proceeds to step S224 to write the sector rewrite data WDRS, but all the bits of the register REG4 are logic “0”. If it is determined that the write operation has been completed, the process for writing the sector write data WDS to the designated sector is terminated.

As described above, in the microcomputer according to the present embodiment, a series of processes relating to the writing operation of the flash memory FROM is mainly performed by software by the central processing unit CPU. At first glance, the processing load on the central processing unit CPU is reduced. I am worried about the increase. However, as described above, the flash memory FROM is for storing a program related to the operation control of the central processing unit CPU, and the flash memory FROM is used for storing the program.
Is performed, it means that the central processing unit CPU and, consequently, the normal processing inherent in the system including the CPU cannot be executed or is in an unnecessary state. Therefore, the central processing unit CPU provides a condition that a control program relating to rewriting of the flash memory FROM is left in, for example, a static RAM or the like.
It can be involved in a series of processes related to the rewriting operation of the flash memory FROM.

A series of processes relating to the writing operation of the flash memory FROM are performed mainly by software by the central processing unit CPU, so that the hardware relating to the writing operation of the flash memory FROM is reduced, and the layout required area, and hence the microcomputer, is reduced. The chip size can be reduced, and the cost of the microcomputer can be reduced. Also, especially during the development period of the microcomputer, the writing procedure can be arbitrarily modified / changed by rewriting the flash memory FROM, thereby shortening the development period of the flash memory FROM and further the microcomputer. .

FIG. 9 shows a basic flow chart of the second embodiment at the time of writing to the flash memory of the microcomputer of FIG. FIG. 10 is an operation conceptual diagram of one embodiment for explaining the operation at the time of writing to the flash memory of FIG. 9, and FIG. 11 is an embodiment of a central processing unit taking the basic flow of FIG. An example process flow diagram is shown. This embodiment basically follows the embodiment shown in FIGS. 4 to 8, and therefore, a description will be added only for portions different from the embodiments.

In FIG. 9, the write data WD generated in step S311 is bit-inverted in step S312 to become inverted write data WDI.
This inverted write data WDI is further transmitted to step S31.
3, the write history data WD is used as it is with the logical value.
H. Needless to say, the initial write history data WDH generated in step S313 is
As shown in the third row of FIG.
I itself.

Next, in step S314, the read data RD read from the specified address of the flash memory FROM is subjected to the logical AND operation with the write history data WDH in step S316 after the determination of the absurd write in step S315. Is obtained and becomes logical product data WDA. The logical product data WDA is further updated by the new write history data WD in step S317.
However, as described above, the initial write history data WDH is the inverted write data WDI itself, and the logical product data WDA of the first loop is inverted as shown in the fifth stage of FIG. Since the write data WDI itself is used, each bit of the new write history data WDH generated in step S317 also retains the previous logical value as illustrated in the sixth row of FIG. .

The logical product data WDA generated in step S316 determines whether all the bits have become logical "0" in step S318, that is, all bits to be written after the write operation is completed have logical "0". Is determined to have changed to "". As a result,
When all the bits of the logical product data WDA have changed to logical “0”, it is determined that the write operation to the specified address has been completed, and the process proceeds to another process. However, if any one of the bits is still logic "1", the process proceeds to step S3.
19, the logical product data WDA is bit-inverted to generate the rewrite data WDR. Then, in step S320, the rewrite data WDR is written to the specified address, and the process returns to step S314.

At the designated address of the memory array MARY after the write operation in step S320, FIG.
As shown in the eighth row of FIG. 10, only the third bit has not been written yet and remains in the logic "1", that is, remains in the erased state. , The third bit of the read data RD becomes logic “1”. Therefore, in the new logical product data WDA obtained in step S316, only the third bit of the logical product data becomes logical "1" as illustrated in the tenth stage of FIG. WDH is also, as exemplified in FIG.
Again, only the third bit becomes logic "1".

Thus, step S3 of the second loop is executed.
19 is the rewrite data WDR generated in FIG.
As shown in the twelfth stage, only the third bit becomes logic "0" and the other bits become logic "1". This rewrite data WDR is written again to the designated address in step S320, and as a result, the third bit of the designated address changes to logic "0" as exemplified in the thirteenth stage of FIG. The bit is in a state where it matches the write data WD.

When the threshold voltage of the memory cell MC of the two-layer gate structure constituting the memory array MARY is in the fluctuation region, the corresponding bit of the read data RD changes from logic "0" to "0" every time a read operation is performed. In some cases, the state changes from "1" or logic "1" to "0".
This causes an abnormality in the determination processing in step S318, causing an undesired increase in the writing time and the occurrence of an infinite loop.

In the case of this embodiment, for example, the memory cell MC corresponding to the fourth bit of the read data RD is in the fluctuation region, and as shown in the fourteenth stage of FIG. The fourth bit of the read data RD has changed to logic "1" in step S314 of the third loop, and has been erased.

In the embodiment of FIG. 4, however, the logical product data WDA is generated on the basis of the read data RD and the inverted write data WDI. Since the data is generated based on the data RD and the write history data WDH, in step S316 in the third loop, the fourth bit of the logical product data WDA remains at logical “0”, and the write is completed.

That is, in the case of this embodiment, the write history data WDH is initially generated as the inverted write data WDI itself. The bit corresponding to the memory cell MC once in the write state changes to logic "0". In other words, each bit of the write history data WDH indicates that the corresponding memory cell MC is a write target bit, and indicates a history that the corresponding memory cell MC has been once rewritten to logic “0”. However, as long as the rewrite data WDR is generated based on the write history data WDH and the read data RD, no rewriting is performed on the memory cell MC once rewritten.

As a result, the memory cell MC in the written state is
Due to overwriting where rewriting is repeated for
It is possible to reliably prevent the threshold voltage of the memory cell from becoming too low, causing a depletion failure, or preventing the variation in the threshold voltage of the memory cell MC from increasing.
As a result, the reliability of the flash memory FROM and thus the microcomputer can be improved.

In the microcomputer of this embodiment, as in the embodiment of FIG. 4, the write operation of the flash memory FROM is actually executed in units of 128-byte sectors, and the write operation of the designated sector is performed. A series of processing is mainly performed by software by the central processing unit CPU. Therefore, in the central processing unit CPU, specific processing proceeds according to the procedure shown in FIG. 11, and the writing operation is performed according to the basic flow of FIG.

That is, the central processing unit CPU first edits the sector write data WDS in units of 128 bytes to be written to the designated sector in step S411, and inverts the bits of the sector write data WDS in the next steps S412 and 413. To generate inverted sector write data WDIS and write history data WDHS. Further, after reading the held data RDS of the specified sector in sector units in step S414, it is determined in step S415 whether or not the writing is abnormal based on the sector read data RDS and the sector write data WDS.

The central processing unit CPU, which has normally completed the absurd write determination processing in step S415, inputs 4 bytes of the write history data WDHS to the register REG1 in the next step S416.
At 17, the corresponding 4 bytes of the sector read data RDS are input to the register REG2. In step S418, the contents of the registers REG1 and REG2, that is, the logical product of the corresponding 4 bytes of the write history data WDHS and the sector read data RDS are obtained, and the processing result, that is, the logical product data is input to the register REG3. By S419, new write history data WDHS is set. Further, step S4
20, it is determined whether or not the register REG3 has become all-bit logic "0". According to the result, the rewrite data WD in steps S424 to S427 is selectively selected.
An RS generation process and a write process are executed. And
In step S423, logic “0” of all bits of the register REG4 is determined, and the write operation for the sector write data WDS is completed.

As described above, by performing a series of processes related to the writing operation of the flash memory FROM mainly by software by the central processing unit CPU, hardware related to the writing operation of the flash memory FROM can be reduced, and the cost of the microcomputer can be reduced. The development time of the flash memory FROM and, consequently, the microcomputer can be shortened.

FIG. 12 shows a basic flowchart of one embodiment of the microcomputer shown in FIG. 1 when erasing the flash memory. The outline of the flash memory erasing operation of the microcomputer of this embodiment and its features will be described with reference to FIG. Note that this embodiment basically follows the embodiment of FIG. 1 to FIG. 8 or FIG. 9 to FIG. This is performed by software by the CPU. The erasing operation of the flash memory FROM is selectively performed by designating a block including a predetermined number of sectors, or performed collectively for all addresses.

In FIG. 12, the erasing operation of the flash memory FROM in the microcomputer of this embodiment is started by generating the write data WD in step S511. In this step S511, logic "0" is applied to all the memory cells MC of the address to be erased.
Is written to generate the write data WD. In step S512, the write data WD generated in step S511 is prewritten to the designated address of the flash memory FROM in units of sectors, and in step S5
It is determined by 13 whether or not pre-writing to all the sectors to be erased has been completed. As a result, when the end of the prewrite to all the sectors is confirmed, step S51 is performed.
In steps 4 and S515, for example, the erasing operation in units of blocks is repeated, and when erasure of all blocks is confirmed, the erasing process ends.

In this embodiment, the prewriting in steps S512 and S513 is performed according to the basic flow of FIG. 4 or FIG. Therefore, the write operation to the two-layer gate structure type memory cell MC constituting the memory array MARY of the flash memory FROM is stopped when each memory cell MC has at least once been in the write state, and the pre-written memory cell MC Are written in a substantially averaged state. For this reason, even though the erasing operation in steps S514 and S515 is performed in units of a block including a relatively large number of memory cells MC, these memory cells MC can be in an average erased state. As a result, a specific memory cell MC is prevented from being in a so-called over-erased state,
Deterioration of the memory cell MC can be prevented, and thereby the reliability of the flash memory FROM and thus the microcomputer can be improved.

FIG. 13 is a partial circuit diagram showing another embodiment of a memory array MARY and peripheral portions included in a flash memory of a microcomputer to which the present invention is applied. In this embodiment, the basic flow of FIG. 9 is realized by hardware mainly by the related circuits of the flash memory, and the load on the central processing unit of the microcomputer is reduced accordingly. 13, those having the same reference numerals as those in FIG. 3 generally correspond to each other as they are. Further, in this embodiment, the hardware corresponding to the absurd write determination processing in step S315 in FIG. 9 is not included, but it can be included as necessary. Less than,
A description will be added for parts different from FIG.

In FIG. 13, column latch CL is not particularly limited, but bit line B of memory array MARY is not limited to column latch CL.
N + 1 provided corresponding to 0 to Bn, that is, substantially 1,
024 unit circuits, each of which includes a latch circuit L1 formed by cross-coupled inverters V1 and V2, another latch circuit L2 formed by cross-coupled inverters V4 and V5, And a two-input AND gate G1 for receiving output signals of the latch circuits L1 and L2. In addition, column latch C
L is substantially 1,02 provided in common to all unit circuits.
And a 4-input AND gate G2.
The input / output nodes below the latch circuit L1 of each unit circuit are respectively coupled to each of the input terminals 2. Needless to say, the AND gate G2 does not consist of one logic gate, but is a 1,024-input AND gate G2 by combining many logic gates.

An input / output node below the latch circuit L1 of each unit circuit of the column latch CL is a switch MOSFET.
Through N1, they are coupled to corresponding data input / output lines D0 to Dn, that is, data input / output circuit IO, and are also coupled to corresponding input terminals of AND gate G2. The input / output node above it is an AND gate G
1 and the input terminal of the inverter V3 of the corresponding unit circuit of the write circuit WC, and furthermore, an N-channel type switch MOSF
Each is coupled to the corresponding output terminal of AND gate G1 via ETN4. The gate of the switch MOSFET N1 is commonly supplied with a latch control signal LC1 from a memory controller MC (not shown).
A latch control signal LC4 is commonly supplied to the gate of the FET N4.

The latch control signal LC1 is normally set at a low level such as the ground potential VSS, and when the flash memory is selected in the write mode, the write data is input from the data input / output circuit IO via the Y gate circuit YG. Is selectively set to a high level such as the power supply voltage VCC at a predetermined timing. The latch control signal LC4 is also normally at a low level, and when the flash memory is selected in the write mode, AND data of read data and inverted write data or write history data is generated by the AND gate G1. At a predetermined timing, in other words, at a timing corresponding to the end of step S316 of the basic flow in FIG.

On the other hand, the input / output nodes below the latch circuit L2 of each unit circuit of the column latch CL are connected to the corresponding data input / output lines D0 to Dn, that is, the data input / output circuit IO via the N-channel type switch MOSFET N3. And an input / output node connected to the left input terminal of the AND gate G1.
It is coupled to the inverting output node of the corresponding unit sense amplifier UA of the sense amplifier SA via the SFET N2. A latch control signal LC2 is commonly supplied from the memory controller MC to the gate of the switch MOSFET N2, and a latch control signal LC3 is commonly supplied to the gate of the switch MOSFET N3.

The latch control signal LC2 is normally set at a low level such as the ground potential VSS, and when the flash memory is selected in the read mode, the output level of the corresponding unit sense amplifier UA is determined. At the timing, it is selectively set to a high level like the power supply voltage VCC. The latch control signal LC3 is also normally set to the low level, and when the flash memory is set to the selected state in the read mode, the read data at the specified address is selectively set high at a predetermined timing to be transmitted to the data input / output circuit IO. Level.

Hereinafter, the write operation of the flash memory of this embodiment will be specifically described in association with each processing step of the basic flow of FIG.

First, the write data WD generated in step S311 of FIG. 9 is supplied from the data input / output circuit IO to the Y gate circuit YG and the corresponding 32 bits of the data input / output lines D0 to Dn in column units of 32 bits. It is supplied to the latch CL. These write data WD are:
Via the switch MOSFET N1 which is turned on in response to the high level of the latch control signal LC1, it is sequentially taken in and held by the latch circuit L1 of the corresponding unit circuit of the column latch CL.

Needless to say, the data input / output lines D0 to D
n, ie, the latch circuit L of each unit circuit of the column latch CL
As for each bit of the write data WD at the input / output node below 1, the bit corresponding to the memory cell MC to be written is set to logic "0", that is, a low level such as the ground potential VSS, and all other bits are set to logic. “1”
That is, it is set to a high level like the power supply voltage VCC. Further, each bit of the write data WD held in the latch circuit L1 is inverted at the output terminal of the inverter V1 to become inverted write data WDI after step S312 in FIG. 9 and write history data WDH after step S313. Become.

Next, in step S314 in FIG. 9, the data is read out from the designated address of the memory array MARY in units of 1,024 bits, that is, in units of 128 bytes.
The read data RD, which is logically inverted and established at the inverted output node of the corresponding unit sense amplifier UA of A, is set via the switch MOSFET N2 of the column latch CL which is turned on in response to the high level of the latch control signal LC2.
The data is simultaneously taken into the corresponding latch circuit L2, and the non-inverted read data R is output from the output terminal of the inverter V5.
D. These read data RDs are ANDed with the corresponding bits of the write history data WDH held in the latch circuit L1 by the corresponding AND gate G1, respectively, and the logical product data WDA after step S316 in FIG. Become. The switch MOSFET which is turned on in response to the high level of the latch control signal LC4
It is taken into the corresponding latch circuit L1 via N4,
New write history data WDH after step S317
Becomes

The write history data WDH, that is, logical product data WDA fetched by the latch circuit L1, is inverted at the input / output node below each latch circuit L1, supplied to the corresponding input terminal of the AND gate G2, and logical product. Is taken. This AND gate G2 corresponds to the determination processing of step S318 in FIG. 9, and its output signal WDA0 indicates that all the bits of the logical product data WDA held in the latch circuit L1 are logical "0". And selectively set to a high level. The output signal WDA0 of the AND gate G2 is supplied to the memory controller MC of the flash memory, and in response to the high level, the end of the write is determined.

On the other hand, write history data WDH, that is, logical product data WDA taken into latch circuit L1 becomes rewrite data WDR at an input / output node below each latch circuit L1. Then, the rewrite data WD
On the condition that the corresponding bit of R is set to logic “0”, that is, on the condition that the corresponding bit of AND data WDA is logic “1”, that is, high level, the corresponding unit of the write circuit WC The MOSFET P1 of the circuit is selectively turned on, and writing to the corresponding memory cell MC of the memory array MARY is selectively performed.

As described above, in the microcomputer of the present embodiment, a series of processes related to the write operation of the flash memory is mainly performed by the related circuits of the flash memory, that is, the column latch CL, the write circuit WC, and the sense amplifier SA in hardware. This is performed, and the central processing unit hardly participates other than the generation of the write data WD and the data transfer in units of 32 bits. For this reason, for example, in the case where the writing of the flash memory is performed in the middle of the normal processing of the central processing unit and partially performed,
With a relatively small amount of additional hardware and relatively fast,
It becomes possible to partially rewrite a flash memory or the like.

The functions and effects obtained from the above embodiments are as follows. That is, (1) In a non-volatile memory such as a flash memory mounted on a single-chip microcomputer or the like, a logical product of read data read from a specified address and bit-inverted data of write data to be written therein is determined based on logical product data. At the same time, the end of the write operation to the designated address is determined, and the rewrite data to be rewritten to the designated address for which the write has not been completed is generated based on the same logical product data, thereby making one write operation. Based on the read data obtained by the read operation,
Since the end of the write operation can be determined and the rewrite data can be generated, an infinite loop is suppressed, particularly when the threshold voltage of the memory cell is in the fluctuation region, and an undesired increase in the time required for writing the flash memory or the like is prevented. It is possible to obtain an effect that the writing characteristics can be improved while suppressing the writing.

(2) In a nonvolatile memory such as a flash memory mounted on a single-chip microcomputer or the like, write data to be written to a designated address,
Alternatively, the end of the write operation to the specified address is determined based on the logical product data of the write history data obtained by bit-reversing the rewrite data for the specified address for which writing has not been completed and the read data read from the specified address. In addition, by generating rewrite data based on the same logical product data, it is possible to prevent rewriting of such a memory cell even when the memory cell once in the written state is in the erased state. Therefore, the infinite loop, particularly when the threshold voltage of the memory cell is in the fluctuation region, is more reliably eliminated.
In this way, it is possible to reliably prevent an undesired increase in the required writing time of a flash memory or the like, and to improve the writing characteristics.

(3) In the above item (1) or (2), a series of processes relating to a write operation of a flash memory or the like is applied to a flash memory or the like having a prewrite function, so that a memory cell to be erased is obtained. And the erasing characteristics can be improved.

(4) In the above items (1) to (3),
By performing an absurd write determination process based on logical product data of write data to be written to the specified address and bit-inverted data of read data read from the specified address, an absurd write to an already written bit of the specified address Can be prevented, and a depletion error can be identified, whereby the reliability of data held in a flash memory or the like can be improved.

(5) In the above items (1) to (4),
A series of processes related to the writing operation of the flash memory or the like is realized as software by a central processing unit mounted on a microcomputer or the like, so that it is not used for normal processing while writing to the flash memory or the like is performed. By utilizing the central processing unit, the amount of hardware of the flash memory can be reduced, the chip size of the microcomputer or the like can be reduced, and the cost can be reduced.

(6) In the above items (1) to (4),
A series of processes related to a write operation of a flash memory or the like is realized by hardware using a related circuit such as a flash memory, so that a relatively small amount of hardware is added, the speed is relatively high, and the central processing unit is used by another central processing unit. An effect is obtained that partial rewriting of the flash memory or the like can be performed during the processing.

(7) According to the above items (1) to (6), the reliability of the flash memory and the like and the single-chip microcomputer including the same are enhanced, and the speed, cost and processing efficiency are improved. The effect that it can be obtained is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the single-chip microcomputer does not necessarily need to include all the illustrated functional blocks, and may include various other functional blocks. The block configuration, the bus configuration, and the like of the single-chip microcomputer can take various embodiments without being restricted by this embodiment.

In FIG. 2, a flash memory FROM
Can have an arbitrary bit configuration such as, for example, × 8 bits or × 16 bits.
Can be divided into a plurality of memory mats including its direct peripheral circuits. The storage capacity of the flash memory FROM can be arbitrarily set, and the same applies to the block configuration. 3 and 13, the memory array MARY can include an arbitrary number of redundant elements, and the absolute numbers of the word lines and the bit lines can be arbitrarily set. The specific circuit configuration of the write circuit WC, the sense amplifier SA, and the column latch CL, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, the effective level of each control signal, and the like can take various embodiments.

In FIG. 4, FIG. 6, FIG. 8, FIG. 9, FIG. 11, and FIG. 12, a specific processing flow at the time of writing / erasing of the flash memory FROM is, for example, the order is changed or the logical value is changed. Various forms may be considered.

In the above description, mainly the case where the invention made by the present inventor is applied to a flash memory as a background of application and a single-chip microcomputer equipped with the same is described. For example, the flash memory and the central processing unit are formed on separate semiconductor substrate surfaces, the flash memory is formed as a single unit, or various types of memory integrated having similar write / erase functions. The present invention is also applicable to circuit devices and various digital systems equipped with the same. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a nonvolatile memory including a memory array in which at least two-layer gate structure type memory cells are arranged in a lattice, and a system including the same.

[0132]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a non-volatile memory such as a flash memory mounted on a single-chip microcomputer or the like, a designated memory is designated based on logical product data of read data read from a designated address and bit inversion data of write data to be written therein. The end of the write operation for the address is determined, and the rewrite data to be rewritten for the specified address for which the write has not been completed is generated based on the same logical product data. Since the end of the write operation can be determined based on the obtained read data and rewrite data can be generated, the infinite loop is suppressed particularly when the threshold voltage of the memory cell is in the fluctuation region, and the flash memory is controlled. It is possible to suppress an undesired increase in the time required for writing to a memory or the like. Rutotomoni, it is possible to improve the writing characteristic such as a flash memory.

In a nonvolatile memory such as a flash memory mounted on a single-chip microcomputer or the like, write history data obtained by bit inversion of write data to be written to a specified address or rewrite data for a specified address for which writing has not been completed. The end of the write operation is determined based on the logical product data of the read data read from the specified address, and the rewrite data is generated based on the same logical product data, thereby temporarily changing the write state. Even if a lost memory cell enters the erased state again, rewriting to such a memory cell can be prevented, so that an infinite loop, particularly when the threshold voltage of the memory cell is in the fluctuation region, is further ensured. Time required for writing to flash memory, etc. It is possible to reliably prevent unintended increase, it is possible to improve the writing characteristic such as a flash memory.

By applying a series of processes relating to the writing operation of the flash memory or the like to a flash memory or the like having a pre-write function and a microcomputer or the like including the pre-write function, a threshold after pre-writing of a memory cell to be erased is obtained. Variation in the value voltage can be suppressed, and the erasing characteristics can be improved.

In the flash memory or the like, an absurd write determination process is performed based on logical product data of write data to be written to a designated address and bit-inverted data of read data read from the designated address, thereby obtaining the designated address. In addition, it is possible to prevent absurd writing of already written bits and to identify a depletion error, thereby improving the reliability of data held in a flash memory or the like.

A series of processes relating to the writing operation of the flash memory or the like is realized by software by a central processing unit mounted on a microcomputer or the like, so that it is used for normal processing while writing to the flash memory or the like is performed. By utilizing the central processing unit which does not need to be used for rewriting the flash memory or the like, the amount of hardware such as the flash memory can be reduced, the chip size of the microcomputer or the like can be reduced, and the cost can be reduced.

A series of processes related to the write operation of the flash memory or the like is realized by hardware using related circuits such as the flash memory, so that a relatively small amount of hardware is added, the speed is relatively high, and the central processing is performed. While the unit is performing other processing, partial rewriting of the flash memory or the like can be performed.

As described above, the reliability of the flash memory and the like and the single-chip microcomputer including the same can be improved, and the speed, the cost and the processing efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a microcomputer to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a flash memory included in the microcomputer of FIG. 1;

FIG. 3 is a partial circuit diagram showing one embodiment of a memory array and a peripheral portion included in the flash memory FROM of FIG. 2;

FIG. 4 is a basic flowchart showing a first embodiment at the time of writing to a flash memory of the microcomputer of FIG. 1;

FIG. 5 is an operation conceptual diagram showing one embodiment for explaining an operation at the time of writing to the flash memory of FIG. 4;

FIG. 6 is a basic flowchart showing one embodiment of an absurd write determination process at the time of writing to the flash memory of FIG. 4;

FIG. 7 is an operation conceptual diagram showing an example for explaining the operation at the time of the absurd write determination processing of FIG. 6;

FIG. 8 is a processing flow chart showing one embodiment of a central processing unit of the microcomputer which takes the basic flow of FIG. 4;

FIG. 9 is a basic flowchart showing a second embodiment of the microcomputer of FIG. 1 when writing to a flash memory.

FIG. 10 is an operation conceptual diagram showing one embodiment for describing a flash memory write operation of FIG. 9;

FIG. 11 is a processing flowchart showing one embodiment of a central processing unit of the microcomputer that takes the basic flow of FIG. 9;

FIG. 12 is a basic flowchart showing one embodiment of erasing the flash memory of the microcomputer of FIG. 1;

FIG. 13 is a partial circuit diagram showing another embodiment of a memory array and a peripheral portion included in a flash memory of a microcomputer to which the present invention is applied.

FIG. 14 is a basic flowchart showing an example of writing to a flash memory by a microcomputer developed by the present inventors prior to the present invention.

FIG. 15 is a basic flowchart showing another example of writing to a flash memory by a microcomputer developed by the present inventors prior to the present invention.

[Explanation of symbols]

CPU: Central processing unit, CPG: Clock generation circuit, IBUS: Internal bus, PBUS: Peripheral bus,
FROM: Flash memory, SRAM: Static RAM (random access memory), DMAC
… Direct memory access controller, BUSC…
... bus controller, SCI ... serial communication interface, TIM ... timer circuit, D /
A: Digital-to-analog conversion circuit, A / D: analog-to-digital conversion circuit, IOPA to IOPK: input / output port, XTAL: crystal oscillator. MARY: Memory array, XD: X address decoder, SC: Source voltage control circuit, WC: Write circuit, SA: Sense amplifier, CL: Column latch, YG: Y gate circuit, YD: Y Address decoder, CB: Control buffer, MC: Memory controller, AB: Address buffer, DB: Data buffer, IO: Data input / output circuit, VG: Internal voltage generation circuit, VCS:
… Voltage control signal, VCC… power supply voltage, VSS… ground potential. W0-Wm word line, B0-Bn bit line, MC ... two-layer gate structure memory cell, S0-Sp
... source line, VPP ... internal voltage, UA ... unit sense amplifier, D0 to Dn ... data input / output line, WP ... write control signal, RC ... read control signal, LC1
LC4 ... Latch control signal. S111 to S118, S1
41 to S143, S211 to S225, S311 to S3
20, S411 to S427, S511 to S515, S6
11 to S619, S711 to S716 ... processing steps. WD: write data, WDI: inverted write data, WDR: rewrite (rewrite) data, WD
H, WDSH: write history data, RD: read data, RDI: inverted read data, WDA, RDA
...... Logical product data, WDS ...... Sector write data, W
DIS: inverted sector write data, WDRS: sector rewrite data, RDS: sector read data, R
EG1 to REG4 ... registers. L1 to L2... Latch circuits. P1 to P3: P-channel MOSFET, N1
To N4 N-channel MOSFET, V1 to V5
Inverter, G1 to G2 ... AND gate.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 (72) Inventor Yasuyuki Saito Yasuyuki 5-2-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Semiconductor Engineering Division (72) Inventor Isao Iwamoto 3681 Hayano Mobara-shi, Chiba F-term in Hitachi Device Engineering Co., Ltd. 5F083 EP02 EP22 ER03 ER06 ER14 ER15 ER22 ER23 ER30 GA01 GA09 GA30 LA04 LA05 LA07 LA10 LA12 ZA13

Claims (10)

[Claims] 1. A memory array comprising two-layer gate structure type memory cells arranged in a lattice, and bit-inverted data of write data to be written to a specified address of the memory array, and read read from the specified address. Based on the logical product data with the data, it is determined that the write operation to the specified address is completed and the rewrite data to be rewritten to the specified address for which the writing has not been completed is performed. Characteristic nonvolatile memory. 2. A method according to claim 1, further comprising a memory array in which memory cells of a two-layer gate structure are arranged in a lattice, and for write data to be written to a specified address of the memory array or for the specified address for which writing has not been completed. Based on the logical product data of the write history data in which the rewrite data to be rewritten to be rewritten and the read data read from the specified address is determined, the end of the write operation to the specified address is determined. A nonvolatile memory in which the rewrite data is generated. 3. The nonvolatile memory according to claim 1, wherein the non-volatile memory pre-writes, prior to erasing data, information held in all memory cells to be erased so as to be in a written state. A series of processes relating to the write operation of the nonvolatile memory are also performed at the time of the prewrite. 4. The nonvolatile memory according to claim 1, wherein in the nonvolatile memory, write data to be written to a designated address of the memory array and read data bits read from the designated address of the memory array. A non-volatile memory in which an abbreviated write to a previously written bit of the specified address or a determination of a depletion error is performed based on logical product data with inverted data. 5. The nonvolatile memory according to claim 1, wherein the nonvolatile memory is mounted on a single-chip microcomputer. 6. The method according to claim 1, wherein the series of processes related to the write operation of the nonvolatile memory are mainly mounted on the same semiconductor substrate surface. A non-volatile memory, which is performed by software by a central processing unit. 7. The non-volatile memory according to claim 1, wherein the series of processing related to the write operation of the non-volatile memory is mainly performed by a circuit related to the non-volatile memory. A non-volatile memory characterized by being performed by hardware. 8. A nonvolatile memory including a memory array in which two-layer gate structure type memory cells are arranged in a lattice, wherein bit-inverted data of write data to be written to a designated address of the nonvolatile memory and , Based on logical product data with read data read from the specified address,
While determining the end of the write operation for the specified address, generating rewrite data to be rewritten for the specified address for which the write has not been completed,
Alternatively, the write data to be written to the specified address of the nonvolatile memory or the write history data in which the rewrite data to be rewritten to the specified address for which writing has not been completed is bit-inverted, and is read from the specified address. A system for determining, based on logical product data with read data, the end of a write operation for the specified address and generating rewrite data for a specified address for which the write has not been completed. 9. The microcomputer according to claim 8, wherein the system is a microcomputer including a central processing unit, wherein a series of processes related to a write operation of the nonvolatile memory is performed mainly by the central processing unit of the microcomputer. A system characterized by being performed in. 10. The nonvolatile memory according to claim 8, wherein the non-volatile memory pre-writes, prior to an erasing operation, information held in all memory cells to be erased so as to be in a written state. A system according to claim 1, wherein a series of processes relating to the writing operation of said nonvolatile memory is also performed during said pre-writing.