JP2000173275A - Nonvolatile memory and memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the service life of a memory and to enhance the reliability of data by adopting monitor bits that relate to each word line, have a smaller threshold margin than that of signals in other nonvolatile memory cells and reach earlier the end of service life. SOLUTION: A flush memory cell group 13 has a plurality of sectors (corresponding to words), and includes a data area 30 where a plurality of flush memory cell groups used for data read/write are laid out and a management area 40 to manage them. Monitor bits 3a, 3b in a sector 2 are formed in the management area 40 and the monitor bit 3a is referred to as a delete bit and the monitor bit 3b as a write bit. Since the monitor bits 3a, 3b have a smaller threshold margin in a data storage performance than that of memory cells in the data area 30, the data bits reach the end of service life earlier than that of the memory cells in the data area. Thus, the service life of a flush memory can be grasped by detecting occurrence of an error in the monitor bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for simplifying external control of a flash memory, and more particularly to a technique effective when applied to a data processing device such as a computer system.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 2-289997 describes a batch erase type EEPROM (electrically erasable and programmable read only memory). This batch erase type EEPROM can be understood as having the same meaning as the flash memory in this specification. Flash memory is capable of rewriting information by electrical erasing / writing,
(Electrically Programmable Read Only
As in the case of (memory), the memory cell can be composed of one transistor, and has a function of electrically erasing all memory cells or a block of memory cells collectively. Therefore, flash memory is
The stored information can be rewritten in the state of being mounted on the system, the rewriting time can be shortened by the batch erasing function, and the chip occupation area can be reduced.

[0003]

A flash memory has a limit on the number of times of writing. When this limit is reached, normal reading and writing cannot be performed. Ignoring it can lead to data corruption. However, not all sectors (sometimes called words) expire at the same time. Therefore, as a technique for preventing data corruption, for example, a spare sector is formed, and when a sector in which the number of writes reaches the reference value is detected, the sector is replaced with the spare sector. I have. The reference value of the number of times of writing differs depending on the flash memory, but is set to, for example, 300,000 times.

[0004] When the sector in which the number of times of writing reaches the reference value is detected as described above, the inventor of the present application has studied a technique for replacing the sector with the above-mentioned spare sector. Replacement with a life span matching the ability cannot be performed, and a sector with a high ability (long life) wastes due to premature replacement. That was found. In addition, when a defect occurs in a bit for storing the number of times of writing up to the present, even though the number of times of writing has actually reached the reference value, normal replacement cannot be performed.

An object of the present invention is to improve the life of a memory and the reliability of data.

Another object of the present invention is to provide a technique for reliably performing replacement.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a plurality of word lines (WL0 to WL
n), a plurality of nonvolatile memory cells (MC) coupled to the word line, and a threshold margin smaller than other nonvolatile memory cells provided for each word line and used for reading and writing data. As a result, the monitor bit (3
a, 3b) to form a nonvolatile memory.

According to the above means, the monitor bit is
Since the threshold margin is smaller than that of other nonvolatile memory cells used for reading and writing data, the life of the nonvolatile memory cell is earlier than that of other nonvolatile memory cells used for reading and writing data. This makes it possible to perform sector replacement according to the ability of each device, and achieves an improvement in memory life and an improvement in reliability.

At this time, the threshold margin of the monitor bit can be reduced by making the thickness of the floating gate of the monitor bit thinner than the floating gate of another nonvolatile memory cell used for reading and writing data. .

In order to reduce the threshold margin of the monitor bit, the area of the surface facing the control gate of the floating gate of the monitor bit is smaller than that of the floating gate of another nonvolatile memory cell used for reading and writing data. can do.

In order to reduce the threshold margin of the monitor bit, each of the nonvolatile memory cell and the monitor bit has a floating gate for accumulating electric charge, and a thickness of an insulating film surrounding the floating gate of the monitor bit. Should be smaller than the thickness of the insulating film in another nonvolatile memory cell used for reading and writing data.

A plurality of word lines, a plurality of nonvolatile memory cells coupled to the word lines, a monitor bit provided for each word line, and an amount of charge stored and written to the monitor bit are used for reading and writing data. Write control circuit (WC)
ONT) to form a nonvolatile memory.

The monitor bit can set a bias condition such that a large amount of disturbance occurs when writing, erasing, or reading the sector to which the monitor bit belongs or another sector.

A defect detection circuit (4) for detecting a defect based on the read data from the monitor bit can be provided.

The memory system (65) can be constructed by providing a means (65a) for replacing a sector based on the detection result of the defect detection circuit.

[0017]

FIG. 8 shows a data processing apparatus including a flash memory according to one embodiment of the present invention.

Reference numeral 65 denotes a flash memory card formed in a card shape including a plurality of flash memory chips. The flash memory card 65 is not particularly limited, but is provided with a random access memory together with a central processing unit (CPU) 61. A bus 66 to which a memory (RAM) 62 and a read-only memory (ROM) 63 are commonly connected;
It is connected via an interface circuit (I / F) 64. The flash memory card 65 is detachably attached to the data processing device by an appropriate connector. The flash memory card 65 stores various programs executable by the CPU 61, various data, and the like.

When the flash memory card 65 is mounted on the data processing device, the flash memory card 65
1 is accessed. The ROM 63 has a CPU 6
The program executed in step 1 is stored. RAM 62
Is a temporary storage area for data to be processed,
It is used as a work area for the arithmetic processing in 61.

Although not particularly limited, the flash memory card 65 is a JEIDA memory card (type I), that is, a memory card having an interface adapted to the JEIDA memory card interface. Then, the local memory 65b and the card controller 65
a, which are connected by a local bus 65c or the like.
Although not particularly limited, the local memory 65b includes a plurality of flash memories having a configuration of × 1 bit (meaning that the unit of data input / output is 1 bit). The card controller 65a controls the flash memory via an interface compatible with the JEIDA.

FIG. 9 shows a configuration example of the card controller 65a.

As shown in FIG. 9, the card controller 65a is not particularly limited.
(Central processing unit) 652, RAM (random access memory) 653, and ROM (read only memory) 654.

A processing program executed by the CPU 652 is stored in the ROM 654. The RAM 653 is used as a work area for arithmetic processing in the CPU 652. Further, in the RAM 653, an address conversion table which is referred to when a logical address from the system is converted into a physical address of the local memory 65b is formed so as not to use a bad sector in the local memory 65b. This address conversion table is created by the CPU 652 each time the power is turned on to the memory card. When an address signal is input to the control unit 651 in accessing the memory card, the control unit 651 refers to the address conversion table in the RAM 653 to determine a physical address, and thereby accesses the local memory 65b. Further, as will be described in detail later, in the local memory 65b, a failure is detected based on the logic of the monitor bit, and the failure detection signal BAD is transmitted to the control unit 651. . In the control unit 651, the failure detection signal BA
When D is asserted, the non-defective code in the management area of the sector at that time is deleted, and the contents of the address conversion table are rewritten so that another sector is selected instead of the sector.

FIG. 1 shows the flash memory card 65.
Is representatively shown as an example of the configuration of a plurality of flash memories constituting.

Although not particularly limited, the flash memory 10 is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The flash memory 10 has a × 1 bit configuration, and includes a 1-bit data input / output terminal I / O and an output terminal for a failure detection signal BAD.

A flash memory cell group 13 is provided,
As shown in FIG. 14, the flash memory cell group 13 includes a plurality of memory cells MC each formed by an insulated gate field effect transistor having a two-layer gate structure in which a control gate 141 and a floating gate 142 are arranged to face each other. It is arranged in a matrix.

W0 to Wn are word lines, and the control gates of the memory cells MC arranged in the same row are connected to the corresponding word lines.

The selection of the word lines W0 to Wn is performed by the X address decoder XADEC decoding the X address signal AX fetched via the X address latch XALAT. The word driver WDRV selectively drives one of the word lines WL0 to WLn based on a selection signal output from the X address decoder XADEC. In the data read operation, the word driver W
The DRV is operated by using a voltage such as 3V supplied from the voltage selection circuit VSEL and a ground potential such as 0V as power supplies, drives a word line to be selected to a selected level by the voltage Vdd, and is not selected. The word line to be maintained is maintained at a non-selected level such as the ground potential. In a data write operation, the word driver WDRV is operated using a voltage Vpp such as -9V and a ground potential such as 0V as power supplies, and drives a word line to be selected to a high voltage level for writing such as -9V. I do. In the data erasing operation, the output of the word driver WDRV is set to 9V.

9V (or -9V) output from the word driver WDRV or the like is generated by boosting the voltage by the power supply circuit SUPP.

Of the data lines DL0 to DLn, DL0
To DLn-2 are Y selection switches YS0 to YS, respectively.
Commonly connected to a common data line CD via n-2, and further connected to the input / output circuit IOC1 via this common data line CD.

The data lines DLn-1 and DLn are connected to the input / output circuit I via selection switches YSn-1 and YSn, respectively.
It is bound to OC2 and IOC3. Y selection switch YS0
To YSn-2 are controlled by the Y address latch YA.
This is performed by the Y address decoder YADEC decoding the Y address signal AY received via the LAT. The Y selection switches YS-1, YSn are controlled by the output signal of an OR gate OR that obtains the OR logic of the output signal of the switch driver YDRV. For this reason,
When any of the Y selection switches YS0 to YSn-2 is turned on, the Y selection switches YSn-1 and YSn are always turned on. Data lines DLn-1 and DLn are conducted to input / output circuits IOC2 and IOC3.

The output selection signal of the Y address decoder YADEC is supplied to Y selection switches YS0 to YSn-2 via a switch driver YDRV. Y selection switch Y
By setting any one of the output selection signals S0 to YSn-2 to the selection level, one data line is selectively connected to the common data line CD. Here, the memory cells provided at the intersections of the word lines WL0 to WLn and the data lines DLn-1 and DLn have a smaller threshold margin than other nonvolatile memory cells used for reading and writing data. The life of the nonvolatile memory is earlier than that of the other nonvolatile memories.

Data read from the memory cell MC to the common data line CD is applied to the sense amplifier SA via the selection switch RS, amplified there, and output to the data bus via the data output buffer DOB. . The selection switch RS is switch-controlled by a read signal READ.

A predetermined voltage for erasing is applied to data lines DL0 to DL0.
An erase circuit ER for supplying to DLn is provided. The erase circuit ER is controlled by an erase control circuit ECONT. That is, when erasing is performed based on the state of the write / erase register WEREG, the erase control circuit ECO
For example, -7V is applied to the data lines DL0 to DLn by NT.
A predetermined voltage for erasing is supplied.

The input / output circuit IOC1 is configured as follows.

Write data supplied from the outside is supplied to a data input latch DIL via a data input buffer DIB.
Is held. When the data held in the data input latch DIL is "0", the write circuit WR supplies a high voltage for writing to the common data line CD via the selection switch WS. The high voltage for writing is, for example, a voltage such as 7 V, which is the Y selection switches YS0 to YS7.
Is supplied to a drain of a memory cell to which a high voltage is applied to a control gate by a word line through any one of the data lines selected by the data line, whereby the memory cell is written. The selection switch WS is switch-controlled by a control signal WRITE.

The value held by the data latch and the sense amplifier S
A comparison circuit for comparing the output signal of A is provided.
This comparison result is used for erase verification and write verification.

A write operation procedure such as various write timings and voltage selection control is performed by a write control circuit WCO.
NT controls. The write / erase control register WEREG gives a write operation instruction and a write verify operation instruction to the write control circuit WCONT. The control register WEREG can be connected to a data bus, and can write control data from outside.

The input / output circuits IOC2 and IOC3 corresponding to the data lines DLn-1 and DLn have basically the same configuration as the input / output circuit IOC1, but need to take in write data from outside. Therefore, the data input buffer DIB and the data latch DIL are omitted, and the logic of the input terminal of the write circuit WR is fixed. This is to fix the logic of the data written to the monitor bits coupled to the data lines DLn-1 and DLn. Although not particularly limited, the input terminal of the write circuit WR in the input / output circuit IOC2 is pulled up to the high-potential-side power supply Vdd in order to fix the write data to the logical value “1”. Further, in order to fix the write data to the logical value “0”, the input terminal of the write circuit WR in the input / output circuit IOC3 is pulled down to the low potential power supply Vss.

The output signals of the input / output circuits IOC2 and IOC3 are transmitted to the failure detection circuit 4 at the subsequent stage. Although not particularly limited, the failure detection circuit 4 is an exclusive OR. The output signal of the failure detection circuit 4 is a failure detection signal B
AD is transmitted to the card controller 65a.

The control register WEREG has a Vpp bit, a PV bit, a P bit, and an E bit.
The P bit is an instruction bit for a write operation. The E bit is an instruction bit for the erasing operation. When the Vpp bit and the E bit are set, the voltage selection circuit VSEL referring to the Vpp bit and the E bit sets the word drive potential to 9 V for the erase operation. Also, when the Vpp bit and the P bit are set, the write control circuit W that refers to these bits is set.
The CONT controls an internal operation for writing according to a predetermined procedure. That is, the input / output circuits IOC1, IOC
2, the control signal WR is supplied to the selection switch WS in the IOC3.
ITE is supplied and turned on, and a write voltage is supplied to the write circuit WR. This enables the supply of the write voltage to the bit line.

The internal operation for erasing and writing is performed by forming a voltage of a predetermined level. The erase verify operation is an operation of performing a read operation on an erased memory cell to verify whether the erasure is completed. The write verify operation reads the write data from the written memory cell and writes it. The operation is to verify whether the writing is completed by comparing the data with the data. These verify operations are performed based on the comparison result of the comparison circuit COM at that time when a read cycle for the flash memory is started.

The memory cells MC in the flash memory cell group 10 are not particularly limited, but are formed by arranging a plurality of flash memory cells constituted by insulated gate field effect transistors having a two-layer gate structure in a matrix. The control gates of the flash memory cells MC are connected to corresponding word lines (not shown), the drains of the flash memory cells are connected to corresponding data lines (not shown), and the sources of the flash memory cells are connected to the lower potential power supply Vss. ing. Erasing is performed by applying a high voltage to the control gate and injecting hot electrons generated near the drain junction into the floating gate to raise the threshold. The erase operation is performed in word units. In addition, writing is realized by applying a high voltage to the drain, setting the control gate to a negative potential, and extracting electrons in the floating gate to the drain by a tunnel phenomenon to lower the threshold.

FIG. 7 shows a configuration of a main part of the flash memory 10.

The flash memory cell group 13 in the flash memory 10 has a plurality of sectors including a plurality of nonvolatile memory cells selected at the same time. 1
A sector corresponds to one word. In FIG. 1, 2, 1
The sector indicated by 1 is representatively shown.

The memory cell group 13 includes a data area in which a plurality of flash memory cell groups used for reading and writing data are arranged, and a management area 40 for managing the data area. Generally, if 98% or more of the flash memory cells belonging to the data area operate normally, the flash memory is regarded as good. In this case, a non-defective code is written in a management area in a normally operating sector in order to avoid using a bad sector. The card controller 65a forms an address conversion table of this management code in the RAM 653 immediately after the power is turned on. When the memory card is accessed, the input logical address is converted into a physical address based on the address conversion table, and the local memory (flash memory) 65b is accessed by the physical address.

Reference numerals 3a and 3b denote monitor bits in the sector 2, which are formed in the management area 40. Although not particularly limited, the monitor bit 3a is an erase bit and the monitor bit 3b is a write bit. The monitor bits 3a and 3b have a smaller threshold margin in data retention characteristics than the memory cells used for reading and writing data in the data area 30. The erase and write operations are performed in the data area 30 and the management area 40.
Irrespective of the above, the monitoring is performed in units of sectors, that is, in units of words. Therefore, the monitor bits 3a and 3b having a smaller threshold margin in the data holding characteristics than the memory cells used for reading and writing data in the data area 30 as described above.
Reaches the end of life earlier than the memory cells used for reading and writing data in the data area 30.

As described above, since the monitor bits 3a and 3b reach the end of their life earlier than the memory cells used for reading and writing data in the data area 30, the data in the memory cells used for reading and writing data are destroyed. It is possible to grasp the life of the flash memory without performing.

That is, by detecting the occurrence of an error in the monitor bit, the life of the sector can be grasped as follows.

FIG. 4 shows the relationship between the threshold value Vth of the memory cell and the bit number distribution state.

As shown in FIG. 4, the threshold value of the flash memory cell in the data area 30 is divided into a write state and an erase state.

The threshold value Vth of the monitor bit (write bit) is set higher than the threshold value of the write state of the flash memory cell in the data area, and the threshold value of the monitor bit (erase bit) is set in the data area. Is set lower than the threshold value of the erased state of the flash memory cell in the above.

When the threshold Vth distribution in the written state varies due to rewriting, as shown in FIG.
When the monitor bit (write bit) exceeds the read threshold value Vth, a failure occurs promptly. As a result, before the memory cell in the data area 30 becomes defective due to its life, it is possible to know from the monitor bit 3a that the life of the sector to which it belongs is approaching.

Although the defect detection circuit 4 is not particularly limited,
It can be constituted by an exclusive OR circuit for comparing the logical values of the monitor bits 3a and 3b. If the monitor bits 3a and 3b have logical values "0" and "1", respectively, the life has not yet been reached. However, the monitor bits 3a and 3b have the logical values "0" and "0", respectively.
Alternatively, when the logical values become "1" and "1", the output logic of the exclusive OR circuit is inverted, and it is detected that the life of the sector to which it belongs is approaching.

When the threshold value Vth of the erased state varies due to rewriting, as shown in FIG. 6, the monitor bit (erase bit) 3b exceeds the threshold value Vth of the read operation. Becomes As a result, before the memory cell in the data area becomes defective due to its life, it is possible to detect from the monitor bit 3b that the life of the sector to which it belongs is approaching.

When reading is performed on the sector 2, the logical values of the monitor bits 3a and 3b are also read, and the logical values are compared by the defect detection circuit 4. The failure detection circuit 4 detects the occurrence of an error in the monitor bits 3a and 3b by obtaining an exclusive OR of the logical values of the monitor bits 3a and 3b. When the logical values of the monitor bits 3a and 3b are aligned as logical values "1" and "1" or "0" and "0", the failure detection signal BAD is asserted to indicate the occurrence of an error. When the failure detection signal BAD is asserted, the sector 11 is used instead of the sector 2 whose life is approaching.

FIG. 2 shows a flow of detecting a defective bit.

At present, the erase bit 3a holds a logical value "1", and the write bit 3b holds a logical value "0". The rewriting operation includes an erasing operation and a writing operation, which are performed in sector units.

An example in which the sector 2 is rewritten will be described.

The erasure control signal ERASE is asserted by the erasure control circuit ECONT, and an erasing voltage such as -7 V is applied to the data lines DL0 to DLn by the erasing circuit ER. Is performed (S21).

Next, erase bit 3a, write bit 3
Writing to b is performed. Since the input terminal of the write circuit WR in the input / output circuit IOC2 is pulled up, a logical value “1” is written, and in that case, supply of the write voltage to the bit is prevented (S
22).

On the other hand, the write bit 3b changes from the state of the logical value “0” (S21) to the logical value “1” by the erasing operation, but the input terminal of the write circuit WR in the input / output circuit IOC3 is pulled down. Therefore, the write data becomes the logical value "0", and is returned to the logical value "0" again by the write operation (S25). That is, in rewriting the sector 2, the logical value of the erase bit 3a is not changed, but the write bit 3b is changed from the logical value "0" to the logical value "1" and further to the logical value "0". Thus, every time the sector 2 is rewritten, the write bit 3b is stressed.

In data reading in the write verify of the erase bit 3a and the write bit 3b, the defect detection circuit 4 obtains the exclusive OR of the logical value of the erase bit 3a and the logical value of the write bit 3b (S
26). When the card controller 65 recognizes that the data of the erase bit 3a has been determined by the above verification, the output logic of the failure detection circuit 4 is taken into the card controller 65a.

When the output logical value of the failure detection circuit 4 is "0", it means that the logical value of the erase bit 3a is "1" and the logical value of the write bit 3b is "0". It will be normal.

However, when the output logic value of the failure detection circuit 4 becomes "1",
It is possible that the logical value of the write bit 3b could not return to "0", which means that the write bit 3b has reached the end of its life. Therefore, in that case, in the subsequent memory card access, the control information is rewritten so that another normal sector 11 is selected instead of the sector 2. For example, information indicating that the sector 2 is defective is written in the management area, and the content of the address conversion table is rewritten accordingly, so that the sector 11 can be accessed instead of the sector 2 thereafter. Become.

Here, to make bit errors more likely to occur in the data area 30 than in memory cells used for reading and writing data, there is no particular limitation. It can be formed under process conditions such that the service life comes earlier than the cell. For example, the surface area of the floating gate of the MOS transistor forming the monitor bits 3a and 3b is made smaller than that of the other bits.
Then, the amount of charge that can be stored in the floating gate is smaller than the other bits from the beginning.
Such a reduction in the amount of charge stored in the floating gate reduces a threshold margin in data retention characteristics.

According to the above example, the following functions and effects can be obtained.

(1) A monitor bit 3 whose life is set shorter than that of a memory cell used for reading and writing data.
a and 3b, and a failure detection circuit 4 for detecting a data failure in the monitor bits 3a and 3b and forming a signal for replacing the sector to which the monitor bit belongs with another sector. As a result, when the failure detection circuit 4 detects that an error has occurred in any of the monitor bits 3a and 3b, the failure detection signal BAD is asserted, and in response to this, the replacement circuit 10 replaces the sector. . In such a failure detection, a sector having a high ability (long life) can be used up to the limit of the life, and the life of the flash memory can be prolonged. Further, in a sector having a low ability (short life), another sector can be replaced before a failure occurs in the data storage area, so that data reliability can be improved.

(2) The life of the monitor bits 3a and 3b is set shorter than that of a memory cell used for reading and writing data.
Since the sector replacement is performed immediately, it is possible to prevent the replacement from failing due to the occurrence of a defect.

(3) In the data processing device provided with the flash memory having the operation and effect (1) or (2), the reliability of the data processing result is improved by improving the reliability of the memory data. Can be.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

In order to set the life of the monitor bit shorter than that of the memory cell used for reading and writing data, various methods can be considered in addition to the above example.

For example, the floating gate 142 of the monitor bit (see FIG. 14) is made thinner 143 than the floating gate of another nonvolatile memory cell used for reading and writing data. When the thickness is reduced, the amount of charge stored in the floating gate is reduced as compared with the case where the thickness is large. Therefore, even in this case, the threshold margin in the data retention characteristics of the monitor bits 3a and 3b is reduced as compared with other bits. Can be reduced.

Monitor Bit Floating Gate 14
2 (see FIG. 14) may be configured such that the area of the surface facing the control gate 141 is smaller than that of the floating gate in another nonvolatile memory cell used for reading and writing data. Even in this case, since the amount of charge stored in the floating gate is reduced as compared with other nonvolatile memory cells used for reading and writing data, the threshold margin in the data retention characteristics of the monitor bits 3a and 3b is reduced. Less bits.

Monitor bit floating gate 14
2 (see FIG. 14) may be thinner than the thickness of the insulating film in another nonvolatile memory cell used for reading and writing data. When the thickness of the insulating film surrounding the floating gate is reduced, the charge storage capacity of the floating gate is reduced accordingly. Therefore, the threshold margin in the data retention characteristics of the monitor bits 3a and 3b should be reduced as compared with other bits. Can be.

By setting the write state and the erase state of the element forming the monitor bit to be shallower than another element in the sector to which the monitor bit belongs, the threshold margin in the data holding characteristic is set to other bits. You may make it small compared with. To realize this, although not particularly limited, the voltage applied to the monitor bits 3a and 3b during the writing operation or the erasing state may be set lower than the level applied to the nonvolatile memory cells in the data area. Good. For example, a write control circuit WCONT
As a result, the voltage applied to the drain electrodes of the monitor bits 3a and 3b is made lower than the voltage applied to other nonvolatile memories used for reading and writing data. As a result, the amount of charge stored in the floating gates of the monitor bits 3a and 3b becomes smaller than that of other nonvolatile memories used for reading and writing data. The threshold margin can be reduced as compared with other bits.

Further, the voltage application time to the monitor bits 3a and 3b during the writing operation or the erasing state may be shorter than the other bits. Thereby, the monitor bits 3a, 3b
Can be made smaller than the accumulated charge amount of the other bits, so that the monitor bit 3
The threshold margin in the data holding characteristics of a and 3b can be reduced as compared with other bits.

In the above example, as shown by 3a and 3b, the number of monitor bits per sector is set to 2, but one of them is a bit having a normal threshold margin in the data holding characteristic. It can be. This bit is used as a reference bit. Since the normal threshold margin of the monitor bit is lower than that of the reference bit, by comparing the logical value of the reference bit with the logical value of the monitor bit, the same operation and effect as in the above-described example can be obtained. .

The bias condition may be set in the monitor bit so that more disturbance occurs in writing, erasing, and reading than in the nonvolatile memory cell in the data area. For example, a bias condition such as making the voltage applied to the drain electrode higher than that of the non-volatile memory cell in the data area makes it easier for data failure in the monitor bit to occur than in the non-volatile memory cell in the data area. By doing so, the same operation and effect as in the above-described example can be obtained.

The monitor bits 3a and 3b may be formed in the data area 30 as shown in FIG.
As shown in FIG.
And the monitor bits 3b are formed at a predetermined distance from each other such that the monitor bits 3b are formed in the management area 40.

As shown in FIG. 7, a replacement circuit 6 for performing sector replacement based on the output signal BAD of the failure detection circuit 4
May be arranged outside the flash memory 10.

Depending on the semiconductor memory, there is a multi-valued memory capable of handling more than two states with one memory cell, and the present invention can be applied to such a semiconductor memory.

Further, in the above-described example, the one having the defect detection circuit 4 has been described. However, as shown in FIG. 3, defect detection can be performed by using verification. In this case, the failure detection circuit 4 as hardware can be omitted.

After the erasure of the specific sector (S31) is performed, it is determined whether or not the erasure is appropriate based on the output of the comparison circuit COM in the input / output circuits IOC2 and IOC3 (S32). In this determination,
If it is determined that the erasure of the monitor bits 3a and 3b is not appropriate (N), it is determined whether or not the number of times of erasure verification has reached a predetermined value (S3).
6). In this discrimination, if the number of times of erase verify has not reached the predetermined value, the process returns to the erase operation of step S31. However, if it is determined in step S36 that the number of erase verify operations has reached the predetermined value (Y), an erase error is determined, and the erase verify operation for the monitor bit ends. Since the erase verify operation for the monitor bits is completed in this manner, if the threshold margin in the data holding characteristic of the monitor bits 3a and 3b is made smaller than that of the other bits, the monitor bits 3a and 3b can be erased. The failure can be detected by checking the timeout in the verification.

If it is determined in step S32 that erasure has been properly performed (Y), a write operation is performed (S33), and write verification is performed (S34). In this write verify,
If it is determined that writing is inappropriate (N),
It is determined whether or not the number of times of write verification has reached a predetermined value (S35). If it is determined in this determination that the number of times of write verification has not reached the predetermined value (N), the write operation of step S33 is performed. However, if it is determined in step S35 that the number of times of write verification has reached the predetermined value (Y), it is determined that a write error has occurred, and the write verification for the monitor bit is terminated. Since the write verification for the monitor bits is completed in this manner, if the threshold margin in the data holding characteristics of the monitor bits 3a and 3b is made smaller than that of the other bits, the monitor bits 3a and 3b are not changed. The failure can be detected by checking the timeout in the verification.

In the above example, when a failure is detected based on the output data of the monitor bit, address replacement for replacing the sector containing the monitor bit with another sector is performed by the card controller 65a. Alternatively, this address replacement may be performed in the flash memory chip. That is, as shown in FIG. 10, the replacement circuit 6 is provided in the chip of the flash memory 10.
Is provided. When the failure detection signal BAD is asserted by the failure detection circuit 4, the replacement circuit 6 replaces the sector including the monitor bit with another sector, so that in the subsequent memory access, the sector 11 is used instead of the sector 2. Is selected. The replacement circuit 6 in this case can be formed by a combination of logic circuits.

As shown in FIG. 2, the erase bit 3a is
The logical value is "1" regardless of erasing or writing.
Therefore, one input terminal of the exclusive OR circuit forming the failure detection circuit 4 may be fixed to a high level by, for example, coupling to the high potential side power supply Vdd. In this case, the erase bit 3a, the corresponding Y selection switch YSn-1, the input / output circuit IOC2, and the like can be omitted.

Further, in the input / output circuits IOC2 and IOC3, as shown in FIG. 13, an inverter INV for logically inverting the output data of the sense amplifier SA is provided, and the data inverted by the inverter INV is transferred to the data latch D
By taking in the IL, the erase bit and the write bit can be toggled.

In the example shown in FIG.
By erasing and writing to b, its logical value is
Although changed to "0", "1", and "0", the stress on the erase bit 3a becomes insufficient because the erase bit 3a is fixed at the logical value "1". Therefore, FIG.
, An inverter INV for logically inverting the output data of the sense amplifier SA is provided, and the first read data in the write verification for the erase bit 3a and the write bit 3b is converted to the inverter INV.
The data is inverted by V and latched by the data latch DIL.
In the write verify in this case, it is determined that the write is insufficient in the first read operation.

As a result, focusing on the erase bit 3a,
Since the logical value “1” is logically inverted by the inverter INV and input to the data latch DIL, the write data becomes the logical value “0”. Therefore, the logical value “1” is erased in step S21, and the logical value “1” is written in step S22. To a logical value “0”. Then, the logical value “0” is read and logically inverted by the inverter INV.
This time, the logical value becomes "1", which is written to the erase bit 3a. Thereby, sufficient stress can be applied to the erase bit 3a.

Further, focusing on the write bit 3b,
The logical value “1” is written by the logical inversion of the logical value “0” of the read data by the inverter INV. Further, the logical value “1” is read out and logically inverted by the inverter INV, so that the logical value “0” is next.
Is written. Thus, sufficient stress can be applied to the write bit 3b.

In the above description, the case where the invention made by the present inventor is mainly applied to a memory card which is the field of application as the background has been described. However, the present invention is not limited to this, and the present invention is not limited thereto. It can be applied as internal memory,
It can be widely applied to various data processing devices.

The present invention can be applied on the condition that it includes at least a plurality of nonvolatile memory cells.

[0095]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a failure occurs in a nonvolatile memory cell used for data read / write by providing a monitor bit having a smaller threshold margin in data retention characteristics than a nonvolatile memory cell used for data read / write. It is possible to detect a defect of the monitor bit beforehand, and in a sector having a high ability (long life), it can be used up to the limit of the life, and the life of the flash memory can be prolonged. In a sector having a low ability (short life), another sector can be replaced before the occurrence of a defect in the data storage area, so that data reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a main part in a flash memory as an example of a nonvolatile memory according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the flash memory.

FIG. 3 is a flowchart for explaining the operation of the flash memory.

FIG. 4 is a threshold voltage distribution diagram for explaining the operation of the flash memory.

FIG. 5 is a threshold voltage distribution diagram for explaining the operation of the flash memory.

FIG. 6 is a threshold voltage distribution diagram for explaining the operation of the flash memory.

FIG. 7 is an explanatory diagram of a configuration example of a main part in the flash memory.

FIG. 8 is a block diagram illustrating a configuration example of a data processing device to which a memory card including the flash memory is applied.

FIG. 9 is a block diagram illustrating a configuration example of a card controller in the memory card.

FIG. 10 is an explanatory diagram of another configuration example of the flash memory.

FIG. 11 is an explanatory diagram of another configuration example of the flash memory.

FIG. 12 is an explanatory diagram of another configuration example of the flash memory.

FIG. 13 is an explanatory diagram of another configuration example of a main part in the flash memory.

FIG. 14 is a perspective view showing a configuration example of a memory cell in the flash memory.

[Explanation of symbols]

 2, 11 Sectors 3a, 3b Monitor bits 4 Failure detection circuit 6 Replacement circuit 10 Flash memory 13 Flash memory cell group 30 Data area 40 Management area 61 CPU 66 Bus 64 Interface circuit 65 Flash memory card 65a Card controller 65b Local memory 65c Local bus VSEL voltage selection circuit XALAT X address latch XADEC X decoder SUPP power supply circuit YALAT Y address latch YADEC Y decoder WCONT write control circuit WEREG write / erase control register WR write circuit DIL data latch DIB data input buffer SA sense amplifier DOB data output buffer COM comparison Circuit IOC1, IOC2, IOC3 I / O circuit

Claims (8)

[Claims] A plurality of word lines, a plurality of nonvolatile memory cells coupled to the word lines, and a threshold which is provided for each of the word lines and which is different from other nonvolatile memory cells used for reading and writing data. A non-volatile memory characterized by including a monitor bit whose life is earlier than the other non-volatile memories by reducing the value margin. 2. The nonvolatile memory cell and the monitor bit each have a floating gate for charge storage, and the floating gate of the monitor bit is used in another nonvolatile memory cell used for reading and writing data. 2. The non-volatile memory according to claim 1, wherein the thickness is smaller than that of the floating gate. 3. The non-volatile memory cell and the monitor bit each have a floating gate for charge storage and a control gate disposed opposite to the floating gate. The floating gate of the monitor bit is used for reading and writing data. 2. The nonvolatile memory according to claim 1, wherein an area of a surface facing said control gate is made smaller than a floating gate of another nonvolatile memory cell to be formed. 4. The non-volatile memory cell and the monitor bit each have a floating gate for charge storage, and the thickness of an insulating film surrounding the floating gate of the monitor bit is different from that used for reading and writing data. 2. The nonvolatile memory according to claim 1, wherein the thickness of the insulating film is smaller than the thickness of the insulating film in the nonvolatile memory cell. 5. A plurality of word lines, a plurality of nonvolatile memory cells coupled to the word lines, a monitor bit provided for each word line, and the amount of charge stored and written to the monitor bits for reading and writing data. And a write control circuit for reducing the number of memory cells to be smaller than that of other nonvolatile memory cells used in the nonvolatile memory. 6. A plurality of word lines, a plurality of non-volatile memory cells coupled to the word lines, monitor bits provided for each word line, and a monitor bit as compared with other non-volatile memory cells. And a write control circuit in which a bias condition is set so as to cause a large amount of disturbance. 7. A fault detecting circuit for detecting a fault based on read data from the monitor bit.
7. The nonvolatile memory according to any one of claims 1 to 6. 8. A memory system comprising: the nonvolatile memory according to claim 1; and means for performing sector replacement based on a detection result of a failure detection circuit in the nonvolatile memory.