JP2000100178A - Non-volatile semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent other data from being damaged due to write by storing information due to the change in a threshold in a memory cell, storing the result where an excessive threshold has been detected in the memory cell, and reading the storage state externally and to transfer the write trouble to a user. SOLUTION: When a bit line BL0 and a signal A are set to 'H' and B is set to 'L', Q2 and Q4 are turned on to form a current path. Then, by setting a node (b) of a latch (O) to 'H', excessive write to a cell is detected. A common node E for connecting the excessive read signal E of each latch circuit is connected to a power supply. With the excessive write state as 'L' of the common node E, F/F cannot be reset even if an over program verification signal reaches 'H'. With the excessive write, when no cells exist and E is 'H', the output of an 2-input AND gate is inverted to RS F/F set state. The state of the F/F stores the excessive write state and outputs it from an MUX.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having a function capable of preventing a user from excessively writing to a memory cell and erroneously writing to an unselected memory cell. The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art Some conventional nonvolatile semiconductor memory devices, such as NAND flash memories, write data to memory cells in page units and collectively erase data. FIGS. 6 and 7 show a method of applying a bias voltage applied to a memory cell when performing such writing and erasing.

[0006] Writing to a memory cell will be described with reference to FIG. The memory cell constituting the NAND flash memory is a floating gate MOS shown in FIG.
A silicon substrate 1 formed of a transistor and having a P-well formed therein, a source / drain diffusion layer 2 doped with a high concentration of N-type impurities, and a channel 3 formed between the source / drain diffusion layers 2; It comprises a thin first insulating film 4, a floating gate 5, a second insulating film 6, and a control gate 7.

The upper surface of the memory cell shown in FIG. 6 is usually covered with an insulating film, and the thin first insulating film 4 and the second
Since the side surface of the insulating film 6 is connected to the insulating film on the upper surface, these insulating films have no boundary line with the outside.

As shown in FIG. 6, in a write operation to the memory cell, a voltage of 0 V is applied to the channel 3 and a voltage of 15 V to 20 V is applied to the control gate 7. At this time, in the two-layer gate structure of the memory cell, the voltage applied to the control gate is divided by capacitance, and the voltage is applied to the thin first insulating film 4 between the channel 3 and the floating gate 5 as positive.

In this manner, electrons from the N-type channel 3 are tunnel-injected into the floating gate 5 through the thin first insulating film 4, and the floating gate is negatively charged, thereby constituting the memory cell. The threshold value of the floating gate MOS transistor (hereinafter referred to as the threshold value of the memory cell) changes to a positive value.

[0007] Such a write operation is usually performed for memory cells arranged in an array in units of pages corresponding to one word line. The case where writing is performed in page units is called normal page writing.

Next, the erasing operation of the memory cell will be described with reference to FIG. Since no channel is formed in the erasing operation, the structure of the memory cell shown in FIG.
Is not shown. The other structure is the same as that of FIG.

As shown in FIG. 7, the control gate 7 of the memory cell is set to 0 V, and the P well has a voltage of 15 V to 20 V.
Is applied. In this way, the electrons injected into the floating gate in the write operation are extracted to the P well, and the threshold value of the memory cell becomes a negative value corresponding to the erased state.

[0010] Such an erasing operation is performed on memory cells arranged in an array in a memory cell group within a certain range or all memory cells at once. The case of performing batch erasing is usually called flash erasing.

That is, in the NAND flash memory, writing and erasing are performed by applying a bias voltage as shown in FIGS. 6 and 7, and electrons are injected from the channel 3 into the floating gate 5 in the written state. The threshold value of the memory cell becomes positive, and in the erased state, on the contrary, electrons are emitted from the floating gate 5 to the channel 3 so that the threshold value of the memory cell becomes negative.

For this reason, in the write state and the erase state, the threshold value of the memory cell changes as shown in FIG. The vertical axis in FIG. 8 indicates the threshold value of the memory cell, and the horizontal axis indicates the cell distribution of the memory cell having this threshold value, and shows the distribution of the memory cell in the written state and the erased state, respectively. The voltage level (4 V) of the non-selected word line is shown at the top of the figure.

In an actual device, the bias voltage shown in FIGS. 6 and 7 is repeatedly applied while measuring the threshold value of the memory cell by the verify operation. The threshold value is set to 0 in the erase operation.
V or less or the erase verify voltage or less.

However, normally, an upper limit is set for the number of repetitions, and even if the number of repetitions reaches this upper limit,
If the threshold value does not reach the voltage, a status signal of "fail" is returned for this write operation or erase operation.

When this status signal "fail" is returned after the end of the write operation or the erase operation,
The memory cell to be written or erased is determined to be defective, and the user uses another normal memory cell.

As described above, in the prior art, the write operation,
When the threshold value of the memory cell does not reach a sufficient value in each of the erasing operations, a countermeasure is provided. However, the malfunction of the writing operation is not necessarily limited to the case where the insufficient writing or the insufficient erasing occurs. .

Next, a description will be given of a change in the threshold value of the NAND flash memory due to a write or erase operation, which is not detected by the conventional method. FIG. 9 shows an example in which NAND-type cells including four nonvolatile memory cells having a two-layer gate structure are arranged in an array.
1 shows a part of a configuration of a cell array of a flash memory.
BL _{0 to} BL ₂ are bit lines to which the NAN is connected.
The drain side of the D-type cell is connected via a selection transistor. The source side of the NAND type cell is connected to a common source line via a selection transistor.

[0018] WL ₁ to WL ₄ are word lines, the control gate of the memory cell having a two-layer gate connected. SG ₁ and SG ₂ are selection lines, and the NAND
The gates of the select transistors on the drain side and source side of the pattern cell are respectively connected.

In the NAND flash memory shown in FIG. 9, for example, when reading out the cell A, the word line WL ₃ is selected and set to 0 V, and the other unselected word lines WL ₁ , WL
The _2, WL ₄ applies a 4V.

The bit line connected to the NAND type cell including the cell A is designated as BL ₁ . Unselected word lines WL ₁ , WL
₂ and WL ₄ are applied with 4 V, so that the bit line BL ₁
Even if a non-selected cell other than the cell A among the NAND cells connected to the memory cell includes a cell in a write state, 4 V is applied to the control gate of the non-selected cell. All cells are turned on.

Since the control gate of the cell A is at 0 V, it is determined from FIG. 8 whether or not the conduction between the common source line and BL ₁ is in accordance with whether or not the cell A is in the writing state. , therefore, by detecting the voltage or current of BL _1, it is possible to read the memory data stored in the cell a.

[0022] At this time, a excessive write state for example cell B, if equal to or greater than the threshold value 4V, path to the common source from the bit lines BL ₁ is always non-conducting state, the cell A Unable to read stored memory data.

Therefore, such an overwriting state can be regarded as a writing failure, but since the overwriting cannot be detected by the conventional method, it is impossible for the user to cope with it.

In addition to the above, there are the following inconveniences that occur during writing in the related art. For example, when select the cell B performing write, same cell A which is adjacent in the NAND cell conduction between the bit lines BL _1, even in the written state is maintained, the cell B to ground the BL ₁ Must be made possible by setting the channel of 0 V to 0 V. Therefore, as shown in FIG. 10 (a), the control gate 7 of the cell A, that is, the word line WL ₃ voltage of 7V to 10V is applied. For the same reason, a voltage of 7 V to 10 V is applied to the word lines WL ₁ and WL ₂ .

On the other hand, a cell C belonging to an adjacent NAND type cell and having a gate connected to the same word line WL ₄ as the cell B.
In order to avoid erroneous writing, FIG.
As shown in FIG.
V to 8V are applied.

At this time, as described above, the word line W
Since a voltage of 7 V to 10 V is applied to L ₁ , WL ₂ and WL ₃ , the write inhibit voltage of 5 V to 8 V can be applied to the channel of the cell C from the bit line BL ₂ . In this way, in FIG. 10B, since the potential difference between the floating gate 5 and the channel 3 becomes small, injection of electrons into the floating gate is prohibited.

As described above, around the write cell B, there are non-write cells such as the cells A and C to which a weak bias voltage is applied when writing the cell B.
If some of these cells are written particularly quickly, the threshold may change due to this weak bias.

Such a change in the threshold voltage destroys the data stored in the memory cell and must be treated similarly as a write failure. In the conventional write verify method, such a write failure is detected. There was a problem that I could not do it.

[0029]

As described above, the conventional write verify method has a problem that it is not possible to detect excessive writing. In addition, there is a problem that a weak bias voltage is also applied to non-write cells around the selected write cell, and memory data in the non-write cells may be destroyed. The present invention has been made in order to solve the above-described problems, and includes means for detecting an abnormality in a write state including overwriting, means for storing a detected result, and a circuit for reading out the detected abnormality to the outside. It is another object of the present invention to provide a non-volatile semiconductor memory device which can detect the destruction of the memory data stored in another non-written cell at the time of writing and can avoid this.

[0030]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: an overwriting detection means; a detection result storage means; and a circuit for reading out the overwriting state to the outside. . Further, by using the detection means, the user can detect an abnormality in the threshold value of the cell and collectively erase the memory cell group connected to the same word line and including the abnormality. Also, at the time of batch erasing, it is possible to temporarily save the memory data stored in the portion of the memory cell group where there is no possibility of a threshold change, and to rewrite this portion at the final stage of writing.

More specifically, a nonvolatile semiconductor memory device according to the present invention comprises a memory cell for storing information by a change in threshold value, a detecting means for detecting an excessive change in threshold value of the memory cell, and a detecting means And a circuit for reading out the storage state stored in the storage means to the outside.

Preferably, after the excessive threshold value change of the memory cell is detected by the detecting means, the excessive threshold value change is selectively or collectively applied to the memory cells having the excessive threshold value change. The method is characterized in that a bias voltage that causes a threshold change in a direction opposite to the change is applied.

[0033] Preferably, upon detection of excessive writing after writing to said memory cells connected to the same word line, when an excessive threshold value change of said memory cells is detected by said detecting means, It is characterized in that all memory cells connected to a word line are erased.

More preferably, the memory cells connected to the same word line are configured to perform writing by dividing the memory cells into a plurality of memory cell groups. Means for temporarily saving memory data of a memory cell group connected to the same word line and which is not targeted for writing, wherein the memory cells connected to the same word line are collectively erased, and The method is characterized in that data is written again to a memory cell group not to be written.

Further, the nonvolatile semiconductor memory device of the present invention comprises a memory cell for storing information by changing a threshold value,
Another memory cell which simultaneously changes the threshold value by the storage operation of the memory cell, detecting means for detecting the threshold value change of the other memory cell, and storage for storing a result detected by the detecting means. Means, and a circuit for reading out the storage state stored in the storage means to the outside.

[0036]

Embodiments of the present invention will be described below in detail with reference to the drawings. The nonvolatile semiconductor memory device according to the first embodiment of the present invention performs page writing and batch erasing of memory data to memory cells like a NAND flash memory, for example.

FIG. 1 shows a NAND according to the first embodiment.
The details of the write / read circuit of the flash memory are shown. Each of the bit lines BL ₀ , BL ₁ ,.
Latch 0, Latch 1,... Composed of the inverters I ₁ and I ₂ are connected. Further, common signals A, B, C, D, E, and F are input to the respective latch circuits as shown in FIG.

A P-channel MOS transistor (hereinafter referred to as PM
OS ₁ ) controls the precharge to bit line BL ₀ by signal D, and N-channel MOS transistors (hereinafter referred to as NMOS) Q ₂ , Q ₃ , Q ₄ are connected to BL _0.
And the signals A and B, the voltage levels of the nodes a and b of the latch 0 are determined.

The NMOSs Q ₅ and Q ₆ determine the level of the signal E in response to the state of the latch 0 by the node b of the latch 0 and the signal F. NMOS, Q _7, the signal C
In response to this, the state of node a of latch 0 is changed to bit line BL ₀
Transfer to

The case where all the bit lines are read simultaneously in the NAND flash memory of the first embodiment will be described. At the time of reading, the selected word line is set to 0 V, and the storage states of the memory cells connected to this word line are simultaneously read.

[0041] The signal D is set to a low level (hereinafter referred to as "L"), confers the precharge voltage via the Q ₁ to the bit line BL _0. If the selected memory cell connected to BL ₀ is in a write state, the bit line B charged via Q ₁
Since no current flows through L ₀ , the high level of BL ₀ (hereinafter referred to as “H”) is maintained.

The "H" level of BL ₀ is set such that by setting the signal B to "H" and A to "L", the GND (0 V) of the source of Q ₂ is latched via Q ₂ and Q ₃ in the ON state. Node b of 0
, The node b of the latch 0 becomes “L”.

On the other hand, if the selected memory cell is not in a write state, a current flows through the bit line BL ₀ , BL ₀ goes to “L” and Q ₂ turns off, so that the state of the latch 0 is maintained. You.

Next, a description will be given of a method of detecting when overwriting occurs in the selected memory cell. At the stage where a series of writing and write verify have been completed for all the memory cells, the nodes b of all the latches are at the low level.

In FIG. 9, word lines WL _{1 to} WL ₄
Are set to the unselected word line voltage 4V in FIG. 8 or an excessive write detection voltage lower than 4V to perform the read operation. For example one of the memory cells of the NAND cell connected to the bit line BL ₀ in FIG. 9 and the cell X, for writing to the cell X is excessively performed, the threshold value is 4V or more over programming voltage, or 4V Assume that the excess overwrite detection voltage has been exceeded. At this time, the bit line B
If the read operation is performed after precharging L ₀ , the cell X cuts off the current, so that the bit line BL ₀ is maintained at the “H” state by the precharge.

In FIG. 1, bit line BL ₀ and signal A
There "H", if the B is _{"L", Q 2, Q} 4 form a current path turned on, it is changed to the node a of the latch 0 "L". Therefore, the node b of the latch 0 becomes “H”. As described above, by setting the node b of the latch 0 to “H” by using the latch 0 as a means for detecting the excessive write, the excessive write to the cell X is detected.

FIG. 2 shows a read circuit for storing the state of overwriting detected by the latch circuit shown in FIG. 1 and reading it out to the outside. Reading circuit shown in FIG. 2, a common node E to read signal E overerasing from each latch circuit are connected, the common node E PMOS, are connected to a power supply via the Q _8. PM
OS, to the gate of Q ₈ signal F in FIG. 1 is input, also common node E is connected to one input terminal of 2-input AND gate 10. An over program verify signal is input to the other input terminal of the two-input AND gate, and its output terminal is connected to the set terminal of the RS flip-flop 20.

This RS flip flop (hereinafter referred to as RS
F / F) 20 outputs the multiplexer MUX, 3
0 is connected to one input terminal, and the other input terminal receives memory data. The output of the MUX 30 is connected to the memory data output terminal of the nonvolatile semiconductor memory device, and the switching signal (not shown) of the MUX 30
If the mode is set to monitor the write state, a read flag for overwriting is output, and if the mode is set to the normal operation mode, memory data is output.

The overwriting read operation will be described in more detail with reference to FIGS. As described above, by setting the node b of the latch 0 to “H”, an excessive write to the cell X is detected. Therefore, the logical sum of the level of the node b of each latch is detected using the signal F. Then, overwriting can be read.

In the normal operation mode, signal F is "L".
, And the order common node E of FIG. 2 is connected to the power supply via PMOS, the Q _8, also, Q ₆ of FIG. 1 is off,
The common node is fixed at "H". At this time, since the over program verify signal is "L",
The output of the two-input NAND gate 10 becomes "L" and RS
The F / F 20 is reset by a write start signal when a write operation is started.

By setting the monitor mode in the writing state,
The signal F becomes "H", and the common node E in FIG.
₈ is turned off and disconnected from the power supply. Also, Q in FIG.
Because ₆ is to be turned on, if either one of the nodes b of the latch is connected to all the bit lines to "H" by excessive writing, common node E of FIG. 1, of the latch Q _5, Q ₆ To “L”. Further, if also has one excessive writing, since the node b is "L", Q ₅ is turned off, the "H" state of the common node E is maintained.

In this manner, the overwriting state read as the state "L" of the common node E is caused by the F / F even when the over program verify signal becomes "H".
F is not set. If there is no overwritten cell and the state of E is “H”, the RS · F / F is inverted from the output of the 2-input AND gate to the set state. The state of the F / F stores the state of overwriting, and the MUX, 3
0 is output to an external terminal, and the user can take measures against overwriting.

Next, a second embodiment of the present invention will be described with reference to FIG. In the first embodiment,
A circuit has been described which allows externally detectable information of overwriting. However, in the second embodiment, in order to cope with overwriting, writing is performed by erasing all memory cells connected to a word line in which a defect is found. The method will be described.

That is, after detecting overwriting using the circuits shown in FIGS. 1 and 2, the word line to which the control gate 7 of the overwriting defective cell is connected is grounded as shown in FIG. After the word line to which the control gate of the normal cell is connected is brought into a floating state, a high voltage of 20 V in the opposite direction to the voltage previously used for writing is applied to the P well.

In this way, by erasing all cells connected to the word line where the overwritten defective cell is found,
Since the threshold value of all the cells connected to the word line where the overwritten defective cell exists is lowered, the overwritten cell does not adversely affect the data of other cells connected in series with the word line.

At this time, by applying a voltage in the reverse direction, it is not always necessary to completely erase all the cells connected to the word line where the overwritten defective cell exists.
It is only necessary that the threshold values of all cells connected to the word line be low so as not to adversely affect the data of other cells connected in series with the overwritten cell.

FIG. 3 shows the case where all cells connected to the word line where an overwritten defective cell is found are collectively erased or collectively applied with a voltage in the reverse direction of writing. Alternatively, the application of the reverse voltage can be selectively performed.

Next, a third embodiment of the present invention will be described with reference to FIG. The third embodiment is similar to the second embodiment.
This embodiment has the same purpose as that of the first embodiment, but differs in the configuration of a memory cell array to be applied. In the memory cell array shown in FIG. 4, one latch is shared by two bit lines.

In the memory cell array shown in FIG. 4, first and second NAND cells are connected to latch 0, latch 1, latch 2,... Respectively, and the gates are connected to select lines SG ₁ ', S ₁ .
One of the first and second NAND cells is selected by a selection transistor connected to G ₂ ′. The role of the selection transistor whose gate is connected to the selection lines SG ₁ and SG ₂ is the same as in FIG.

For example, cells connected in series to the first NAND cell of the latch 0 are denoted as M _{1,1 to} M _4,1 ,..., And cells whose control gates are connected to the same word line WL _{2 Are} defined as M _{2,1 to} M _2,6,. here,
For example, M _2,2 is one of the cells included in the second NAND cell of the latch 0.

At this time, writing and reading are performed by M _2,1 , M ₂ , ₁ belonging to the first NAND cell corresponding to one page.
M _2,3 , M _2,5 , ... or M _2,2 , M _2,4 , M _2,6 ,
…, Are performed as a unit. In such a page-based write, for example, M _2,1 , M belonging to the first NAND cell of latch 0, latch 1, latch 2,...
_{After the} overwriting of any of ₂ , ₃ , M _2,5 ,... Is detected by the circuits shown in FIGS. 1 and 2, the same word line shown in FIG. by performing the collective erasure of all the cells connected to WL _2, M _{2, 2} belonging to the second NAND type cell which is not the subject of the page _{write, M 2,4, M 2,6, ...} , a page of Are also erased at the same time.

Since the memory data erasing operation performed here is performed at a different time from the writing operation, the memory data erased by the erasing operation may not be stored anywhere. Therefore, M _2,2 , M belonging to the second NAND type cell connected to the same word line
The memory data of the pages _2,4 , M _2,6 ,... _Are once saved to latches 0 to 2,.
Erases operation of L _2, belonging subsequent memory data stored in the latch to the second NAND type cell M
_{2,2, M 2,4, M 2,6,} ..., again written to, it may be finished writing operation upright overerasing flag from the output of the read circuit of excess write shown in FIG.

Data saving and rewriting are performed as follows. That is, in FIG. 1, after the node a of the latch is set to "H", the signal A is set to "H" and the signal B is set to "L", the memory data to be saved via Q ₂ and Q ₄ is read, and the C and "H", it is sufficient to re-write load data to a bit line via the Q _7.

Next, a fourth embodiment of the present invention will be described with reference to FIG. As described earlier with reference to FIG.
When writing to cell B, erroneous writing is performed on unselected cells C connected to the same word line, and even when the threshold value of cell C changes, this is detected and an erroneous writing flag is set. It is desirable. If the erroneous write state can be detected using the circuit of FIG. 1, the erroneous write flag can be output by the circuit of FIG.

Here, the erroneously written cell is indicated by a circle in FIG.
Assume that it has a threshold like a mark. In the case of erroneous writing, the threshold value is lower than that of cells to which normal writing has been performed (these cells have a higher threshold value than the word line level at which verification has been performed after writing), but 0 V (selected word line voltage). ), The erroneous data is read.

A method for detecting an erroneous write after writing is as follows. In FIG. 1, the nodes b of all the latches are set to "L". This corresponds to the state after normal write verification. Next, after precharging the bit lines, the signal A is set to “H”, the signal B is set to “L”, the selected word line is set to 0 V, and the read operation is performed via Q ₂ and Q ₄ . At this time, the latch b corresponding to the write cell and the erroneous write cell is inverted to “H”.

[0067] Then the following verify level writes the selected word line, and, as a highly erroneous write detection level than the threshold of the erroneous write cell, the signal B and "H", the _{A "L", Q 2,} Q _The read operation is performed again via ₃ . By doing so, the node b of the latch corresponding to the write cell is inverted to "L", so that only the node b of the latch corresponding to the erroneous write cell is maintained at "H". This state can be externally monitored in the same manner as described with reference to FIGS. The present invention is not limited to the above embodiment. In addition, various modifications can be made without departing from the spirit of the present invention.

[0068]

Conventionally, after a user writes to a non-volatile semiconductor memory device, until the user attempts to read out the cell in which the writing has been performed and other cells affected by the abnormal threshold value of the cell, It was unknown whether the memory data was destroyed.

As described above, according to the nonvolatile semiconductor memory device of the present invention, if, for example, after writing data, the mode of monitoring the writing state is set and the status of the chip is output from an external terminal, no erroneous writing or abnormality occurs. Since the value change can be monitored, the user can cope with this. Further, the same effect can be expected with respect to erroneous writing to another cell which occurs when writing to a cell.

Further, by taking measures such as collectively erasing cells connected to the same word line as the cell in which the overwriting or erroneous writing has been detected, it is possible to inform the user of a writing defect and to make a write error. Data corruption in other cells can be prevented, and the user can more easily address these issues.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a latch circuit of the present invention.

FIG. 2 is a diagram showing a read circuit for overwriting and erroneous writing according to the present invention.

FIG. 3 is a diagram showing a bias method in batch erase according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a NAND-type nonvolatile memory cell array according to a third embodiment of the present invention.

FIG. 5 is a diagram showing threshold values of erroneously written cells according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a bias method in writing in a conventional nonvolatile memory cell.

FIG. 7 is a diagram showing a bias method in erasing a conventional nonvolatile memory cell.

FIG. 8 is a diagram showing a threshold distribution in writing and erasing of a conventional nonvolatile memory cell.

FIG. 9 is a diagram showing a configuration of a conventional NAND type nonvolatile memory cell array.

FIG. 10 is a diagram showing a bias applied to cells A and B in the vicinity of a conventional write cell B;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 source / drain diffusion layer 3 channel 4 thin insulating film 5 floating gate 6 insulating film 7 control gate 10 AND gate 20 RS flip-flop 30 multiplexer Q ₁ , Q ₈ PMOS _{Q 2 ~Q 7 ... NMOS I 1} , I 2 ... inverter _{SG 1, SG 2, SG 1} ', SG 2' ... select lines WL ₁ to WL ₄ ... word lines BL ₀ to BL ₂ ... bit lines M _{1, 1} ~ M _4,1 , M _2,1 ~ M _2,6 ... memory cells

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B025 AA03 AB01 AC03 AD03 AD04 AD05 AD08 AE08 AE09 5F001 AA25 AB08 AC02 AD12 AE02 AE08 AF06 5F083 EP02 EP23 ER03 ER09 ER14 ER19 ER21 GA15 GA21 GA30 LA10 LA12 LA16

Claims (5)

[Claims] 1. A memory cell for storing information according to a change in a threshold value, a detecting means for detecting an excessive change in the threshold value of the memory cell, a storing means for storing a result detected by the detecting means, A circuit for reading out the storage state stored in the storage means to the outside. 2. After the excessive threshold value change of the memory cell is detected by the detecting means, the excessive threshold value change is selectively or collectively applied to the memory cells having the excessive threshold value change. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a bias voltage causing a threshold change in a direction opposite to that of the bias voltage is applied. 3. An over-write detection after writing to the memory cell connected to the same word line, wherein when an excessive threshold value change of the memory cell is detected by the detection means, the same word line is detected. 2. The nonvolatile semiconductor memory device according to claim 1, wherein all the memory cells connected to the nonvolatile semiconductor memory are erased. 4. The memory cell connected to the same word line is configured to perform writing by dividing into a plurality of memory cell groups, and after the overwriting after the writing is detected by the detecting means, Means for temporarily saving memory data of a memory cell group that is connected to the same word line and that is not targeted for writing, after batch-erasing the plurality of memory cell groups connected to the same word line, 4. The nonvolatile semiconductor memory device according to claim 3, wherein the temporarily saved memory data is written again to the memory cell group not to be written. 5. A memory cell for storing information according to a threshold value change, another memory cell which simultaneously changes a threshold value by a storage operation which causes the memory cell to change a threshold value, and the other memory cell Detecting means for detecting a change in the threshold value, a storing means for storing a result detected by the detecting means, and a circuit for reading out a storage state stored in the storing means to the outside. Nonvolatile semiconductor memory device.